JPS596063B2 - How to form multilayer wiring - Google Patents
How to form multilayer wiringInfo
- Publication number
- JPS596063B2 JPS596063B2 JP54139136A JP13913679A JPS596063B2 JP S596063 B2 JPS596063 B2 JP S596063B2 JP 54139136 A JP54139136 A JP 54139136A JP 13913679 A JP13913679 A JP 13913679A JP S596063 B2 JPS596063 B2 JP S596063B2
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- film
- wiring
- layer
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置における多層配線、特に金属膜に
よる多層配線の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming multilayer wiring in a semiconductor device, and particularly to a method for forming multilayer wiring using a metal film.
従来のこの種の多層配線の形成方法を第１図ａ〜ｃに示
してある。A conventional method for forming this type of multilayer wiring is shown in FIGS. 1a-c.
すなわち、まず同図ａにみられるように、シリコン半導
体基板１上に酸化珪素膜２を形成した上で、この膜２上
に公知の写真製版技術により第１層目のアルミ配線層３
、４を形成させ、ついでこれにプラズマデポジション法
などにより、低温で窒化硅素膜５を層間絶縁膜として形
成し、これに同図ｂで示すように、同様の写真製版技術
によりフォトレジスト６をマスクとしてコンタクトホー
ルＴを開口させ、さらにこのフォトレジスト６を除去し
たのち、同図ｃのように第２層目のアルミ配線層８を形
成するのである。しかし乍らこのように構成される従来
の多層配線では、第２層アルミ配線層８のアルミが、層
間絶縁膜である窒化硅素膜５の中に拡散して、第１層ア
ルミ配線層８と短絡し、層間絶縁不良を生ずるという欠
点があつた。すなわち、第２図ａは２層アルミ形成後の
表面から深さ方向へのアルミ、窒化硅素などの濃度分布
を示しており、２層アルミ形成直後は窒化硅素膜とアル
ミ膜とが分離しているが、第２図ｂにみられるように、
４５０℃で３０〜６０分間のアルミジッターを行なつた
後は、第２層アルミが窒化硅素膜中へ深く拡散し、第１
層アルミと短絡を生じている。この発明は従来のこのよ
うな欠点を改善するため、層間絶縁膜と第２層配線金属
層との間に安定な絶縁膜を形成して、層間短絡のない多
層金属配線を得ようとするものである。That is, as shown in FIG. 1A, first, a silicon oxide film 2 is formed on a silicon semiconductor substrate 1, and then a first aluminum wiring layer 3 is formed on this film 2 by a known photolithography technique.
. After opening a contact hole T as a mask and removing the photoresist 6, a second aluminum wiring layer 8 is formed as shown in FIG. However, in the conventional multilayer wiring configured in this way, the aluminum of the second aluminum wiring layer 8 diffuses into the silicon nitride film 5, which is an interlayer insulating film, and is mixed with the first aluminum wiring layer 8. The drawback was that short circuits occurred, resulting in poor interlayer insulation. In other words, Figure 2a shows the concentration distribution of aluminum, silicon nitride, etc. in the depth direction from the surface after two-layer aluminum is formed. Immediately after forming two-layer aluminum, the silicon nitride film and aluminum film are separated. However, as shown in Figure 2b,
After performing aluminum jitter at 450°C for 30 to 60 minutes, the second layer of aluminum diffuses deeply into the silicon nitride film, and the first layer of aluminum diffuses deeply into the silicon nitride film.
A short circuit has occurred with the aluminum layer. In order to improve these conventional drawbacks, this invention aims to form a stable insulating film between an interlayer insulating film and a second-layer wiring metal layer to obtain multilayer metal wiring without interlayer short circuits. It is.
以下、この発明方法の一実施例につき、第３図ａ−ｆを
参照して詳細に説明する。Hereinafter, one embodiment of the method of this invention will be described in detail with reference to FIGS. 3a-f.
この実施例においても同図Ａ，ｂに示すように、ンリコ
ン半導体基板１上に酸化硅素膜２を形成したのち、この
膜２上に第１層目のアルミ配線層３，４および窒化硅素
膜５を順次に形成させ、かつ窒化硅素膜５にフオトレジ
スト６を用いて、選択的にコンタクトホール７を開口さ
せ、このフオトレジスト６を除去するまでは前記従来例
と同様に行なわれる。In this embodiment as well, as shown in FIGS. A and b, a silicon oxide film 2 is formed on a silicon semiconductor substrate 1, and then a first aluminum wiring layer 3, 4 and a silicon nitride film are formed on this film 2. 5 are sequentially formed, contact holes 7 are selectively opened using a photoresist 6 on the silicon nitride film 5, and the photoresist 6 is removed in the same manner as in the conventional example.
ついでその後、前記コンタクトホール７を含む窒化硅素
膜５の部分に、同図ｃにみられるとおり再度フオトレジ
スト６１をパターニングした上で、同図ｄのように、ア
ルミターゲツトを酸素ガスでスパツタすることにより、
これらの窒化硅素膜５およびパターニングしたフオトレ
ジスト６１上に、酸化アルミ膜９，１０を薄く形成させ
、続いてフオトレジスト６１とその上の酸化アルミ膜１
０をリフトオフ法により除去して、同図ｅに示すように
、コンタクトホール７とその開口部周辺を除く窒化硅素
膜５上に、絶縁膜としての酸化アルミ膜９を得たのち、
同図ｆのように第２層目のアルミ配線層８を形成するの
である。すなわち、このようにして、層間絶縁層である
窒化硅素膜５と第２層アルミ配線層８との間に酸化アル
ミ層９を形成したので、第２層アルミ配線層８の窒化硅
素膜５への拡散を防止でき、結果的に第１層、第２層ア
ルミ配線層３，８間の短絡を阻止し得るのである。なお
前記実施例では、コンタクトホール部の酸化アルミ膜の
除去方法として、リフトオフ法を用いたが、通常の写真
製版技術によりレジスタパターンを形成し、三酸化クロ
ムとリン酸混合液などで酸化アルミ膜を選択的に除去し
てもよく、また酸化アルミ膜の形成方法としては、別に
酸化アルミのターゲツトをアルゴンなどの不活性ガスを
使つてスパツタする方法、あるいはアルミ膜を形成後に
、陽極酸化法などで酸化させる方法であつて差支えなく
、さらに酸化アルミ膜に代えて、酸化硅素膜、あるいは
チタン・ハフニウムなどの金属酸化膜を用いても良い。Thereafter, a photoresist 61 is patterned again on the portion of the silicon nitride film 5 including the contact hole 7, as shown in FIG. According to
Thin aluminum oxide films 9 and 10 are formed on the silicon nitride film 5 and the patterned photoresist 61, and then the photoresist 61 and the aluminum oxide film 1 thereon are formed.
0 by a lift-off method to obtain an aluminum oxide film 9 as an insulating film on the silicon nitride film 5 except for the contact hole 7 and the area around its opening, as shown in FIG.
A second aluminum wiring layer 8 is formed as shown in FIG. That is, since the aluminum oxide layer 9 was formed between the silicon nitride film 5, which is an interlayer insulating layer, and the second aluminum wiring layer 8 in this way, the silicon nitride film 5 of the second aluminum wiring layer 8 As a result, short circuit between the first and second aluminum wiring layers 3 and 8 can be prevented. In the above example, the lift-off method was used as a method for removing the aluminum oxide film in the contact hole portion, but a register pattern was formed using ordinary photolithography technology, and the aluminum oxide film was removed using a mixed solution of chromium trioxide and phosphoric acid. Alternatively, the aluminum oxide film can be formed by sputtering an aluminum oxide target using an inert gas such as argon, or by anodizing after forming the aluminum film. Further, in place of the aluminum oxide film, a silicon oxide film or a metal oxide film such as titanium or hafnium may be used.
以上詳述したようにこの発明によるときは、配線金属層
と層間絶縁膜との間に安定な絶縁膜を介在して形成した
ので、層間絶縁不良のない多層金属配線を得ることがで
きるものである。As detailed above, according to the present invention, since a stable insulating film is interposed between the wiring metal layer and the interlayer insulating film, a multilayer metal wiring without interlayer insulation defects can be obtained. be.
第１図ａ−ｃは従来例による多層金属配線の形成方法を
工程順に示す断面図、第２図Ａ，ｂは同上金属配線の窒
化硅素膜への拡散状態を示す説明図、第３図ａ−ｆはこ
の発明に係わる多層金属配線の形成方法の一実施例を工
程順に示す断面図である。
１・・・・・・シリコン半導体基板、２７・・・・・酸
化硅素膜、３，４・・・・・・第１層アルミ配線層（金
属配線層）、５・・・・・・窒化硅素膜（層間絶縁膜）
、６・・・・・・フオトレジスト、７・・・・・・コン
タクトホール、８・・・・・・第２層アルミ配線層、９
，１０・・・・・・酸化アルミ膜（安定な絶縁膜）。Figures 1a-c are cross-sectional views showing the conventional method for forming a multilayer metal wiring in the order of steps, Figures 2A and b are explanatory diagrams showing the state of diffusion of the same metal wiring into the silicon nitride film, and Figure 3a. -f is a cross-sectional view showing an embodiment of the method for forming a multilayer metal wiring according to the present invention in the order of steps. 1...Silicon semiconductor substrate, 27...Silicon oxide film, 3, 4...1st layer aluminum wiring layer (metal wiring layer), 5...Nitriding Silicon film (interlayer insulation film)
, 6...Photoresist, 7...Contact hole, 8...Second aluminum wiring layer, 9
, 10... Aluminum oxide film (stable insulating film).
Claims (1)
を順次に形成させる多層配線において、層間絶縁膜への
配線金属の拡散を阻止するために、これらの層間絶縁膜
と配線金属層との間に、安定な絶縁膜を形成する工程を
含むことを特徴とする多層配線の形成方法。 ２ 配線金属層にアルミを、層間絶縁膜に窒化硅素を、
安定な絶縁膜に酸化アルミを各々用いることを特徴とす
る、特許請求の範囲第１項記載の多層配線の形成方法。[Claims] 1. In a multilayer wiring in which a first wiring metal layer, an interlayer insulating film, and a second wiring metal layer are sequentially formed, in order to prevent the wiring metal from diffusing into the interlayer insulating film, A method for forming a multilayer interconnection comprising a step of forming a stable insulating film between an interlayer insulating film and a metal interconnection layer. 2 Aluminum is used for the wiring metal layer, silicon nitride is used for the interlayer insulation film,
A method for forming a multilayer wiring according to claim 1, characterized in that aluminum oxide is used for each of the stable insulating films.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54139136A JPS596063B2 (en) | 1979-10-25 | 1979-10-25 | How to form multilayer wiring |
| US06/184,171 US4381595A (en) | 1979-10-09 | 1980-09-04 | Process for preparing multilayer interconnection |
| DE3033513A DE3033513C2 (en) | 1979-10-09 | 1980-09-05 | Process for the production of an aluminum-containing conductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54139136A JPS596063B2 (en) | 1979-10-25 | 1979-10-25 | How to form multilayer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5661146A JPS5661146A (en) | 1981-05-26 |
| JPS596063B2 true JPS596063B2 (en) | 1984-02-08 |
Family
ID=15238369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54139136A Expired JPS596063B2 (en) | 1979-10-09 | 1979-10-25 | How to form multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596063B2 (en) |
-
1979
- 1979-10-25 JP JP54139136A patent/JPS596063B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5661146A (en) | 1981-05-26 |
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