JPS596084B2 - Timer setting value setting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital timer set value setting device suitable for use in a program storage type sequence control device.

There are various types of digital timers, but the clock pulses are counted by a counter based on the timer activation signal, this counted value is compared with the set value, and when the time elapses, the counted value of the counter and the set value match. Therefore, it is common to use this method to obtain a time signal.

Since the above-mentioned sequence control device operates on a time-division basis, this is utilized to allow one counter to be shared by a plurality of timers. In other words, this type of sequence control device stores a sequence program in a program storage device, reads out this program in a cyclical manner, and an arithmetic processing unit executes this program in sequence and controls it to a predetermined state according to input conditions. It controls the object. Therefore, operation instructions for each of the plurality of timers are stored in the program storage device. A timer setting value storage device is installed to store the setting values of each of the plurality of timers at each address. When the timer operation instruction is read from the program storage device, the arithmetic processing unit determines the presence or absence of the reference clock pulse signal, and updates the contents of the counter based on the result of this determination, or stores the contents of the counter in the data storage device without updating. Store it in a predetermined location as a timer elapsed value. Furthermore, when the program completes one cycle and this timer operation command is read, the elapsed value stored in a predetermined location of the data storage device is set in the counter, and when the reference clock pulse signal is applied, this elapsed value is updated. Its contents are again stored at a predetermined location on the data storage device. After inputting a start signal for each timer, the arithmetic processing unit sequentially and cyclically executes the above operations for each timer according to the program, and updates the elapsed value of each timer. At the same time, when the timer operation command is read, the timer setting value specified by this command is read from the setting storage device, and this content is compared with the content set in the counter. Outputs a time signal. Since the program execution cycle is extremely short compared to the reference clock pulse signal cycle, this allows one counter to be shared by multiple timers, and is equivalent to multiple timers operating in parallel. It is said that it becomes. Furthermore, since the program execution period is extremely short compared to the period of the reference clock pulse signal, there is a possibility that one clock pulse signal will be counted for each timer operation command. Therefore, in this type of timer, the circuit is constructed so that one clock pulse signal counts only once.
Furthermore, in this type of timer, the number of bits in the counter is determined in advance.

Therefore, the upper limit to which the timer can be set is determined by the period of the reference clock signal. Therefore, in the past, counters with a limited number of bits were provided with multiple reference clock pulse signals of different periods in order to enable longer time settings, and the reference clock pulse signals could be arbitrarily selected by a timer operation command. It is structured as follows. That is, for example, if the setting range of the counter is from "0" to "99", and the reference clock pulse signal is provided with a period of 0.1 [seconds] and a period of 1 [second]. , if a reference clock pulse signal with a cycle of 0.1 [seconds] is selected, the upper limit of the counter setting is 9.9 [seconds], and if a reference clock pulse signal with a cycle of 1 [second] is selected, the upper limit of the counter setting is 9.9 [seconds]. It becomes [seconds].

When executing one timer operation command, which reference clock pulse signal among a plurality of reference clock pulse signals is used to update the contents of the counter is stored in the timer setting value storage device together with the setting value. That is, each address of the timer setting value storage device stores a timer setting value and selection information for selecting a desired reference clock pulse signal from among a plurality of reference clock pulse signals. Then, the arithmetic processing unit simultaneously reads the setting value and selection information from the timer setting value storage device, and updates the counter with the reference clock pulse signal designated by the selection information. However, the timer device configured as described above uses a reference clock pulse signal with a long period, which occurs due to digital errors, to operate over a relatively long period of time, depending on the setting value and the selection of the unit clock pulse signal. There is a risk that a contradictory phenomenon may occur in which the set timer times up earlier than the timer set to a relatively short time due to the reference clock pulse signal having a short cycle.

That is, this will be explained as follows with reference to FIG. Now, there are two timers with setting ranges from "O" to "99", and the first timer TMl inputs the reference clock pulse signal P, with a period of 0.1 [seconds], and the setting value is "97'', that is, the setting time is 9.7 seconds.
It is assumed that the second timer TM2 inputs the reference clock pulse signal P2 having a period of 1 [second], and that the set value is "10", that is, the set time is 10 [seconds]. And the first
Assume that the second timers TMl and TM2 are simultaneously started at time T1 as indicated by a starting signal S. Since the sequence control device operates on a time-sharing basis, the first and second
Although the timers TM, TM2 do not start at the same time, since the time it takes to execute one cycle of the program is extremely short compared to the reference clock pulse signal, it is safe to assume that they start almost at the same time. Therefore, if these timers start at the same time, the first timer TMl receives the 97th pulse from the starting time T, and times up at time T4, but the second timer TML
M2 receives a clock pulse that has elapsed for 1 [second] at time T2, which is 0.4 [seconds] after starting time t1, and as a result, the second timer TM2 times up at time T3, which is earlier than time T4. . That is, even though two timers are started at the same time, the timer set to a relatively long time ends up timing up earlier than the timer set to a relatively short time. In sequence control, the starting order of operations becomes a problem, and if the above-mentioned inconvenience occurs to such a controlled object, it may lead to a serious accident.

The reason why such a contradictory phenomenon occurs is that the set value of a timer using a reference clock signal with a short period falls within the digital error of a timer using a reference clock signal with a long period.

That is, the time until time-up of the timer using the reference clock pulse signal with period T1 is t1, and the set value is m1.
If the time up to time-up of the timer using the reference clock pulse signal with period T2 is T2, the set value is M2, and T1<T2, then m1・T1<M2・T
2, the range shown by equation (1) overlaps with the range shown by equation (2).

The present invention has been made in view of the above points, and by limiting the setting range for each reference clock pulse signal and preventing the setting ranges from overlapping, multiple timers can be started almost simultaneously. If the timer set to a relatively short time always times up before or at the same time as the timer set to a relatively long time, the setting value of each timer and selection information of the reference clock pulse signal are determined and stored. However, it is an object of the present invention to provide a timer setting value setting device that can eliminate the above-mentioned disadvantages.

In order to achieve the above object, the present invention is characterized in that at least a reference data storage means sets the set upper limit value for each reference clock pulse signal of a plurality of reference clock pulse signals with different periods in order from the reference clock pulse signal with the shortest period. a reference data output means that is stored in advance at each address of , inputs a step pulse signal, and sequentially outputs the set upper limit value and selection information for selecting the reference clock pulse signal corresponding thereto; and inputs the selection information. death,
A period generation means for outputting the period of the reference clock pulse signal specified by this information, a time setting value and the period from the period generation means are input, the time setting value is divided by the period, and the quotient is output. a dividing means that inputs and compares the set upper limit value and the quotient, outputs a first control signal when the set upper limit value is greater than or equal to the quotient, and otherwise outputs a second control signal; a comparison means for outputting a control signal; a timer setting value storage means having a setting value storage area and a selection information storage area at each address; write control means for writing the quotient from the dividing means as a set value and the selection information from the reference data output means at the address specified by the reference data output means; step control means for stopping application of the step pulse signal to the data output means and applying the step pulse signal to the reference data output means in response to the second control signal; The set upper limit value M for each reference clock pulse signal
xi is the longest one, where Ti is the period of the reference clock pulse signal, Ti+1 is the period of the reference clock pulse signal with the next longest period after this reference clock pulse signal, and Mii+1 is the predetermined lower limit value. The timer setting value setting device is characterized in that the setting upper limit value for a reference clock pulse signal having a period is arbitrary.

An embodiment of the present invention shown in FIG. 2 will be described below. 1 is a reference data output means, 2 is a cycle generation means, 3 is a division means, 4 is a comparison means, 5 is a timer setting value storage means, 6
7 is a write control means, and 7 is a step control means.

The reference data output means 1 includes a reference data storage device 10 and an address counter 11 that counts the step pulse signal a, scans and designates each address of the reference data storage device 10 based on the count contents, and sequentially reads out the reference data. It consists of Each address of the reference data storage device 10 includes an area for storing selection information STi for selecting any one of a plurality of reference clock pulse signals, and an area for storing a set upper limit value Mxi of the reference clock pulse signal. Here, the upper limit value for each reference clock pulse signal is determined as follows. That is, in equations (1) and (2) above, in order for the range shown by equation (1) to not overlap with the range shown by equation (2), the following must be true.

That is, when using a plurality of reference clock pulses with different periods, the period of one reference clock pulse signal is Ti, and the upper limit of the setting range of the reference pulse signal is Mx.
If the lower limit value of il is Mii, the period of the reference clock pulse signal with the next longest period after the reference clock pulse signal with this period Ti is Ti+1, and the lower limit value of the setting range of the reference clock pulse signal is Mii+1, then the setting range of each reference clock pulse signal is If the upper limit value Mxi is set, the setting ranges of the respective reference clock pulse signals do not overlap. Here, the set lower limit value Mii of each reference clock pulse signal may be set arbitrarily, but it is generally preferable to determine it based on the error allowed by the timer device. The setting upper limit value Mxi for each reference clock pulse signal determined in advance in this way is written to each address of the setting value storage device 10 in order from the one with the shortest cycle to the one with the shortest cycle, along with the predetermined selection information STi. Reference numeral 12 denotes this writing device, which is composed of a keyboard and the like.

Figure 3 shows the selection information STi and the setting upper limit value M for the reference clock pulse signal with periods of 0, 1 [seconds], 1 [seconds], and 10 [seconds] when the setting range is from 0 to 99.
This shows a specific example of xi, which is written to each address ADD of the reference data storage device 10. In this figure, the set lower limit value Mii does not need to be written in the reference data storage device 10, but is shown for reference. In addition, (0.1), (1), and (10) are selection information Sl
, S2, and S3 are information for selecting reference clock pulse signals with periods of 0.1 [seconds], 1 [seconds], and 10 [seconds]. The upper limit value of the reference clock pulse signal having the longest period may be set arbitrarily, but in this case, the maximum value of the setting range is written. The lower limit setting value of the reference clock pulse signal having the shortest period is necessarily the minimum value of the setting range. The period generating means 2 inputs the selection information STi from the reference data storage device 10, and generates the period T1 of the reference clock pulse signal designated by this information STi. 13 is a setting device for setting the set time of the timer, and the dividing means 3 inputs the time value b from the setting device 13 and the period T1 from the period generating means 2, and converts the time value b into the period Tl.
Divide by , discard the remainder, and output only the quotient c.

This quotient c becomes a set value. The comparison means 4 inputs the set upper limit value Mxi from the reference data storage device 10 and the set value c from the dividing means 3, compares the two, and only when the set upper limit value Mxi is greater than or equal to the set value c, a logical ``O
", and in other cases, outputs a logical "1" signal. Each address of the timer setting value storage means 5 includes an area for storing selection information STi for selecting any one of a plurality of reference clock pulse signals, and an area for storing a setting value c for the reference clock pulse signal. Reference numeral 14 denotes an address setter for setting a write address of the timer setting value storage means 5 into which the selection information STi and the setting value c are written.

The write control means 6 includes a NOT circuit 15 and gate circuits 16 and 17.
, and a control circuit 18. And comparison means 4
The output from the inverter is input to the inverting circuit 15. The output of the NOT circuit 15 is input to the control terminals of the gate circuits 16 and 17 and the control circuit 18. Gate circuits 16 and 17 are negative circuits 1
The gate is opened only when the output of 5 is logically [1], and the set value c and the selection information STi from the reference data storage device 10 are input to the timer set value storage means 5. Since the output of the NOT circuit 15 is logically "1", the control circuit 18 transfers the set value input via the gate means 16 to the address specified by the address setter 14 of the timer set value storage means 5. c and the selection information ST! input through the gate means 16.The step control means 7 is composed of an AND gate circuit 19 and a step pulse generator 20, and the control terminal of the AND gate circuit 19 The output from the comparing means 4 is input to the step pulse generator 20, and the inverting circuit 1 is input to the step pulse generator 20.
Input the output of 5. PB is a pushbutton switch for applying the starting signal STAT, and the stepping pulse generator 20 receives this starting signal STAT and oscillates the stepping pulse signal a at fixed time intervals, so that the output of the NOT circuit 15 is logically Oscillation is stopped when the signal becomes "L". AND gate circuit 1
Reference numeral 9 opens a gate when the output of the comparison means 4 is logically "1", and inputs the step pulse a from the step pulse oscillator 20 to the address counter 11.
The start signal STAT from the pushbutton switch PB is also applied to the clear terminal CL of the address counter 11. Hereinafter, when the data shown in FIG. 3 is written to addresses 0, 1, and 2 of the reference data storage device 10, 9.7 [seconds] is set to the first timer TMl as shown in FIG. The operation will be described in the case where the second timer TM2 is set to 10 [seconds].

It is assumed that the setting value C of the first and second timers TM and the selection information STi are stored at addresses 1 and 2 of the timer setting value storage means 5. First, the setting operation of the first timer TMl is as follows. That is, a set time value of 9.7 [seconds] is set in the setter 13, and an address l is set in the address setter 14. When this is completed, press pushbutton switch PB. By applying the start signal STAT, the address counter 11 is cleared, and this address counter 11 specifies the O address of the reference data storage device 10 and selects the selection information STi.
S1 is output as the setting upper limit value Mxi, and "90" is output as the set upper limit value Mxi. The period generating means 2 inputs the selection information S1 and generates the period "
0.1" is output. The dividing means 3 divides the set time value "9.7" from the setter 13 by the cycle "0.1" and outputs "97" as the set value C. The comparison means 4 compares the set upper limit value "90" with the set value "97", but since the conditions are not met, it logically outputs a signal of "1".
Therefore, the output of the NOT circuit 15 becomes logically "O", the gate circuits 16 and 17 close their gates, and the control circuit 1
8 also does not perform write control. Since the output of the comparison means 4 is logically "l", the AND gate 19 opens the gate. When the step pulse generator 20 outputs the step pulse signal a after a certain period of time after the start signal STAT is applied, the address counter 11 outputs the step pulse signal a because the gate of the AND gate circuit 19 is open. signal a
Count and specify address 1. As a result, the reference data storage means 10 outputs S2 as the selection information STi and "90" as the set upper limit value Mxi. Then, the period generating means 2 outputs the period "1", and the dividing means 3 outputs "9.7".
Divide by "1" and output the set value "9". this is,
Since the conditions of the comparison means 4 are satisfied, the comparison means 4 logically outputs a signal of "0". As a result, gate circuit 1
6 and 17 open the gates, and the control circuit 18 opens the address setter 1.
9 is written as the setting value C and S1 is written as the selection information STl in address 1 of the timer setting value storage means 5 set to 4. Since the output of the comparing means 4 is logically "O" and the output of the NOT circuit 15 is logically "1", the AND gate circuit 19 closes the gate and the stepwise pulse generator 2
0 stops oscillation. As described above, the setting value C of the first timer TMl and the selection information STi are stored in the timer setting value storage means 5. Next, the setting operation of the second timer TM2 is as follows. That is, the set time value 1 is set in the setter 13.
0 [seconds], set the address 2 in the address setting means 14, and press the pushbutton switch PB. As before, the address counter 11 is cleared and the address O of the reference data storage means 10 is designated. The setting value C, which is the output of the dividing means 3, is "100", which does not satisfy the condition of the comparing means 4, so the setting value "100" and the selection information S1 are not written into the timer setting value storage means 5. Instead, the address counter 11 receives the step pulse signal a from the step pulse generator 20 and specifies the second address. Then, the output of the dividing means 3 becomes "10", and the setting upper limit value Mxi becomes "9".
0'', this satisfies the condition of comparison means 4,
In the same manner as described above, "10" is written as the setting value C and S2 is written as the selection information STi at address 2 in the timer setting value storage means 5, as shown in FIG. That is, the first
1. The second timers TM, TM2 are both set to operate with a reference clock pulse signal with a cycle of 1 [second], and the set value C of the first timer TMl is "9", and the set value C of the second timer TM2 is "9".
The set value C is "10". Therefore, as shown in FIG. 1, if these timers TMl and TM2 are started almost simultaneously at time t1, the first timer TM, will time-up at time Ta, and the second timer TM2 will time-up at time T3. do. That is, a timer set to a relatively long time will time up later than a timer set to a relatively short time, and the inconvenience of the conventional system can be solved. That is, by doing the above, the range of time that can be set by each reference clock pulse signal of each period Ti is limited. That is, if the setting value for a period of 0.1 seconds is M, and the setting value for a period of 1 second is M2, the setting range is as follows.

Therefore, the maximum time allowed by equation (6) is set using a reference clock pulse signal with a period of 0.1 [seconds], and the minimum time allowed by equation (7) is set using a reference clock pulse signal with a period of 1 [second]. However, if these two timers are started at the same time, then from equations (1) and (2) above.

As is clear from this equation, the time ranges t1 and T2 do not overlap. Also, the above is a period of 0.1 [seconds]
The same thing can be said about the period 1 [second] and the period 10 [second]. Furthermore, for other periods,
It is obvious that there is no need to explain that if the set upper limit value is determined so as to satisfy equation (6), the result will be the same as described above. In the above embodiment, a case has been described in which a divider is used as the division means 3 and a comparator is used as the comparison means 4, but a computer or the like may be used for this part. Fifth
The figure shows an example of a flowchart in this case, in which the set time value b is input from the setter 13 in step P1, and the start signal STAT is input in step P2. In step P3, "O" is written to the register i set as the address counter 11, that is, register i is cleared.Then, in step P4, the set time value b is divided by the period Ti input from the period generating means 2. death,
The quotient, that is, the set value C is calculated. In step P5, the set upper limit value MXl input from the reference data output circuit 10 is compared with the set value C, and if the conditions are not satisfied, step P6
The contents of register i are incremented at step P4, and the process returns to step P4. If the conditions are satisfied in step P5, the set value C and the selection information STl from the reference data output means 10 are outputted in step P7, and the writing control means 6 is outputted in step P8.
The setting value C and the selection information STi are written into the timer setting value storage means 5, and the process ends at END. It will be clear from the above description that the purpose can be achieved even in this manner. Furthermore, in the above embodiments, the selection information STi for selecting any one of a plurality of reference clock pulse signals having different periods was also written in the reference data storage device 10 in advance. The output information of the address counter 11 may also be used. That is, the set upper limit values are stored in the reference data storage device 10 in order from the initial address of the reference clock pulse signal with the shortest period. Therefore, if the address information of the address counter 11, or information obtained by converting this information if necessary, is matched with the address assigned to each reference clock pulse signal in advance, and this is used as the selection information STi, Reference data storage device 10
There is no need to write selection information STi to. As is clear from the above explanation, the present invention limits the setting range for each reference clock pulse signal and prevents the setting ranges from overlapping, so that multiple timers are started almost simultaneously. In this case, the timer set to a relatively short time always times up before the timer set to a relatively long time, or in the worst case, the timer times up at the same time. This has great practical effects.

In addition, in the conventional method, the timer setting time value is divided into selection information for selecting a reference clock pulse signal of a predetermined period and the setting value, and the writing device directly writes the setting value into the timer setting value storage device, which makes the operation easy. In addition to being troublesome, there was a risk of incorrect settings. In this regard, in the present invention, if the time value is directly set, the setting value and selection information are automatically created and stored in the timer setting value storage device, so the operation is extremely simple and there is no possibility of incorrect settings. It is something that can drastically reduce sex.

[Brief explanation of drawings]

Fig. 1 is a time chart for explaining a conventional example and the present invention, Fig. 2 is a block wiring diagram showing an embodiment of the present invention, and Figs. 3 and 4 are a reference design device 10 and timer setting values. FIG. 5, which is a diagram showing an example of the capacity of the storage device 5, is a flowchart showing another aspect of the present invention 771. Standard data output means, 2; period generation means, seven comparison means, 5
; timer setting value UU control means, 7; step control means, control means.

Claims (1)

[Claims] 1 At least, the set upper limit values for each of the reference clock pulse signals of a plurality of reference clock pulse signals with different periods are stored in advance at each address of the reference data storage means in order from the reference clock pulse signal with the shortest period, and the step pulse signal is stored in advance at each address of the reference data storage means. a reference data output means for inputting and sequentially outputting the set upper limit value and selection information for selecting the corresponding reference clock pulse signal; and inputting the selection information and a period of the reference clock pulse signal specified by this information. a period generating means for outputting a time setting value and a period from said period generating means, a dividing means for inputting a time setting value and a period from said period generating means, dividing said time setting value by said period, and outputting the quotient; a comparison means for inputting and comparing a quotient and outputting a first control signal when the set upper limit value is greater than or equal to the quotient, and outputting a second control signal in other cases; a timer setting value storage means having a setting value storage area and the selection information storage area at an address; write control means for setting the quotient as a set value and writing this set value and the selection information from the reference data output means; and a write control means for writing the set value and the selection information from the reference data output means; write step control means for stopping the application of the step pulse signal and applying the step pulse signal to the reference data output means upon receiving the second control signal, the setting upper limit for each of the reference clock pulse signals; The value Mxi is such that Mxi≦(
Mii+_1-1) Ti+_1/Ti,
1. A timer setting value setting device, characterized in that the setting upper limit value for a reference clock pulse signal having the longest period is arbitrary.