JPS596104B2 - 2-phase PSK carrier wave regeneration circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on two-phase PSK (PhaseShiftKeyi).
ng) In a demodulator that receives a signal and reproduces data from this signal, a two-phase PSK that performs carrier wave recovery of the signal.
This relates to a carrier wave regeneration circuit.

Figure 1 shows the structure of a conventional two-phase PSK carrier wave regeneration circuit. Indicates completion. In the figure, 1 is an input terminal for a received two-phase PSK signal, 2 is a two-phase PSK carrier wave recovery circuit, and 3 is an output terminal for the recovered carrier wave. Next, the operation will be explained.

The two-phase PSK carrier wave recovery circuit 2 performs carrier wave recovery from ( ) on the two-phase PSK signal inputted from the input terminal 1 , and outputs the recovered carrier wave s ( ) to the output terminal 3 .

This two-phase PSK carrier wave recovery circuit performs carrier wave recovery based on the following principle.

To the received signal (to) to (to)■ ej(2πfot+φ
), (!) 610, 7l(1). Here f
o is the carrier frequency. When this signal is multiplied by 2 using a multiplier (not shown), (φε(O2
π), and 2φ=0m0q2π, so the multiplied signal q() becomes q()■[ni()]'=e2j(2
πfot+φ) = ej4πf0 (2).

Next, when this signal is input to a divider (not shown), its output becomes [q()] = e1X2, (j4ff0) - ej2πfo.

Therefore, the reproduced carrier wave s()■ cos2πf0(3) is obtained.

The conventional two-phase PSK carrier wave recovery circuit is configured as described above, so if the divider malfunctions due to noise, a cycle skip occurs in the output, and the phase of the recovered carrier wave changes by π. The reproduced carrier wave is s () ■ c
os (2πfo +π) = c0s2πfot.

In this case, the modulation power formula is CPSK (C
(herentPhaseShiftKeying) If the modulation power type is used, data after this point will be erroneously demodulated. As described above, the conventional two-phase PSK carrier wave recovery circuit has the disadvantage that cycle skips occur in the recovered carrier wave. This invention was made to eliminate the drawbacks of the conventional two-phase PSK as described above.
It is an object of the present invention to provide a two-phase carrier wave recovery circuit that can output a normal recovered carrier wave even when a cycle skip occurs by adding a new cycle skip suppression circuit to the carrier wave recovery circuit.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows the configuration of a two-phase PSK carrier recovery circuit according to the present invention, where 2 is a conventional carrier recovery circuit, 4 is a newly added cycle skip suppression circuit, and 5 is a recovered carrier output terminal. Further, FIG. 3 shows the configuration of the cycle skip suppression circuit 4, in which 6 is a delay circuit that delays the recovered carrier wave s(t) by a predetermined time, and 7 is a delay circuit that delays the recovered carrier wave s(t) and the delay circuit 6.
a phase detector that detects a phase difference with the output signal d(t) of
8 operates at the falling edge of the output signal p(t) of this phase detector 7, and by outputting an 'H' or 'L' signal, the signal 2 changes when a cycle skip occurs in the recovered carrier wave. A T flip-flop that outputs a value signal, 9 is this 'H
〃 or 'L'' signal ゞ+17 or 1-1 respectively
The comparator 10 associated with the comparator 9 is a multiplier that multiplies the output of the comparator 9 by the recovered carrier wave s(t). Here, it is assumed that the characteristics of the phase detector 7 are defined by the following relational expression.

It is also assumed that the delay time of the delay circuit 6 satisfies the relationship expressed by τ.

Here n is a positive integer. Next, the operation will be explained.

FIG. 4 shows a time chart of each signal waveform in the circuit configured as shown in FIG. First, consider a steady state without cyclopis skips. At this time, the phase difference between the signal s(t) and the signal d(t) is zero according to equation (5), so the output p(t) of the phase detector 7 is 1 as shown in equation (4). becomes. At this time, if the initial state of the T flip-flop 8 is HI, the output of the comparator 9 becomes '1', and the output signal c(t) of the multiplier circuit 10 becomes.

Next, when a cycle skip occurs in the signal s(t) at the time t=TO, the output of the delay circuit 6 becomes as shown in FIG.

Therefore, according to equation (4), the output p(t) of the phase detector 7 is as follows.

Also, at the time t=TO, the T flip-flop 8 detects the fall of the signal p(t), and its output changes from 'H' to '
At the same time, the output of the comparator 9 changes from '1' to -1. Therefore, the output signal c(t) of the multiplier circuit 10 becomes as follows.

In this way, even though a cycle skip has occurred in the recovered carrier wave s(t) at the time t=TO, the output signal c
Since the phase of (t) is the same as the phase of the recovered carrier wave s(t) before the cycle skip occurs, this means that the cycle skip can be suppressed. By the way, if the initial state of the T flip-flop 8 is SL'', the relationship between the reproduced carrier wave s(t) and the output signal c(t) will be expressed in place of equation (6), but this is not an essential problem.

This is because the recovered carrier wave s(t) has two states of phase uncertainty, O and π, with respect to the carrier wave of the received signal r(t), and whether Equation (6) or Equation (self) holds true. This is because the question of whether to do so is absorbed by this phase uncertainty. In the above embodiment, the characteristics of the phase detector 7 are expressed by the equation (
4), and the T flip-flop 8 was designed to detect the falling edge of the output p(t) of the phase detector 7, but this was replaced with one that detects the rising edge, and the signal is reproduced in the multiplier 10. It is also possible to input the output d(t) of the delay circuit 6 instead of the carrier wave s(t) to create a circuit configuration as shown in FIG.

It goes without saying that the flip-flop is not limited to the T flip-flop. Moreover, by applying the cycle skip suppression circuit according to the present invention not only to the two-phase PSK carrier wave recovery circuit but also to signal processing where cycle skips in the above sense are a problem, Effects similar to those of the embodiment can be obtained.

As described above, according to the present invention, since a cycle skip suppression circuit is added to the conventional two-phase PSK carrier wave regeneration circuit, it is possible to suppress cycle skips and output a recovered carrier wave with good characteristics. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a conventional two-phase PSK carrier wave regeneration circuit, FIG. 2 is a block circuit diagram of a two-phase PSK carrier wave recovery circuit according to an embodiment of the present invention, and FIG. Block circuit diagram of the block suppression circuit, Figure 4 a-e
is an operation waveform diagram thereof, and FIG. 5 is a block circuit diagram of another example of the cycle skip suppression circuit. 2...2-phase PSK carrier wave regeneration circuit, 4...
... Cycle skip suppression circuit, 6 ... Delay circuit, 7 ... Phase detector, 8 ... T flip-flop, 10 ... Multiplier.

Claims (1)

[Claims] 1. In a two-phase PSK carrier wave recovery circuit that recovers a carrier wave from a received two-phase PSK signal, a delay circuit that delays the phase of the recovered carrier wave for a predetermined period of time, and a phase of the output of this delay circuit and a phase of the recovered carrier wave are configured. a phase detector for comparative detection; a flip-flop that outputs a t-value signal that changes at the time when a cycle skip occurs in the recovered carrier wave due to the output of the phase detector or at a time delayed by the predetermined time from that time; 2, characterized in that it comprises a cycle skip suppression circuit that suppresses cycle skips of the reproduced carrier wave, and includes a multiplier that multiplies the output of the flip-flop by the reproduced carrier wave or the signal delayed by the predetermined time. Phase PSK carrier wave regeneration circuit.