JPS596531B2 - automatic frequency control device - Google Patents
automatic frequency control deviceInfo
- Publication number
- JPS596531B2 JPS596531B2 JP2252779A JP2252779A JPS596531B2 JP S596531 B2 JPS596531 B2 JP S596531B2 JP 2252779 A JP2252779 A JP 2252779A JP 2252779 A JP2252779 A JP 2252779A JP S596531 B2 JPS596531 B2 JP S596531B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- transmission
- signal
- output
- discriminator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/02—Automatic frequency control
- H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transmitters (AREA)
Description
【発明の詳細な説明】
本発明は、マイクロ波送受信機等において送信周波数を
目標周波数(パルス変調された受信信号の被変調周波数
)に所要の精度で合致させる自動周波数制御装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic frequency control device for matching a transmission frequency to a target frequency (modulated frequency of a pulse-modulated received signal) with required accuracy in a microwave transmitter/receiver or the like.
第1図は従来のこの種の装置の一例を示したものである
。FIG. 1 shows an example of a conventional device of this type.
図において、1はパルス変調されたマイクロ波信号等の
受信信号が印加されるミキサであつて、このミキサ1に
おいては受信信号の被変調周波数即ち目標周波数flと
送信周波数f2とが混合されて中間周波数1F(=f1
〜f2)をつくるようになつている。2は中間周波数1
Fを増幅する中間周波増幅器、3は中間周波増幅器2の
出力を検波する検波器、4は中間周波数1Fを電圧信号
に変換する周波数弁別器、5は周波数弁別器4から間欠
的に出力される電圧信号を増幅するパルス増幅器、6は
検波器3が出力を出しているときパルス増幅器5から出
されている電圧信号をキヤッチしてこれを所定時間保持
するサンプルホールド回路である。In the figure, reference numeral 1 denotes a mixer to which a received signal such as a pulse-modulated microwave signal is applied, and in this mixer 1, the modulated frequency of the received signal, that is, the target frequency fl, and the transmission frequency f2 are mixed and intermediated. Frequency 1F (=f1
~f2). 2 is intermediate frequency 1
3 is a detector that detects the output of the intermediate frequency amplifier 2; 4 is a frequency discriminator that converts the intermediate frequency 1F into a voltage signal; 5 is intermittently output from the frequency discriminator 4. The pulse amplifier 6 that amplifies the voltage signal is a sample hold circuit that catches the voltage signal output from the pulse amplifier 5 when the detector 3 is outputting and holds it for a predetermined time.
7は直流増幅器、8は閉ループ系が発振しないように抑
制するローパスのループフィルタ、9はドライバー、1
0はドライバー9に制御され電圧信号を周波数に変換し
て送信周波数f2をつくる電圧制御発振器である。7 is a DC amplifier, 8 is a low-pass loop filter that suppresses the closed loop system from oscillating, 9 is a driver, 1
0 is a voltage controlled oscillator that is controlled by the driver 9 and converts a voltage signal into a frequency to create a transmission frequency f2.
この送信周波数f2はミキサ1及び送信側に印加される
ようになつている。このような自動周波数制御装置の場
合には、温度変化等で基準となる周波数弁別器4の特性
が変動すると、その変動が送信周波数に加味されてしま
う欠点がある。This transmission frequency f2 is applied to the mixer 1 and the transmission side. In the case of such an automatic frequency control device, there is a drawback that if the characteristics of the frequency discriminator 4, which serves as a reference, fluctuate due to temperature changes or the like, the fluctuation is taken into account in the transmission frequency.
これを避けるためには周波数弁別器において安定度の優
れている非常に高価な部品を必要とする等の種々の欠点
があつた。本発明の目的は、周波数弁別器の特性に変動
が生じてもこれを補正できる自動周波数制御装置を提供
するにある。In order to avoid this, there were various disadvantages such as the need for very expensive parts with excellent stability in the frequency discriminator. SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic frequency control device that can compensate for variations in the characteristics of a frequency discriminator.
以下本発明の具体例を第3図にて詳細に説明する。A specific example of the present invention will be explained in detail below with reference to FIG.
図において、11はアンテナであつて、このアンテナに
はパルス変調された被変調周波数(目標周波数)がfl
の受信信号が受信され、且つこの日標周波数に合致する
ように制御された送信周波数f、の送信信号が送信され
るようになつている。12は送信信号と受信信号の通過
を制御するサーキユレータ、13はサブローカル周波数
がf3のサブローカル信号を発生する局部発振器、14
は送信周波数f2とサブローカル周波数f3とを混合し
てローカル周波数(F2+F3)のローカル信号を出力
するサブミキサである。In the figure, 11 is an antenna, and this antenna has a pulse-modulated frequency (target frequency) fl
A reception signal of f is received, and a transmission signal of a transmission frequency f, which is controlled to match this datemark frequency, is transmitted. 12 is a circulator that controls the passage of the transmitted signal and the received signal; 13 is a local oscillator that generates a sublocal signal with a sublocal frequency f3; 14
is a submixer that mixes the transmission frequency f2 and the sublocal frequency f3 and outputs a local signal of the local frequency (F2+F3).
15はメインミキサであつて、目標周波数f1とローカ
ル周波数(F2+F3)を混合し、又は送信周波数F2
とローカル周波数(F2+F3)を混合して中間周波数
FIFの中間周波信号を形成するようになつている。15 is a main mixer, which mixes the target frequency f1 and the local frequency (F2+F3), or mixes the transmission frequency F2.
and local frequency (F2+F3) to form an intermediate frequency signal of intermediate frequency FIF.
16は中間周波信号を増幅する中間周波増幅器、17は
増幅された中間周波信号の中間周波数FIFを電圧信号
に変換して出力する周波数弁別器である。16 is an intermediate frequency amplifier that amplifies the intermediate frequency signal, and 17 is a frequency discriminator that converts the intermediate frequency FIF of the amplified intermediate frequency signal into a voltage signal and outputs it.
この周波数弁別器17は、特に中心周波数がF3に選定
されていて、入力周波数がF3のとき出力電圧が零にな
る構造にされている。18は中間周波信号を検波する検
波器、19は検波出力をもとにして後述するように各部
の制御を行う制御回路である。This frequency discriminator 17 has a center frequency selected to be F3 in particular, and is structured such that the output voltage is zero when the input frequency is F3. Reference numeral 18 is a detector for detecting an intermediate frequency signal, and reference numeral 19 is a control circuit for controlling various parts based on the detection output as described later.
20は制御回路19に制御されて送信時にのみ周波数弁
別器17の電圧信号を記憶する送信時サンプルホールド
回路、21は制御回路19に制御されて周波数弁別器1
7から電圧信号が出されるたびに新たな電圧信号を受信
時のみ記憶する高速サンプルホールド回路である。Reference numeral 20 indicates a sample and hold circuit at the time of transmission, which is controlled by the control circuit 19 and stores the voltage signal of the frequency discriminator 17 only at the time of transmission; and 21, the frequency discriminator 1 which is controlled by the control circuit 19;
This is a high-speed sample-and-hold circuit that stores a new voltage signal only when receiving it every time a voltage signal is output from 7.
22は加算回路、23ば出力帰還用の第1のサンプルホ
ールド回路、24は出力帰還用の第2のサンプルホール
ド回路であつて、これらの3つの回路で受信時における
毎回の出力を入力側に戻して新たな入力に加算する動作
を繰返し行う人出力繰返し加算回路25を形成している
。22 is an adder circuit, 23 is a first sample-and-hold circuit for output feedback, and 24 is a second sample-and-hold circuit for output feedback. These three circuits input each output at the time of reception to the input side. A human output repetitive addition circuit 25 is formed which repeatedly performs the operation of returning the input data and adding it to a new input.
即ち、加算回路22は高速サンプルホールド回路21の
出力と送信時サンプルホールド回路20の出力と出力帰
還用の第2のサンプルホールド回路24の出力とを加算
し、出力帰還用の第1のサンプルホールド回路23に毎
回新たな記憶をさせるようになつている。出力帰還用の
第2のサンプルホールド回路24は、第1のサンプルホ
ールド回路23が新たな記憶をする前にその回の記憶内
容を記憶して加算回路22に与えるようになつている。
制御回路19は各サンプルホールド回路21,23,2
4の記憶が受信時に所定の時間間隔で順次行われるよう
に制御信号を出すようになつている。26はドライバー
、27はドライバー26に制御されて電圧信号を周波数
に変換して送信周波数F2の送信信号をつくる高周波電
圧制御発振器、28は送信信号を2分配する分配器であ
る。That is, the adder circuit 22 adds the output of the high-speed sample-and-hold circuit 21, the output of the transmitting sample-and-hold circuit 20, and the output of the second sample-and-hold circuit 24 for output feedback, and adds the output of the high-speed sample-and-hold circuit 21, the output of the transmitting sample-and-hold circuit 20, and the output of the second sample-and-hold circuit 24 for output feedback. The circuit 23 is configured to store a new memory each time. The second sample and hold circuit 24 for output feedback is configured to store the stored contents of the current time and provide the stored contents to the adder circuit 22 before the first sample and hold circuit 23 performs new storage.
The control circuit 19 includes each sample hold circuit 21, 23, 2
A control signal is issued so that the storage of 4 is performed sequentially at predetermined time intervals upon reception. 26 is a driver, 27 is a high frequency voltage controlled oscillator that is controlled by the driver 26 and converts a voltage signal into a frequency to create a transmission signal of transmission frequency F2, and 28 is a divider that divides the transmission signal into two.
一方の送信信号はサブミキサ14に与えられ、他方の送
信信号は高周波増幅器29に与えられ増幅される。30
は制御回路19に制御されて送信時間帯にのみ送信信号
を通過させる送信制御スイッチである。One transmission signal is given to the sub-mixer 14, and the other transmission signal is given to the high frequency amplifier 29 and amplified. 30
is a transmission control switch that is controlled by the control circuit 19 and allows the transmission signal to pass only during the transmission time period.
このような自動周波数制御装置は、送信時間帯において
は、後述するようにして送信周波数F2が所要の精度で
目標周波数f1に追従すると、制御回路19からの送信
指令により送信制御スイッチ30がオンとなり、高周波
電圧制御発振器27の出力である周波数F2の送信信号
は高周波増幅器29で増幅されてサーキユレータ12を
通りアンテナ11より輻射される。In such an automatic frequency control device, during the transmission time period, when the transmission frequency F2 follows the target frequency f1 with the required accuracy as described later, the transmission control switch 30 is turned on by a transmission command from the control circuit 19. A transmission signal of frequency F2, which is the output of the high frequency voltage controlled oscillator 27, is amplified by the high frequency amplifier 29, passes through the circulator 12, and is radiated from the antenna 11.
送信出力つまり高周波増幅器29の出力は大きいため、
周波数F2の送信信号はりーケージ信号としてサーキユ
レータ12のアイソレーシヨン分たけ低下して受信系に
入る。従つて、メインミキサ15の信号入力としては周
波数F2の送信信号の一部が、ローカル入力としては周
波数(F2+F3)のローカル信号が入ることになる。
従つて、その中間周波出力の中間周波数FIFはF3と
なる。周波数弁別器17の中心周波数は前述したように
F3に選定してあるので、基準となるこの周波数弁別器
17の中心周波数に一ΔF3のエラーがあれば、その工
ラー分だけ電圧ΔV3が表われる。この電圧ΔF3を制
御回路19の指令で送信時サンプルホールド回路20が
記憶して送信時に自動制御ループに加算すれば、周波数
弁別器17のエラーは自動補正されることになる。即ち
、第2図に示すように、周波数弁別器17の周波数弁別
特性を正常のときは中心周波数がF3となつている実線
Aとし、ΔF3のエラーが生じているときを破線Bとす
ると、周波数F3が入力された周波数弁別器17は一Δ
F3のエラーが生じているとΔV3の出力を出す。ΔF
3のエラーが生じるときには、受信時になると中間周波
数FIFは(F3−ΔF3)の周波数に収れんするよう
に自動制御がなされるので周波数弁別器17の出力が正
常時よりΔ■3だけ小さく表われることになる。つまり
、送信周波数F2は正常時よりΔF3のエラーを伴うこ
とになる。従つて、受信時に送信時サンプルホールド回
路20よりΔV3を加算回路22に印加すると、エラー
が自動補正されることになる。次に受信時間帯の動作を
説明する。Since the transmission output, that is, the output of the high frequency amplifier 29, is large,
The transmitted signal of frequency F2 enters the receiving system as a leakage signal, reduced by the amount of isolation of the circulator 12. Therefore, a part of the transmission signal of frequency F2 is input as a signal input to the main mixer 15, and a local signal of frequency (F2+F3) is input as a local input.
Therefore, the intermediate frequency FIF of the intermediate frequency output is F3. As mentioned above, the center frequency of the frequency discriminator 17 is selected to be F3, so if there is an error of 1 ΔF3 in the center frequency of this frequency discriminator 17, which is the reference, a voltage ΔV3 corresponding to the error will appear. . If this voltage ΔF3 is stored in the sample and hold circuit 20 at the time of transmission according to a command from the control circuit 19 and added to the automatic control loop at the time of transmission, the error of the frequency discriminator 17 will be automatically corrected. That is, as shown in FIG. 2, when the frequency discrimination characteristic of the frequency discriminator 17 is normal, the center frequency is F3 as a solid line A, and when an error of ΔF3 has occurred as a broken line B, then the frequency The frequency discriminator 17 to which F3 is input is -Δ
If an error occurs in F3, an output of ΔV3 is output. ΔF
When error 3 occurs, the intermediate frequency FIF is automatically controlled to converge to the frequency of (F3 - ΔF3) at the time of reception, so the output of the frequency discriminator 17 appears to be Δ■3 smaller than the normal state. become. In other words, the transmission frequency F2 is accompanied by an error of ΔF3 compared to the normal state. Therefore, if ΔV3 is applied from the sample-and-hold circuit 20 to the adder circuit 22 during reception, the error will be automatically corrected. Next, the operation during the reception time period will be explained.
目標周波数(受信周波数)f1がアンテナ11で受信さ
れてサーキユレータ12を通りメインミサキ15に印加
される。メインミキサ15では、目標周波数f1とロー
カル周波数(F2+F3)が混合されて中間周波数FI
F(=F2+F3−f1)に変換され、中間周波増幅器
16に印加される。中間周波増幅器16で増幅された周
波数が(F2+F3一f1)の中間周波信号は周波数弁
別器17に印加される。中間周波信号は検波器18で検
波され制御回路19のトリガ信号となり、高速サンプル
ホールド回路21に制御信号が与えられる。目標波数f
1と送信周波数F2との周波数差は周波数弁別器17で
電圧Δvに変換され高速サンプルホールド回路21に記
憶され、加算回路22に印加される。加算回路22の加
算出力は出力帰還用の第1のサンプルホールド回路23
に記憶され、次にその記憶内容が出力帰還用の第2のサ
ンプルホールド回路24に移されて、加算回路22にフ
ィードバックされる。サンプルホールド回路21,23
,24の各々のサンプルタイミングは、21,23,2
4の順序で、目標周波数f1のパルス繰返し周期T毎に
行われる。加算回路22の入力には、高速サンプルホー
ルド回路21を介して自動周波数制御系の一巡ループの
出力信号の他に、出力帰還用の第2のサンプルホールド
回路24を介して入出力繰返し加算回路25の出力がフ
ィードバック信号として与えられる。また、エラー補正
用に送信時にサンプルホールド回路20からも出力信号
が与えられている。加算回路22は、これら3つの入力
信号の加算を行う。加算出力は第1、第2のサンプルホ
ールド回路23,24に順次移され、再び加算回路22
の人力側にフィードバックされ新たな入力に加算される
。このような動作が繰返し行われ、回路25の出力は大
きくされる。入出力繰返し加算回路25の出力はドライ
バー26に与えられ、高周波電圧制御発振器27を制御
し、出力に応じた送信周波数F2に変換される。ループ
の利得をKとすると、制御対象である高周波電圧制御発
振器27の制御量は、受信時間中のパルス繰返し周期T
がn回であるとすると、となる。つまり、系の利得はN
Kと等価である。一般に受信時間は、パルス繰返し周期
Tより十分大きいため、系の一巡ループ利得Kは1以下
で十分である。高周波電圧制御発振器27の出力即ち周
波数がF2の送信出力は、分配器28で2分配され、方
はサブミキサ14に与えられ、他方は高周数増幅器29
に与えられる。A target frequency (reception frequency) f1 is received by the antenna 11, passes through the circulator 12, and is applied to the main misaki 15. In the main mixer 15, the target frequency f1 and the local frequency (F2+F3) are mixed to produce an intermediate frequency FI.
It is converted into F (=F2+F3-f1) and applied to the intermediate frequency amplifier 16. The intermediate frequency signal whose frequency is (F2+F3-f1) amplified by the intermediate frequency amplifier 16 is applied to the frequency discriminator 17. The intermediate frequency signal is detected by a detector 18 and becomes a trigger signal for a control circuit 19, and a control signal is given to a high speed sample and hold circuit 21. Target wave number f
1 and the transmission frequency F2 is converted into a voltage Δv by the frequency discriminator 17, stored in the high speed sample and hold circuit 21, and applied to the adder circuit 22. The addition output of the addition circuit 22 is sent to the first sample and hold circuit 23 for output feedback.
The stored contents are then transferred to the second sample-and-hold circuit 24 for output feedback, and fed back to the adder circuit 22. Sample hold circuit 21, 23
, 24 are sample timings of 21, 23, 2
4, every pulse repetition period T of the target frequency f1. The input of the adder circuit 22 is connected to the output signal of the one-loop loop of the automatic frequency control system via the high-speed sample-and-hold circuit 21, as well as the input-output repeat adder circuit 25 via the second sample-and-hold circuit 24 for output feedback. The output of is given as a feedback signal. Furthermore, an output signal is also provided from the sample and hold circuit 20 during transmission for error correction. The adder circuit 22 adds these three input signals. The addition output is sequentially transferred to the first and second sample and hold circuits 23 and 24, and then transferred to the addition circuit 22 again.
It is fed back to the human power side and added to the new input. Such operations are repeated, and the output of the circuit 25 is increased. The output of the input/output repeat adder circuit 25 is given to a driver 26, which controls a high frequency voltage controlled oscillator 27, and is converted into a transmission frequency F2 according to the output. Assuming that the loop gain is K, the control amount of the high frequency voltage controlled oscillator 27, which is the controlled object, is the pulse repetition period T during the reception time.
Assuming that is n times, then In other words, the gain of the system is N
It is equivalent to K. Generally, the reception time is sufficiently longer than the pulse repetition period T, so it is sufficient that the system open loop gain K is 1 or less. The output of the high-frequency voltage controlled oscillator 27, that is, the transmission output with a frequency of F2, is divided into two parts by a divider 28, one of which is given to the sub-mixer 14, and the other to the high-frequency amplifier 29.
given to.
送信時間になると、制御回路19から送信指令が出て送
信制御スイッチ30がオンとなり、送信信号はサーキユ
レータ12を経てアンテナ11から輻射される。When the transmission time comes, a transmission command is issued from the control circuit 19, the transmission control switch 30 is turned on, and the transmission signal is radiated from the antenna 11 via the circulator 12.
なお、入出力繰返し加算回路25は、その入力をアナロ
グ・デジタル変換してデジタル的に処理を行うようにし
てもよい。Note that the input/output repeating addition circuit 25 may perform analog-to-digital conversion of its input to perform digital processing.
その出力はデジタル・アナログ変換回路でアナログ量に
変換してドライバー26に与えるようにする。以上説明
したように本発明に係る自動周波数制御装置では、メイ
ンミキサのローカル周波数をサブローカル周波数と送信
周波数混混合により得て、このローカル周波数と目標周
波数f1又は送信周波数と混合するようにし、また周波
数弁別器はその中心周波数をサブローカル周波数F3に
一致させてこの周波数F3に収れんするような制御を行
わせるようにし、また周波数弁別器の後段には送信時に
この周波数弁別器の出力電圧信号を記憶する送信時サン
プルホールド回路と、前記周波数弁別器の出力電圧信号
と前記送信時サンプルホールド回路からの電圧信号を加
算する加算回路とを設けているので、基準となる周波数
弁別器にエラーが生じてもこれを自動補正することがで
きる。The output is converted into an analog quantity by a digital-to-analog conversion circuit and is then applied to the driver 26. As explained above, in the automatic frequency control device according to the present invention, the local frequency of the main mixer is obtained by mixing the sub-local frequency and the transmission frequency, and this local frequency is mixed with the target frequency f1 or the transmission frequency, and The frequency discriminator has its center frequency matched with the sublocal frequency F3 and is controlled to converge to this frequency F3, and the output voltage signal of the frequency discriminator is connected to the downstream stage of the frequency discriminator at the time of transmission. Since a transmitting sample-hold circuit for storing data and an adding circuit for adding the output voltage signal of the frequency discriminator and the voltage signal from the transmitting sample-and-hold circuit are provided, an error occurs in the reference frequency discriminator. However, this can be corrected automatically.
従つて、本発明によれば周波数追従性能の優れた自動周
波数制御装置を提供することができる。また、本発明に
よれば、周波数弁別器で安定度の優れた非常に高価な部
品を使用する必要がなくなり、安価に製造することがで
きる。Therefore, according to the present invention, it is possible to provide an automatic frequency control device with excellent frequency tracking performance. Further, according to the present invention, there is no need to use very expensive parts with excellent stability in the frequency discriminator, and the frequency discriminator can be manufactured at low cost.
第1図は従来の装置のブロック図、第2図は周波数弁別
器の特性図、第3図は本発明に係る装置の一例を示すブ
ロック図である。
11・・・・・・アンテナ、12・・・・・・サーキユ
レータ、13・・・・・・局部発振器、14・・・・・
・サブミキサ、15・・・・・・メインミキサ、17・
・・・・・周波数弁別器、19・・・・・・制御回路、
20・・・・・・送信時サンプルホールド回路、22・
・・・・・加算回路、27・・・・・・電圧制御発振器
、30・・・・・・送信制御スイッチ。FIG. 1 is a block diagram of a conventional device, FIG. 2 is a characteristic diagram of a frequency discriminator, and FIG. 3 is a block diagram showing an example of a device according to the present invention. 11...Antenna, 12...Circulator, 13...Local oscillator, 14...
・Sub mixer, 15...Main mixer, 17・
...Frequency discriminator, 19...Control circuit,
20...Sample and hold circuit during transmission, 22.
... Addition circuit, 27 ... Voltage controlled oscillator, 30 ... Transmission control switch.
Claims (1)
サブローカル周波数と送信周波数とを混合してローカル
周波数を形成するサブミサキと、受信時には目標周波数
と前記ローカル周波数を混合しまた送信時には前記送信
周波数と前記ローカル周波数を混合して中間周波数を形
成するメインミキサと、中心周波数が前記サブローカル
周波数に選定されていて前記中間周波数を電圧信号に変
換する周波数弁別器と、送信時に前記周波数弁別器の出
力電圧を記憶する送信時サンプルホールド回路と、前記
周波数弁別器側からの電圧信号と前記送信時サンプルホ
ールド回路からの電圧信号とを加算する加算回路と、加
算された電圧信号を前記送信周波数の送信信号に変換し
て前記サブミキサ側及び送信側に与える電圧制御発振器
を備えていることを特徴とする自動周波数制御装置。1. A local oscillator that generates a sublocal frequency, a submisaki that mixes the sublocal frequency and the transmission frequency to form a local frequency, and a submisaki that mixes the target frequency and the local frequency during reception and mixes the transmission frequency and the a main mixer that mixes local frequencies to form an intermediate frequency; a frequency discriminator whose center frequency is selected as the sublocal frequency and converts the intermediate frequency into a voltage signal; and an output voltage of the frequency discriminator during transmission. a transmitting sample-and-hold circuit that stores the frequency discriminator, an adding circuit that adds the voltage signal from the frequency discriminator side and the voltage signal from the transmitting sample-and-hold circuit, and an adding circuit that adds the added voltage signal to the transmitting signal of the transmitting frequency. An automatic frequency control device comprising: a voltage controlled oscillator that converts the frequency into a voltage controlled oscillator and supplies the converted signal to the sub-mixer side and the transmission side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252779A JPS596531B2 (en) | 1979-03-01 | 1979-03-01 | automatic frequency control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252779A JPS596531B2 (en) | 1979-03-01 | 1979-03-01 | automatic frequency control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55115736A JPS55115736A (en) | 1980-09-05 |
| JPS596531B2 true JPS596531B2 (en) | 1984-02-13 |
Family
ID=12085256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2252779A Expired JPS596531B2 (en) | 1979-03-01 | 1979-03-01 | automatic frequency control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596531B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60174632U (en) * | 1984-04-27 | 1985-11-19 | 日産ディーゼル工業株式会社 | Vehicle auto-clutch device |
| JPS61136044A (en) * | 1984-12-04 | 1986-06-23 | Kubota Ltd | Method of operating hydraulic clutch in hydraulically operated speed change gear unit |
| JPS63308226A (en) * | 1987-06-10 | 1988-12-15 | Kubota Ltd | Hydraulic clutch control device |
| JPS63308225A (en) * | 1987-06-08 | 1988-12-15 | Kubota Ltd | Hydraulic clutch operating device |
-
1979
- 1979-03-01 JP JP2252779A patent/JPS596531B2/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60174632U (en) * | 1984-04-27 | 1985-11-19 | 日産ディーゼル工業株式会社 | Vehicle auto-clutch device |
| JPS61136044A (en) * | 1984-12-04 | 1986-06-23 | Kubota Ltd | Method of operating hydraulic clutch in hydraulically operated speed change gear unit |
| JPS63308225A (en) * | 1987-06-08 | 1988-12-15 | Kubota Ltd | Hydraulic clutch operating device |
| JPS63308226A (en) * | 1987-06-10 | 1988-12-15 | Kubota Ltd | Hydraulic clutch control device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55115736A (en) | 1980-09-05 |
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