JPS59848B2 - microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer to which an external memory having a different number of instruction bits can be added.

Normally, in order to increase the number of instructions in a one-chip microcomputer, the number of bits in the instruction memory must be increased.

However, in order to minimize the chip size of the LSI from the viewpoint of accuracy, yield, etc., it is necessary to minimize the increase in the number of bits. For such inconvenience,
Attempts have also been made to increase the number of instructions by adding external memory to fill in the gaps as needed. The additional external memory is required to be easily available and inexpensive. Now, if the number of bits of the instruction memory of a microcomputer is designed to be 9 bits in relation to the number of instructions, it is naturally necessary to design the number of bits of the external instruction memory to be added to 9 bits as well. However, it is generally difficult to obtain a 9-bit instruction memory, and a 10-bit instruction memory is relatively easy to obtain, but is expensive. On the other hand, 8-bit memory is easy to obtain both in terms of price and quantity, but it has the disadvantage that it cannot be used as an external instruction memory in conventional systems because it lacks one bit. The present invention has been made in view of the above-mentioned drawbacks of conventional microcomputers, and it is an object of the present invention to provide a microcomputer that allows the addition of an external memory with an insufficient number of bits.

That is, for example, an 8-bit instruction ROM is used as an external instruction memory for a microcomputer consisting of 9-bit instructions, and the remaining 1 bit (here, this is the 9th bit) is always kept at a "low" level. In this case, clearly 9
Although it cannot be used for instructions that set the 9th bit to a ``high'' level, it is possible to use this instruction to set the 9th bit to a ``high'' level by incorporating an instruction that sets the 9th bit to a ``high'' level as a type of instruction on the microcomputer side. Even though the 9th bit of the instruction is set to the '6 low' level, the 9th bit becomes the 'high' level as an instruction, and a 9-bit configured instruction can be obtained, and an 8-bit configured external The desired purpose can be achieved with the instruction memory.Although the present invention has the disadvantage that it requires an instruction to set the 9th bit of the external instruction memory to a "high level," This is not a problem compared to the advantage of using less. Next, the present invention will be described in detail with reference to the drawings, with reference to an embodiment in which an external ROM with 8-bit instructions is added to an LSI with 9-bit instructions. Figure 1 shows that on one semiconductor chip (LSI),
18. A data memory for storing data; 18. An arithmetic unit for performing arithmetic or logical operations on the data stored in the data memory; 1. An instruction memory for storing instructions; 1.8) A program counter for addressing the instruction memory; and an output from the instruction memory. 1 is a block diagram of a one-chip microcomputer provided with a decoder for decoding instructions to be executed, the data memory I8 calculation unit, various registers for controlling the input/output terminals of the LSI, and the like. In the figure, the CG forms an oscillator circuit with a crystal resonator or passive elements such as resistors and capacitors connected to terminals 1 and 2 of the LSI, and the CG output of this oscillator is used as the operating clock frequency of the LS. The signal is supplied to each section described later to form operation timing, and is also supplied to the frequency dividing stage DIV.

The frequency dividing stage DIV is composed of 15 stages, and outputs f1 to Fl5 are obtained from each stage of the frequency dividing stage, but in this embodiment, the output F
Four types of frequency divided outputs, l, f3, f, and FlO, are derived and provided to an output frequency control register F, and an output of a desired frequency is taken out from the output terminal 22. A.C.
Cl and ACC2 are accumulators consisting of 4-bit general-purpose registers.

The ALU is an arithmetic unit that executes arithmetic or logical operations, and in this embodiment, the arithmetic operations are carried out between the accumulator ACCl and the accumulator ACC2, either the accumulator ACCl or the accumulator ACC2 and RAM (data memory), and either the accumulator ACCl or the accumulator ACC2 and the ROM. (instruction memory). A flip-flop C connected to the accumulator ACCl has a function of holding a carry generated as a result of an operation, and the flip-flop C can be set or reset by a command. The input terminals 3 to 6 are connected to the general-purpose register of the accumulator ACCl, and the signals ((
data) in general-purpose register ACCl. The input/output terminals 7 to 10 are connected to the general-purpose register of the accumulator ACC2, and data signals can be sent and received according to commands. The output terminal 11 is connected to a shift register consisting of 9 bits including the above-mentioned 1-bit component carrier flip-flop C, 4-bit component carrier flip-flop C, and two 4-bit component general-purpose registers ACCl and ACC2. , the contents of the 9-bit shift register are shifted and any one bit of the contents is output. The output terminal 13 functions as a general-purpose output terminal when the LSI functions as a normal one-chip microcomputer, and when an external ROM is added to the LSI as shown in Figure 2, it is used to access the external ROM. It also has the function of supplying timing signals. 0D connected to the input/output terminal 12 is an output regulation circuit that generates timing for exchanging data, and RW connected to the output terminal 13 provides timing for reading and writing. R
OM is an instruction memory that stores various instructions according to the functions of the microcomputer, and the stored instructions are read out by specifying an address by the program counter PC. In particular, in the present invention, an external ROM with an insufficient number of bits
Since the ROM is configured to be connectable, the following instruction is written to the ROM. That is, in the next step, the contents of the external ROM are read into the LSI, and the missing 9th bit in the external ROM says "If a high-level instruction is required, the corresponding external ROM that has been read is An instruction to supplement the 9th bit with 4 "high" levels to the 8-bit instruction in the ROM is pre-infected.D is an instruction decoder, which decodes the instruction read from the instruction memory ROM and reads L.
It has the function of giving commands to each part of S. Instruction memory ROM
The IG inserted between the and instruction decoder D is a gate circuit,
It is switched whether the instruction given to the instruction decoder D is output from the instruction memory ROM inside the LSI or whether the data of the external ROM read from terminals 3 to 10 and 12 of the LSI is input to the instruction decoder D. That is, the gate circuit ID is stored in the internal instruction memory R as shown in FIG.
It is provided with input terminals 110-118 to which OM commands are input and manual terminals 1E0-1E7 to which external ROM commands are input. Here, the input terminals 1E0 to E7 have the above LS
The 8-bit command from the external sound VB, OM supplied to the input terminals 3 to 10 of I is input, and an input terminal 1E8 is further provided as the 9th bit, and the input terminal E8 always has a low As shown in FIG. 3, each input terminal 1E0-1E8 is connected with an AND gate and a D-type flip-flop to form a gate circuit. In addition to the instructions in the external ROM, the micro order B1 issued from the internal instruction memory ROM is input immediately or via an inverter.The above micro order B1 is input to the external R
A "high" level signal is applied when the OM instruction is taken into the LSI.On the other hand, at the input terminals 110-118 to which the internal instruction memory ROM instruction is applied, the micro-order B2 is directly or The micro order B2 is given via an inverter.
Does it issue the command given to IEO-1E7 from the external ROM as a command, or does it issue instructions 10 to 18 from the internal memory ROM?
This signal is applied to one input terminal of each AND gate to turn on/off the commands supplied to the input terminals o to 17 and the flip-flop output on the external ROM side. It's in control. Here, regarding the 9th bit, in order to achieve the supplementary function of the 9th bit of the external ROM, the micro order B3
A D-type flip-flop A is provided.

For the above micro order B3, the next external ROM instruction is 9.
In a state where the micro-order issued from the internal instruction memory ROM requires supplementation of the ゜゜high level as the bit number, when the microphone b order B3 is issued, the instruction in the corresponding external ROM is determined by looking at the flip-flop. Output terminal.In order to synchronize with the timing of reaching ~7,
External RO with clock delay and 8-bit configuration
As the 9th bit of the M instruction, a high level signal is output from the terminal 18 and is supplied to the next stage instruction decoder ID as a 9-bit component instruction from -18. When the ninth bit is at a "low" level and does not require correction, the "low" level signal that is always applied to the terminal E8 is output as is from the output terminal 18 as a 1-bit component of the command. In any of the above cases, the external ROM instruction given in 8 bits is supplemented with a 9-bit component and transferred to the instruction decoder D via the gate circuit 1G. In FIG. 1, RAM is a data memory and can exchange data with the accumulators ACCl and ACC2.

Addressing of the data memory RAM is given from register H and register L consisting of 4 bits. Register H specifies the upper 4 bits, and register L specifies the lower 4 bits. Terminal 23 is an LS terminal that is also applied to conventional LSIs.
This terminal supplies signals for setting the initial states of various registers including the program counter PC when power is turned on to I, and is connected to an auto clear circuit ACL to form a signal. In this embodiment, P3 and P4 are both composed of 4-bit registers, and are connected to the accumulators ACCl and A.
Data can be input from either CC2.
Output terminals 14-17 and 18-21 are terminals for outputting the contents of register P3 and register P4, respectively. S
Rl and SR2 are stack registers that hold the contents of the program counter PC.
This register is used to store the return address during the period in which the address of the subroutine is specified, and is composed of two stages of stack registers. Terminal 24 connects LSI to GN
D, and the terminal 25 is connected to the power supply VDD. Output terminals 38 to 44 and 26 to 37 are terminals for connecting numeric display light emitting diodes, etc. Output terminals 38 to 44 output seven types of segment signals, and output terminals 26 to 37 output normal digit signals. A desired digit is displayed by a combination of the segment signal and the segment signal. S connected to the segment output terminal is a 4-bit register for holding display numerical data, and SD is a segment decoder that converts the contents of register S into necessary characters or symbols. Output terminals 27-36
outputs a digit signal for display when the LSL is running normal operations using only the functions within one chip.
When an external additional memory is provided, the address signal of the external ROM is output and the instruction code written to the designated address of the external ROM is applied to the LSI through the input/output terminals 3 to 10 and 12. , output terminals 27-3
Switching between the above-mentioned display drive and external memory addressing operations in step 6 is performed by the contents of a 4-bit register ST. The contents of the register ST can be rewritten by data transfer from the accumulator ACCl or the accumulator ACC2 according to a command from the ROM. Necessary data from the contents of the register ST is selected by the gate circuit G and outputted from the output terminals 26-37. As described above, according to the present invention, it is possible to use an external instruction memory with a small number of bits by simply adding a few instructions to write to the internal memory, and even if the microcomputer main body side has a unique command with a different number of bits, it is possible to use an external instruction memory with a small number of bits. Even when processing is required, a general-purpose memory device that is easy to handle can be used as an external memory, and it is possible to economically fill in the missing functions of a 1-chip microcomputer, significantly expanding the scope of use of the microcomputer. Can be expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an LSI according to the present invention, FIG. 2 is a block diagram showing a state in which an external instruction memory is added to the same LSI, and FIG. 3 is a block diagram of the main part of an LS according to the present invention. . ROM: Instruction memo 18 G: Gate circuit External ROM:
External instruction memory, IEOQlE8: External instruction memory instruction input terminal, 110-118: Internal instruction memory instruction input terminal, Bl, B2, B3: Micro order, AO: D
Type flipflop.

Claims (1)

[Claims] 1 External memory is added where the instruction consists of m bits 1
In a chip microcomputer, an internal instruction consists of n bits larger than m, and the (n-m) bit component is set in advance as a "low" (or "high") level signal for an m-bit external memory instruction. In the step of executing an instruction in an external memory whose (n-m) bit component is at a "high" (or "low") level, in a step before this step, an instruction in an external memory of read m bits is executed. An instruction that requires replenishment of (n−m) bit components of “high” (or “low”) level is written in the internal memory in advance,
A microcomputer characterized by converting m-bit instructions in an external memory into n-bit instructions.