JPS598909B2 - sense magnifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to sense amplifiers used in integrated memories and the like.

The flip-flop type is well known as a known sense amplifier.
Journal of Solid State Circuits Volume SC-10 Number 5 (1EEEJ0URNAL0F
50L1D-5TATEC1RCU1T5, V0LUM
E5C-10, NUMBER5, 5PP255-261
) (published in October 1975) paper ``1 Peripheral circuit of transistor cell MOSRAM'' (``Perifera
1CircuitsforOne-Transistor
rCellM0SRAM's''), and a sense amplifier as shown in Figure 1 is described10.l In a transistor type memory, the charge stored in the capacitor of a memory cell is transferred to a switching transistor which is a selection gate. Since a destructive read is performed by sensing through the memory cell, it is necessary to amplify the sensed stored information and rewrite it to the corresponding memory cell.

Flip-flop type sense amplifiers are high-performance circuits that have both reading and rewriting functions, but conventional devices generate a DC current bus when reading and writing, resulting in large power consumption. There were advantages and disadvantages. Therefore,
SUMMARY OF THE INVENTION An object of the present invention is to provide a sense amplifier with low power consumption.

According to the present invention, a high-performance sensing amplifier with low power consumption can be obtained without impairing sensitivity.

That is, first and second transistors 25 each have their drains connected to the gates of the other, their drains connected to a first bit line, their gates connected to a first clock line, and a first
A third transistor whose source is connected to the drain of the transistor, and a first transistor whose drain is connected to the second bit line.
A fourth transistor has its gate connected to the clock line of the second transistor and its source connected to the drain of the second transistor. a transistor, a fifth transistor having a drain connected to the first power supply, a gate connected to the second clock line, and a source connected to the drain of the third transistor; a sixth transistor whose gate is connected to the drain of the fourth transistor; a seventh transistor whose drain is connected to the source of the first transistor; its gate is connected to the third clock line; and its source is connected to the second power supply. and an eighth transistor having a drain connected to the source of the second transistor, a gate connected to the third clock line, and a source connected to the second power supply. can get. Next, an explanation will be given with reference to the drawings, taking an n-channel MOS transistor as an example of the transistor.

FIG. 1 shows a well-known sense amplifier, in which one transistor Q34 is slowly turned on by a clock φ3 after a differential input D, T) with a memory cell reading signal applied to one side is input. Initially, the cross-coupled transistor Ql,
Due to the positive feedback effect of Q2, the input signal is amplified somewhat, for example, transistor Q1 becomes closer to conduction than transistor Q2. Next, when transistors Q5 and Q6 are turned on by clock φ2, the drain of transistor Q1 approaches the low level V2 potential, while transistor Q
The drain of 2 approaches the high level V1 potential, and eventually the minute input signal is amplified to the power supply voltage, or almost the difference between V1 and V2, and the amplified signal is output to the outside,
The selected memory cell is rewritten. At this time, transistor Q1 is conductive while transistors Q5 and Q34 are conductive, creating a current path from power supply V1 to V2.

The shorter the time for this current to flow, the better, but it continues to consume power at least until pit wire b reaches a completely high level, and this power has not been used in recorded history.
FIG. 2 shows an embodiment of the present invention, in which cross-coupled transistors Ql and Q2 are replaced by transistors Q3 and Q, respectively.
It is connected to the bit line D, l5 via the bit line D, l5. Transistors Q3 and Q4 are transistors Q5 and Q4, respectively.
It is connected to a first power supply via Q6, while the sources of transistors Q1 and Q2 are connected to a second power supply via transistors Q7 and Q8. Transistors Q5, Q6
Although shown as being connected to transistors Q3 and Q4 without going through the bit line, it may be connected through the bit line.

FIG. 3 shows a schematic diagram of operating waveforms of the sense amplifier of FIG. 2. Prior to reading, bit lines D and D are precharged to the same level.

At this time, the clock φ1 goes to a high level b, making the transistors Q3 and Q4 conductive, and furthermore, the transistors Ql and Q2 are also turned on, and the sources of the transistors Ql and Q2, R} and S, are connected to the potential of the bit lines D and b. Almost transistor Ql,
It is precharged to a potential lower by the threshold value of Q2. Therefore, even if there is a difference in threshold between transistors Ql and Q2, which also affect sensitivity, the gate-source voltage is approximately equal to each threshold voltage, and this brittle charge makes the threshold difference substantially becomes invalid. After the flash charge is completed, the selected memory cell is then read. When the read signal of the memory cell is applied, the potential of D becomes b
Suppose that it reaches a slightly higher level. transistor Q
After the readout signal component is added to the potential of the drains P and T (nodes) of transistors Ql and Q2 through Q4, the clock φ becomes low level and cuts off transistors Q3 and Q4. . Since the potential of the node P has increased by the amount of the read signal, the transistor Q2 changes from the saturated state to the conductive state, and the charge at the node T flows into the node S, and the capacitance of the node S becomes smaller than the capacitance of the node T. If it is sufficiently large, the potential at node T will drop to a level approximately equal to the potential at node S. That is, node P.
The potential difference between and T is amplified to a value approximately equal to the threshold of transistor Q2. Next, the transistor Q7 is activated by the clock φ3.
, Q8 are made conductive, and the signal amplified to about the threshold value is amplified by the b amplifier composed of transistors Ql, Q2, Q7, and Q8.

That is, the transistors Q7 and Q8 are gradually turned on by the clock φ3, and the sources R of the transistors Ql and Q2 are
The potentials of nodes P and T are further increased by lowering the potentials of nodes P and S. On the other hand, while transistors Q3 and Q4 are cut off, clock φ2 turns off transistors Q5 and Q.
6 becomes conductive and charges up bit lines D and 5 to a high level. Charge bit lines D and D to a sufficiently high level.
After the clock is turned on, the transistors Q5 and Q are turned on by the clock φ2.
6 is cut off, and then the clock φ1 is set to high level again to make the transistors Q3 and Q4 conductive. At this time,
Since there is already a potential difference between nodes P and T that pre-amplifies the read signal, and transistor Q2 is in a state closer to being more conductive than Q1, charge is supplied from the bit line via transistors Q3 and Q4. , the potential at node P rises rapidly, transistor Q2 becomes completely conductive, lowering the potential at node T, and transistor Q1 becomes completely non-conductive. Therefore, the potential of bit line B rapidly decreases and approaches the level of the second power supply, but the potential of bit line D hardly changes because transistor Q1 does not conduct, and remains at a high level. There is. The sensitivity amplifier of this invention has V1
Since there is no current path from V2 to V2 in terms of direct current, and the power consumption is only as much as the charge stored in the capacitance of the bit line, the power consumption is extremely small.

In order to improve the sensitivity of this sense amplifier, the Gm ratio of the transistor is 9mZm1 (=9m4) to increase the gain.
/9m2) (However, Gml is 9m of transistor Q1,
9m2 represents 9m of the transistor Q2, gm3 represents 9m of the transistor Q3, and 9m4 represents 9m of the transistor Q4.

) is desirably small, for example 0.3 to 0.
1, but if the 9m ratio becomes too small, the response time and writing time will increase even if the sensitivity improves, so it is better to select the 9m ratio depending on the usage situation. As explained above, according to the present invention, a sense amplifier with extremely high sensitivity and low power consumption can be obtained, and it will be understood that it is extremely useful.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a known sense amplifier, Fig. 2 is a circuit diagram of a sense amplifier showing an embodiment of the present invention, and Fig. 3 is a waveform diagram for explaining the operation of Fig. 2. It is a diagram. Q1 to Q8 are transistors, V1 is a high level power supply, V2
is a low level power supply, and φ1, φ2, and φ3 are clock signals.

Claims (1)

[Claims] 1 First and second transistors with one drain connected to the other gate, the drain connected to the first bit line, the gate connected to the first clock line, and the source connected to the drain of the first transistor. a third transistor, a fourth transistor having a drain connected to the second bit line, a gate connected to the first clock line, a source connected to the drain of the second transistor, and a drain connected to the first power supply;
A fifth transistor has a gate connected to the second clock line, a source connected to the drain of the third transistor, a drain connected to the first power supply, a gate connected to the second clock line, and a source connected to the drain of the fourth transistor. A seventh transistor has its drain connected to the source of the first transistor, its gate connected to the third clock line, its source connected to the second power supply, and its drain connected to the source of the second transistor. and an eighth transistor having a gate connected to the third clock line and a source connected to the second power supply.