JPS6156599B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit using a Schottky junction gate field effect transistor that has a simple circuit configuration, low power consumption, short read and write times, and high speed.

Conventionally, a memory circuit using a Schottky junction gate field effect transistor (hereinafter simply referred to as a transistor for simplicity) has four transistors Q ₁ , Q ₂ , Q ₃ and Q ₄ as shown in FIG. The drains D of the transistors Q ₁ and Q ₂ are connected to the power supply line L ₁ through loads M ₁ and M ₂ , for example consisting of resistors R ₁ and R ₂ , respectively, and the sources S of the transistors Q ₁ and Q ₂ are connected to each other. _The gates of transistors Q ₁ and Q ₂ are connected to _the drains of transistors Q ₂ and _{Q 1 ,} respectively, and the sources ( _or drain) is each transistor _Q1
and Q ₂ drains, the gates of transistors Q ₃ and Q ₄ are connected together to word line W, and the other drains (or sources) of transistors Q ₃ and Q ₄ are connected through bit lines B ₁ and B ₂ , respectively. A configuration using a memory circuit cell connected to two data write lines _D1 and _D2 through two inputs _S1 and _S2 of a sense amplifier SA and two gate transistors _Q5 and _Q6 . Proposed.

By the way _{, the} memory circuit _shown in FIG _.
Construct a flip-flop with L ₁ and L ₂ ,
Therefore, _the transistor _{Q 1}
(or Q ₂ ) and Q ₂ (or Q ₁ ) are on and off, respectively, and correspondingly, the drains of transistors Q ₁ (or Q ₂ ) and Q ₂ (or Q ₁ ) are at low and high potentials, respectively. Information is stored in a state where the potential is maintained, and reading and writing of the information is configured as described below.

When a high potential is applied to the word line W, transistors Q ₃ and Q ₄ turn on, and current flows from the bit line B ₁ (or B ₂ ) side through the transistor Q ₃ (or Q ₄ ) to the transistor Q ₁ (or Information flows into the drain D side of transistor Q ₁ (or Q ₂ ), or flows into the bit line B _{1 (or B 2 ) side via transistor Q 3 ( or Q 4} ). Reading and writing are performed, but at this time, when gate transistors _Q5 and _Q6 are on and a signal potential for writing is applied by data write lines _D1 and _D2 , information is written. Conversely, when gate transistors Q ₅ and Q ₆ are off and the state of the flip-flop is detected by the sense amplifier SA through the current flowing through transistor Q ₃ (or Q ₄ ), information is read out. has been done.

Since the circuit was configured in this way, the flip-flop was connected to transistors Q ₃ and Q ₄ during readout.
Its state may change due to the influence of the current flowing through it. Furthermore, in order to reduce the above-mentioned influence, there is a limit to the size of the transistors Q ₃ and Q ₄ through which signal current flows during reading and writing. Therefore, the on-resistance is large, which makes it difficult to allow much signal current to flow, resulting in a disadvantage that reading and writing times become slow.

In order to solve these drawbacks, the present invention is designed so that the flip-flop is not affected by external circuits during reading, and the on-resistance of the gate transistor through which the signal current flows during reading and writing is reduced. Explain in detail.

FIG. 2 shows an example of a memory circuit according to the present invention,
Components corresponding to those in FIG. 1 will be described with the same reference numerals. Schottky junction gate field effect transistor (hereinafter simply referred to as transistor for simplicity) Q _{1
The drains D of _}
W ₁ and the sources S of transistors Q ₁ and Q ₂ are connected to each other and connected to the word power line W ₂ which is a pair with the word power line W ₁ , and the gates G of Q ₇ and Q ₈ are connected to the transistor Q ₁ respectively. , to the drain D of Q ₂ ,
A transistor whose sources S of transistors _Q7 and _Q8 control the amount of current as a constant current source by the two inputs _S1 and _S2 of the sense amplifier SA and the gate-source voltage through the bit lines _B1 and _B2 , respectively. At the drain D of Q ₉ and Q ₁₀ , transistor Q ₇
The drains D of transistors Q 9 and Q ₈ are connected to each other and connected to the data write line D ₃ , the gates G of transistors Q ₉ and Q ₁₀ are respectively connected to current control signal sources, and the sources S of transistors Q ₉ and Q ₁₀ are connected to each other. It has a configuration in which it is connected to the power supply line _L3 .

According to this configuration, as in the case of FIG. 1, a flip-flop is constructed with transistors Q ₁ and Q ₂ , loads M ₁ and M ₂ , and word power lines W ₁ and W ₂ , and word power lines W ₁ and W 2 are connected to each other. With a constant voltage applied between W ₂ and transistor Q ₁ (or
Q ₂ ) and Q ₂ (or Q ₁ ) are turned on and off, respectively, and the transistor Q ₁ (or
Information is stored while the drains of Q ₂ ) and Q ₂ (or Q ₁ ) are at a low potential and a high potential, respectively, and the information should be read out as described below. It is configured.

Apply a high potential to the word power supply lines _W1 and _W2 while keeping the voltage between them constant, and also apply a high potential to the data write line
While applying a high potential to D ₃ , transistors Q ₉ and
When a high potential is applied to the gate of Q ₁₀ to cause a constant current to flow, transistors Q ₇ and ₈ are turned on and a constant current flows, operating as a source follower circuit with transistors Q ₉ and Q ₁₀ as loads, forming a flip-flop. Depending on the level of drain voltage of transistors _Q1 and _Q2 , transistors _Q7 and
A high and low voltage is generated at the source of _Q8 , and reading is performed by detecting this with the inputs _S1 and _S2 of the sense amplifier SA. Therefore, during readout, the flip-flop current can be read out stably without drawing out the current from the flip-flop, that is, without external influences on the flip-flop. In addition, the readout time is also improved by allowing a large current to flow through the bit lines B ₁ and B ₂ , which quickly charges and discharges the capacitance of the bit lines B ₁ and B ₂ and changes the voltage, allowing the state of the flip-flop to be sensed more quickly. It can be detected and read by amplifier SA.

On the other hand, in the case of writing, assume that transistor Q ₁ of the flip-flop is on and transistor Q ₂ is off, and the respective drain voltages are in a state of low potential and high potential. Explain the operation when writing to the opposite state. Then it will look like this: Word power line W ₁ and W ₂
A high potential is applied while keeping the voltage between them constant, and a low potential is applied to the data write line _D3 . A high potential is applied to the gate of the current control transistor _Q10 on the side of ₂ to turn it on and a constant current (write current) flows.The drain voltage of the flip-flop transistor is at a low potential and is raised to a high potential by writing. should transistor
Apply a low potential to the gate of the current control transistor _Q9 on the side of _Q1 to turn it off and cut off the current. Then, the above constant current (writing current) is
The current flows through transistor Q ₈ through B ₂ , but since the data write line D ₃ connected to the drain of transistor Q ₈ is at a low potential, most of the current is
This becomes the gate current of Q ₈ , and this current flows through the load M ₂ . Therefore, writing is performed by lowering the gate potential of transistor _Q1 and inverting the flip-flop. Therefore, during writing, the required write current can be set to a large value and the gate potential of the flip-flop transistor to be turned off can be quickly changed from high potential to low potential, so the state of the flip-flop can be quickly reversed. The writing time can be shortened.

As described above, the configuration of the memory circuit of the present invention provides stability without external influences on the flip-flop during readout, and also enables high-speed readout. Furthermore, writing can be performed at high speed, and application to information processing devices requiring high-speed storage circuits is expected.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing a conventional memory circuit, and FIG. 2 is a connection diagram showing an example of a memory circuit according to the present invention. Q ₁ , Q ₂ ... Schottky junction field effect transistors forming a flip-flop, Q ₃ to _{Q 8} ...
...Gate transistor using a Schottky junction field effect transistor, Q ₉ , Q ₁₀ ... Current control transistor using a Schottky junction field effect transistor, M ₁ , R ₁ , M ₂ , R ₂ ... Load (resistance) , SA...Sense amplifier, _S1 , _S2 ...Sense amplifier input terminal, _L1 , _L2 , _L3 ...Power line, W...
Word line, W ₁ , W ₂ ... Word power line, B ₁ , B ₂ ...
...Bit line, D ₁ , D ₂ , D ₃ ... Data write line,
S...source, G...gate, D...drain.

Claims (1)

[Claims] 1 first, second, third, and fourth shotgun junction gate field effect transistors Q ₁ , Q ₂ , Q ₇ ,
Q ₈ , and the drains of the first and second shotgun junction gate field effect transistors Q ₁ and Q ₂ are connected to the first word power supply line W ₁ through the first and second loads M ₁ and M ₂ respectively. In the above first and second
Schottky junction gate field effect transistor
The sources of Q ₁ and Q ₂ are connected to the second word power supply line W ₂ , and the gates of the first and second shotgun junction gate type field effect transistors Q ₁ and Q ₂ are connected to the second and second word power supply lines W 2 , respectively. The gates of the third and fourth Schottky junction gate field effect transistors Q ₇ and Q ₈ are connected to the drains of the first and second Schottky junction gate field effect transistors Q ₂ and Q ₁ , respectively. The drains of the shotgun junction gate field effect transistors Q ₁ and Q ₂ and the sources of the third and fourth shotgun junction gate field effect transistors Q ₇ and Q ₈ are connected to the first and second data input/output lines B, respectively. ₁ and B ₂ , the drains of the third and fourth shot junction gate field effect transistors Q ₇ and Q ₈ are connected to each other and connected to the data write line D ₃ . A memory circuit using type field effect transistors.