JPS599115B2 - hand tie memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory that avoids data line imbalance due to a rewrite pulse to a memory cell generated in a rewrite signal line that intersects with a data line.

Conventionally, a charge transfer type amplifier as shown in FIG. 1 has been used as a high-sensitivity sense amplifier.

The operation of this circuit is as follows. That is, by applying a precharge signal to the gate of the transistor Qp, the output line D
Breach L and data line D. However, Qt
A voltage VR (where VR<VDD) is applied to the gate of. Next, a pulse is applied to the word line W to read out the information stored in the memory cell MC. As a result, the voltage of D is
It changes slightly from the above precharge voltage. The larger Cd is compared to Cs, the smaller this changing voltage becomes. As long as the voltage is Co-Cs, even if the voltage appearing at D is small, it will appear as a sufficiently large voltage change at DL. In this case, Qt acts as a kind of amplifier (for details, see ISSCC75Sessi
onX Memory, “High-Sensitive
eCharge-TransferSenseAmpl
i-fier"). A feature of this type of memory is that after reading the MC, it is necessary to rewrite the MC. This operation is performed using a type of AND circuit AND (
An amplifier may be used) to rewrite the resulting signal voltage read from a predetermined MC via Qt using the rewrite command ◆signal R/W. However, if a rewriting circuit is provided for each of a pair of electrically balanced data lines connected by a differential amplifier, the rewriting command signal R/
There is a problem with inputting W. In other words, since there is a coupling capacitance at the intersection of the R/W signal line and the data line,
If the rewrite command signal R/W is input to only one system, a voltage will be generated only in one system due to this coupling capacitance. The present invention solves this drawback and will be explained in detail below using examples. Figure 2 shows two electrically balanced data lines D.
, D, an amplifier and the rewriting (or writing) circuit described above are added to the memory.

In this case, the R/W signal line provided in each rewrite circuit crosses the two data lines. In other words,
A semiconductor memory has a large number of memory circuits shown in FIG. 2 arranged vertically. Since the R/W signal line is arranged perpendicularly to the data line and connected to each memory circuit, it crosses the data line (not shown). Connect terminal A to VR (
Set VR to DD-) and use Qp, Qp- to DL
, DL, D, and D, MC and a dummy cell DC for noise cancellation are connected to the word lines W, DL, D, and D, as is well known.
Select by applying voltage to DW, DL, DL
A differential readout signal is extracted. After this, set R/W to 0
By setting it to N and operating the AND (an amplifier may be used), the MC is rewritten according to the gate voltages of Qw and Ow (this is ultimately determined by the voltage of the MC's storage capacity Cs at the time of reading). In other words, if DL just before reaching R/Wl)50N is a low voltage compared to DL, the gate voltage of (MCO)Cs corresponds to a low voltage) Qw's gate voltage is a low voltage (0).
It remains as it is. This is because the gate voltage of Qw is transmitted to 0 during precharging. On the other hand, DL is D. L
As a result, the gate of Q1 is charged to a high voltage due to the high voltage compared to D. The battery is charged to high voltage. If MC
O) If the voltage of Cs is a high voltage, contrary to the above, the gate voltage of Qw becomes a high voltage, and the high voltage is rewritten to MC. The problem with this circuit is that it is read when the voltage of MCO)Cs is low, and this read signal is detected and Qw is used to rewrite the low voltage to MC. Because Cs and Cd, the voltage of D at the time of rewriting is a high voltage close to R-V,h (threshold voltage of Th:Q,) after completion of reading, and the gate voltage of Qw is 0V, so Qw is cut off. For this reason, a low voltage (0) cannot be written to the MC. Differential amplifiers Q2 and Q2 are used to solve this problem. That is, terminal B is set to a sufficiently high voltage (>VR-Th) so that Q2 and Q2 are cut off during reading, and is set to a low voltage (0) during rewriting. At this time, D continues to be charged to a high voltage by Qw, and on the other hand? Since D is at a high voltage higher than D due to cut-off, D is fed back quickly by Q2 and Q2, and D is discharged to O. As a result, the low voltage is rewritten to the MC. The feature of this circuit is that either Qw or Qw is always cut off, so almost dynamic operation is performed, so power consumption is low. In order to further speed up the rewriting operation, the terminal A may be set to 0 during this operation to cut off Ql and Qt so that the capacitances of DL and Dl do not become a load on Qw and ``Qw. Even if you try to pre-charge Qt, Q, 1) and D after the rewriting is completed (in this type of charge transfer amplifier, this voltage level must be approximately R-Vth), the rewriting point just before that Since either D or D is charged to a sufficiently high voltage (~DD-Th) and the other is discharged to O, terminal A becomes VR (VR) during pre-charging.
As long as the data line is charged to a high voltage,
Because the Q or Q that leads to this is cut off,
It is never possible to precharge to VR-Vth. Therefore, Q, which is 0N with a precharge signal, is used. Assume that as a result of rewriting, D becomes 0 and D becomes VDD-Th. CE is 0N7! If Q1 is 0N, the capacitances of D and D are almost equal, so D, -
The voltage of 1D is approximately equal to l(DO-, h).

If this voltage is smaller than VR-,h, Qt and Qt are turned ON, and as a result, D and 'D are precharged to VR-,h, thereby establishing the conditions for the next read operation to be performed normally. In this embodiment, since the rewrite command signal R/W is given to each rewrite circuit of the data line, the coupling capacitance at the intersection of the data line and the R/W signal line on each side The electrostatic induction potentials generated are balanced. Therefore, the rewrite signal can be given at the same time without distinguishing between the two rewrite circuits, so the circuit that generates the rewrite signal can be shared, which has the effect of simplifying the circuit. There is. Figure 3 also shows the so-called two-intersection/bit memory cell method, which detects a read signal from a memory cell connected only to one of the intersections of two electrically balanced data lines and a word line. This is an example to which the above invention is applied.

The operation is similar to that shown in FIG. In this case, the data lines are arranged in a folded manner. That is, since the semiconductor memory has a structure in which a large number of memory circuits shown in FIG. 3 are arranged vertically, the R/W signal line is arranged perpendicularly to the data line and connected to each memory circuit. Therefore, the R/W signal line crosses each of the two data lines (not shown) and has a coupling capacitance with each data line. Therefore, even if the rewrite command signal R/W is applied to one rewrite circuit, a potential due to electrostatic induction is similarly generated in both data lines, so that electrical balance can be maintained. or,
The space for two data lines can be used for arranging the rewriting circuit, making the layout of the rewriting circuit easier compared to the space for one data line as shown in Figure 2. It's also effective. Note that in the second and third times, the voltage at the gates of Qw and Qw is a differential signal D as a read signal.

, DO. Furthermore, it is obvious that during writing, if the gate voltages of Qw and Qw are controlled differentially, a write data signal from the outside can be written to the MC. Note that the AND may be an amplifier as described above, but a specific example thereof is shown in FIG. 4 using a two-intersection/bit memory cell system as an example.

The part K in the box corresponds to AND in FIG. 3. The operation is performed as follows. The signal appearing at the gates of Q4 and Q4 through Qt is changed to φPa, which was previously at a high level (so that Q3 and Q3 are cut off).
is set to O, Q3, Q3 are turned on and amplified, and Qi, Q
Depending on the read information, one is discharged to 0V and the other is held at a high level. Next, Q4, Q4
φ, which was set to a high level to keep it cut off,
, the operation by φ8 is completed, that is, Q4, Q4
0 after any of the gates of is discharged to approximately 0. This ensures that if the gate of Q4 is 0V, the gate of Q6 remains at a high level precharged by Q5, while in this case the gate of Q4 is at a high level, so Q4 is turned on. The gate of Q6 is discharged to 0
It becomes V. After this, when R/W is turned on (set to high level), the gate of Qw remains at the voltage just before turning on R/W, that is, O, and is therefore cut off. On the other hand, since Q6 is on, the gate O of Qw is charged to a high voltage, so that Qw is on and D is charged to a high level. As described above, according to the present invention, it is possible to maintain electrical balance between the two data lines even if rewrite signals are applied simultaneously without distinguishing between the two rewrite circuits.
This has the effect that the circuit for sending out the rewrite signal can be shared, which simplifies the circuit. In another invention, even if a rewrite signal is given to one rewrite circuit, the electrical balance between the two data lines can be maintained, and furthermore, the layout of the rewrite circuit can be made easier. effective.

[Brief explanation of the drawing]

FIG. 1 is a conventional circuit diagram, and FIGS. 2 to 4 are examples of the present invention.

Claims (1)

[Scope of Claims] 1. A pair of data lines, and a differential amplifier that differentially amplifies the potentials of the pair of data lines to bring the potential of one data line to a first potential level; A pair of first circuits are provided corresponding to the pair of data lines, and set the corresponding data lines to a third potential level by a rewrite signal when the potential of the corresponding data lines is at the second potential level. and second means for simultaneously sending a rewrite signal to the pair of first means. 2 a pair of folded data lines; a differential amplifier that differentially amplifies the potentials of the pair of data lines to bring the potential of one data line to a first potential level; A pair of first electrodes are provided corresponding to each pair of data lines, and when the potential of the corresponding data line is at the second potential level, the rewrite signal causes the corresponding data line to be at the third potential level. A semiconductor memory comprising: means; and second means for sending a rewrite signal to the first means of the pair.