JPS6012661B2 - ROM check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION ROM incorporated in the present invention (large-scale integrated circuit)
This invention relates to a ROM check method for checking the function of (read-on memory).

Type 4 electronic calculators are generally equipped with a fixed memory ROM for microinstructions, and are configured to perform various arithmetic and control operations using instructions retrieved from the ROM.

Therefore, in a computer equipped with the above-mentioned ROM, it is necessary to check the ROM, and conventionally, a checking method has been adopted in which microinstructions stored in the ROM are executed and the results are judged. However, the above-mentioned checking method requires a large amount of test time to execute various pre-programmed calculations, and has the drawback that it is not possible to perform a test check with sufficient accuracy. Also, ROM
In addition to the above-mentioned checking method, a determination method has been considered in which the ROM address is automatically advanced and all outputs are derived externally and the contents are determined. It requires many dedicated circuits and
It is necessary to separately provide a terminal used only for checking to output the OM output to the outside. Since the number of terminals in LIS is limited, it is not preferable to provide a terminal exclusively for checking. The present invention has been made in view of the above points, and is a data memory RAM (random access memory).
Store a different value in each address, specify the address of the RAM by the output of the ROM,
It is an object of the present invention to provide a ROM check method that can reliably perform a check without adding a check terminal by transmitting the contents to the outside and making a determination.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a ROM that fixedly stores various microinstructions, and a ROM address section 12
The address is specified by In addition to various instructions, the above-mentioned ROM II has a RAM 13 for storing calculation data.
It stores the address for and its own next address, from output line a to the row address UA of RAM 13, from output line b to column address LA of RAM 13, from output line c to various instructions INS, from output line d to outputs its own next address NA. The above RO
The row address output from the output line a of the MII is supplied to the row address input terminal of the RAM 13 via the gate circuit 14 and the OR circuit 15, and is also supplied to the row address input terminal of the RAM 13 through the gate circuit 14 and the OR circuit 15.
and is supplied to the row address input terminal of the RAM 13 via the OR circuit 15. Further, the column address outputted from the output line b of the ROMII is directly sent to the column address control section 17 and also sent to the OR circuit 15 via the gate circuit 18.
and is sent to the column address control section 17. This column address control section 17 controls R according to input column address data Z.
Controls the column address of AM13. Furthermore, the above ROM
The instruction output from the output line c of I1 is sent to the instruction decoder 19 and also sent to the column address control section 17 via the gate circuit 20. Z can also be sent to the next address register 21 output from the output line d of the ROMII. In this address register 21, address data is set in accordance with the next address and the result of the calculation applied via the output line d during normal calculation, and address data is set by the address control section 22 in the case of 2 check. The address control unit 22 operates when a signal is applied from a test terminal 23 provided in the general unit 1, and sets two address data inputted from the outside into the address register 21. In this case, the address data to the address control unit 22 is given, for example, by sharing a key input terminal. In addition, each of the gate circuits 14, 16, 18, 20
are gate-controlled by the timing layer No. 3 t, -W outputted from the timing generation circuit 24 via the gate group 25. The gate group 25 has output lines 25a and 25b.
During normal calculations, a timing signal is given to the gate circuit 14 through the output line 25a to control the gate, and when a test signal is given to the test terminal 23 to check the ROMII. is the output line 25b
A timing signal is applied to the gate circuits 16, 18, and 20 via the gate circuits 16, 18, and 20 to perform gate control. Each of the above gate circuits 16
, 18, and 20 are gates that operate only during checking, and are in an open state during normal calculation. Although not shown, the instruction decoder 19 outputs control signals for controlling various arithmetic control gates and outputs an issue/write command R/W. This R/W
The command is sent to the RAM 13 via the AND circuit 26, and when it is "0", it is set, and when it is "1", it is written. The test signal applied to the test terminal 23 is applied to the AND circuit 26 via an inverter 27 as a control signal. Further, the RAM 13 is composed of a plurality of registers, for example, eight registers, and each register has a 16-digit structure. Each register is then specified by a row address, and the digit of the specified register is specified by a column address. Although not shown, the data output terminal of the RAM 13 is connected to an arithmetic unit, a display unit, etc., as well as an external tester 28. This external tester 28 has, for example, a printing function, a data checking function, etc., and prints out the data retrieved from the RAM 13, and determines whether the read data is correct or not. Further, with reference to FIG. 2, the detailed structure of the main parts shown in FIG. 1 will be explained in detail.

The gate circuit 14 is connected to the row address output line a of RAM II.
It consists of 6 transfer gates corresponding to the number of
Each gate is interposed on the output line a, respectively. Above 6
The gates are divided into a first gate group 14a and a second gate group 14b of three each.
The outputs of the gate group 14b are connected in pairs, and are connected to the row address input terminal of the RAM 13 via OR circuits 15a to 15c. In addition, the gate circuit 16,
18 and 20' are provided corresponding to the number of row address output lines a, column address output lines b, and instruction output lines c of the ROMII, respectively. For example, R.O.
Since the MII has 6 output lines a, 8 output lines b, and 7 output lines c, a total of 21 lines, the gate circuits 16, 18, and 2 gates are composed of a total of 21 transfer gates. , each gate is respectively interposed in the output line of ROMII. Then, three output terminals of each gate constituting the gate circuits 16, 18, 20 are sequentially connected together, and the first to seventh gate groups G, to G
It is divided into 7 parts. Then, the first to third gate groups ○, ~
The output of G3 is sent to RAM1 via OR circuits 15a to 15c.
The outputs of the fourth to seventh gate groups G4 to G7 are input to the column address control section 17. During normal calculation, when the column address control unit 17 receives the calculation start column address and calculation end column address from the ROMII,
The calculation start column address is counted up one by one until it reaches the calculation end column address, and a 4-bit column address is given to the RAM 13. Also, when checking, a part of the column address and instructions from ROMII are all 4 bits.
Address control operations such as providing a bit column address to the RAM 13 are performed. On the other hand, a gate group 25 to which timing signals t, ~t3 are applied from the timing generation circuit 24
consists of AND circuits 31a, 31b, 32a to 32c, and inverter circuits 33 and 34, and AND circuits 32a to 32
A test signal from the test terminal 23 is directly applied to one input device of the circuit c, and the test signal is input via an inverter 33 to one input terminal of the AND circuits 31a and 31b.

Timing signals t and t3 output from the timing generation circuit 24 are input to the other input terminals of the AND circuits 32 Za to 32 c, respectively. Furthermore, the timing signal t, is directly input to the other input terminal of the AND circuit 31b, and the timing signal t, is input via the inverter 34 to the other input terminal of the AND circuit 31a.
Thus, the gate control of the first gate group 14a of the gate circuit 14 is performed by the output of the AND circuit 31a.
Gate control of the second gate group 14b is performed by the output of the AND circuit 31b. Moreover, the AND circuits 32a to 32
Each gate of the first to seventh gate groups ○, to G7 in the gate circuits 16, 18 and 2 is sequentially controlled in a time-sharing manner by the output of the gate c. Next, the operation of the present invention configured as described above will be explained.

When the test signal is not applied to the test terminal 23, the output of the inverter 33 in the gate group 25 is "1".
Therefore, the gates of AND circuits 31a and 31b are opened. Since the AND circuit 31a is given the timing signal t, via the inverter 34, and the AND circuit 31b is directly given the timing signal t, the AND circuit 31a outputs a "1" signal at the timing t. The AND circuit 31b outputs a "1" signal at the above timing. Therefore, the first gate group 14a of the gate circuit 14 is activated at the L timing, and the second gate group 14a is activated at the L timing.
4b opens the gate and transfers the row address output from ROMI I to the RAM 13 via the OR circuits 15a to 15c. In this case, the AND circuits 32a to 32c in the gate group 25 close their gates, and their outputs are "0". For this reason, the gate circuit 16,
All gates 18 and 2 are closed, and the column address control section 17 is given only the column address output from the ROM II via the output line b. Therefore, during normal operations, the RAM 13 is addressed by the row address and column address output from the ROMII. Further, instructions outputted from ROMI I via output line c are sent to an instruction decoder 19, and various control signals outputted from this instruction decoder 19, such as read/write commands to the RAM 13, adder circuits ( Calculation control is performed by addition/subtraction commands for (not shown), transfer of calculation data, display commands, etc. Further, the start address of ROMI I is given by key operation on a key input unit (not shown), and subsequent ROM addresses are given according to the next address outputted from ROMII, the calculation result, etc. Next, the operation when checking the ROMII will be explained.

When checking, first, predetermined data is stored in the RAM 13 as shown in FIG. 3, for example. in this case,
Each piece of data is stored differently in the same row and column. In FIG. 3, numerical values from 0 to 15 are stored in each row, but the storage positions are shifted by three digits between each row. Next, a test signal is applied to the test terminal 23, and address data for specifying the address of ROMI I is applied to the address control section 22.

When a test signal is applied to the terminal 23, the inverter 27
The output becomes "0" and the gate of the AND circuit 26 is closed. As a result, input of a write command to the RAM 13 is prohibited, and the RAM 13 is maintained in the write mode while the test signal is applied. On the other hand, when the gate group 25 is given a test signal, the AND circuits 32a to 32c
When the gates of the AND circuits 31a and 31b open, the output of the inverter 33 becomes "0" and the gates of the AND circuits 31a and 31b are closed. As a result, the outputs of the AND circuits 31a and 31b become "0", closing the gate of the gate circuit 14, and the AND circuit 3
Timing signals t, . . . , etc. are sequentially outputted from 2a to 32c, and are opened in synchronization with each gate timing signal t, .about.t3 of gate circuits 16, 18, 20. Above gate circuit 1
6, 18, 20 are composed of the first to seventh gate groups G, -G7 as described above, and each gate group ○, -G7 opens its gate in synchronization with the timing signal et al. -t3, and R
The row address, column address, and instruction output from OMI I are sent to the RAM 13 and column address control section 17 as address data of the RAM 13. Therefore, as shown in Figure 4, the output of ROMII is 6 row address output lines and 3 column address output lines.
3 row addresses U,, U2, U4, and the remaining 5 column address output lines and instruction output line 7.
The book becomes the column address L, -, L, L8 of the RAM 13. Therefore, if the ROM II is configured as shown in FIG. 4 and the storage contents of the RAM 13 are set as shown in FIG.
The output of 13 is as shown in FIG. For example, the ROM address section 12 sets the ROMII address line,
is specified, at timing t, the row address "
100" 4, column address "1101" 13 output "0001" of RAM 13 becomes 1, and at these timings, row address "010" 2, column address "1111" 15 RAM
1 3 output n0OU 9, and furthermore, at the timing of t3, the row address "100" 4 and the column address "110"
0"12, and the output of RAM13 becomes "0000"0.
Address lines 1 to ln of the ROM II are sequentially designated according to data input from the address control section 22 to the ROM address section 12 via the address register 21. During this test, input of the next address NA output from the ROM 11 to the address register 21 is prohibited. In this manner, the addresses of the RAM 13 are sequentially specified according to the output contents of the ROMII, and the contents of the RAM 13 are read out. The data read from this RAM 13 is sent to the external tester 28 via the number of normally used output terminals that output data to an external memory, etc., and the external tester 28 checks whether the ROMII is operating normally. is determined. That is, this judgment is made by incorporating data corresponding to the address of RAM 13 expected by the design of ROMII into the external tester 28 in advance, and automatically comparing and collating it with the data actually output from RAM 13 at the time of checking. Determine whether or not it is operating normally. Note that this external tester 28 may be one that does not have an automatic judgment function and only has a printing function.
Of course, the determination may be made based on the printing results. In this way, in the above embodiment, the output of the 21-bit ROMII is sequentially applied in a time-sharing manner to the 128-digit RAM 13 addressed by 7 bits (3 bits x 4 bits), so that it is output in 4 bits. By this,
Even though the output data is compressed, RAM1
Since the data storage format in ROMI 3 does not include the same data in the same row or column, it will be normal unless multiple bits of ROMI1 output are incorrect at the same time (the probability that multiple bits of ROMII will be incorrect at the same time is extremely low). You can perform various checks. Note that in the above embodiment, when checking, the RO is
Although the address of MII is specified, this may be done by using the next address NA of ROMI I itself and adding some branch condition processing circuits.

Also, the method of addressing RAM 13 using the output of ROMII is completely arbitrary; the point is that it is sufficient to use the output of ROMII as an addressing signal to RAM 13 using an appropriate method.
The method is not limited to the time division method as in the above embodiment.

Furthermore, in the above embodiment, for example, when an external memory etc. is included,
That is, although the case has been described with a 4-bit output terminal connected to the RAM 13, in a case without an external memory etc., it is also possible to compare and check from outside the output data converted for the display segment. .

As described above, according to the present invention, predetermined data is stored in the RAM provided in the computer itself, this RAM is addressed using the output data of the test ROM, and the memory contents of the RAM are determined by this addressing. proposed and RO
Since the setting data expected by the M design and the actual input data are compared to determine the quality of the ROM, external connection terminals can be added by simply adding a simple checking circuit. This allows the ROM to be checked without fail.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is an overall circuit configuration diagram, FIG. 2 is a circuit diagram showing details of the main parts of FIG. 1, and FIG. 3 is a test diagram stored in RAM. FIG. 4 is a diagram showing an example of a ROM configuration. FIG. 5 is a diagram showing an example of a ROM configuration, and FIG. 5 shows a correspondence between ROM output data during a test and RAM address data addressed by this output data. It is a figure showing a relationship. 1 1...ROM (read-on memory), 13
．． ．．・．．・RAM (random access memory), 14
, 16, 18, 20...gate circuit, 28...external tester, G, ~G7...first to seventh gate groups. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1 In a logic circuit that is controlled by a ROM that stores RAM addresses and various instructions and performs arithmetic control functions, predetermined data is stored in the RAM at the time of testing, and the test signal is input to the test signal input terminal. The signal inhibits the normal address control operation for the RAM, and also operates the test address control system to sequentially designate the address of the RAM using each output of the ROM, and determine the address of the ROM from the data content read from this RAM. A ROM check method characterized by performing a check.