JPS6012783B2 - semi-moving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a multilayer wiring structure.

Generally, a semiconductor device having this type of multilayer wiring structure includes a so-called silicon gate field effect semiconductor device using polycrystalline silicon for a gate electrode.

In this semiconductor device, when forming the source and drain regions,
In addition to these regions, another diffusion region may be provided in the semiconductor substrate, and this diffusion region may be used as a wiring region. Further, the above-described semiconductor device uses a diffusion region provided in the semiconductor substrate as a wiring region, and
Polycrystalline silicon produced during the formation of the gate electrode is selectively left and used as a wiring layer. In this manner, when manufacturing a semiconductor device using polycrystalline silicon as a gate electrode and wiring layer, it is necessary to diffuse impurities into the polycrystalline silicon in order to make the polycrystalline silicon a conductor. Generally, in order to reduce duplication of steps, this impurity diffusion is usually performed at the same time as the diffusion step for forming the source and drain regions and the above-mentioned wiring regions in the semiconductor substrate. However, in the method of simultaneously diffusing impurities into polycrystalline silicon and diffusing impurities into a semiconductor substrate, the wiring region cannot be formed unless the polycrystalline silicon located above the diffusion wiring region provided in the semiconductor substrate is removed.

Therefore, it is difficult to mount a wiring layer made of polycrystalline silicon over the wiring region with an insulating film interposed therebetween. Therefore, in this semiconductor device, the wiring region and the wiring layer are configured so that they do not overlap, and a perfect multilayer wiring structure cannot be expected, which is one of the factors that prevents miniaturization of the device. An object of the present invention is to provide a semiconductor device having a structure in which a process of overlapping a wiring region within a semiconductor substrate and a wiring layer disposed on the semiconductor substrate can be performed extremely easily.

Another object of the present invention is to provide a semiconductor device with a multilayer wiring structure that can be expected to achieve higher density.

Another object of the present invention is to provide a field effect semiconductor device using polycrystalline silicon as a gate electrode and wiring layer.

A feature of the present invention is that a first wiring layer of an opposite conductivity type is provided in a region of one conductivity type of a semiconductor substrate, and the first wiring layer is connected via an insulating film provided on the main surface of the semiconductor substrate. a second wiring layer including a semiconductor layer intersecting with the first wiring layer;
In the semiconductor device, the width of the second wiring layer at a portion where the second wiring layer intersects is narrower than the width at other portions.

In the present invention, since the wiring layer is provided in the area that is to become the wiring area so that the width is narrower than that in other parts, the wiring layer is A continuous wiring region is also formed in the lower part.

Since the portion under this wiring layer is narrow, it is not necessary to widen the wiring region in the lateral direction, and therefore a wiring region having a width and depth sufficient for practical use can be formed. Then, a semiconductor device having a structure in which a wiring region within the semiconductor substrate and a wiring layer disposed on the semiconductor substrate overlap with each other with an insulating film interposed therebetween is obtained. Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1A and 1B are a cross-sectional view and a plan view for explaining an example of a subordinate semiconductor device.

Referring to FIG. 1, "In addition to a source region 9 and a drain region 10, a wiring region 4 is formed by diffusion in the semiconductor substrate 1. In addition, a gate region 4 is formed in the region between the source region 9 and the drain region 10. An insulating film 5 and a gate electrode 7 made of polycrystalline silicon are provided so as to partially overlap the source and drain regions.Furthermore, on the insulating film 2 on the semiconductor substrate 1, a wiring layer 8 made of polycrystalline silicon,
A wiring layer 12 made of an aluminum metal film is provided to connect the wiring layers 8 and 8'. When manufacturing a semiconductor device having multilayer wiring layers in this way, silicon dioxide (Si02) 2 is first formed on the surface of the semiconductor substrate 1, and the source and drain regions are
The insulating film 2 in the portion corresponding to the gate region and the insulating film 2 in the area where the wiring region is to be provided is selectively removed to expose the surface of the semiconductor substrate 1.

Next, a gate insulating film 5 is formed by thermal oxidation in an oxygen atmosphere, and then a polycrystalline silicon film is provided on the entire surface. This polycrystalline silicon film is selectively etched to form a gate electrode 7.
and wiring layers 8, 8' are formed. Furthermore, the insulating film 5 deposited on the semiconductor substrate 1 is removed except for the part that will become the gate insulating film, and the parts of the semiconductor substrate corresponding to the wiring region 4, source region 9, and drain region 10 are exposed. let In this way, the surface of the semiconductor substrate 1 is selectively exposed, and
Impurity diffusion is performed with polycrystalline silicon layers 8, 8' and gate electrode 7 exposed to the outside.

As a result, the impurity is diffused into the exposed surface and the polycrystalline silicon surface of the semiconductor substrate 1, and is further injected into the conductive source region 9, drain region 10, polycrystalline silicon gate electrode 7, and polycrystalline silicon wiring layer 8. , 8' are formed. Next, after depositing an insulating film 11 on the entire exposed surface, the connecting portions of the polycrystalline silicon wiring layers 8, 8' are formed with holes.

Next, after coating the entire surface with an aluminum metal wiring film,
This is selectively etched to form a polycrystalline silicon wiring layer 8.
, 8' are electrically coupled to each other.
form 2. In the method described above, the step of providing a diffusion region on a semiconductor substrate and the step of making polycrystalline silicon disposed on the substrate conductive are performed simultaneously.

Therefore, it is difficult to create a multilayer wiring in which the wiring region constituted by the diffusion region and the zero polycrystalline silicon film overlap. 2 to 11 are diagrams sequentially showing the manufacturing process of a semiconductor device according to an embodiment of the present invention.

Here, a case will be described in which a P channel silicon gate MOS transistor is used as the field effect transistor. Referring to FIG. 2, an N-type silicon substrate 10
1 (for example, resistivity 60), an insulating film 102 made of silicon dioxide is formed to a thickness of 80,000 Å by thermal oxidation.

Next, as shown in FIG. 3, the insulating film 102 is selectively etched by photolithography to expose the surface of the semiconductor substrate 101 and define the activation region 103 and wiring area 104 of the field effect transistor. . In this case, a hydrofluoric acid solution is suitable as the etching solution for the silicon dioxide film 102.
Furthermore, as shown in FIG. 4, a silicon dioxide film 105 having a thickness of 1000 Å is deposited on the exposed regions 103 and 104 of the semiconductor substrate 101 by thermal oxidation. In this case, the insulating film 105 may be made of Si3N4, ON203, or the like. Subsequently, as shown in FIG.
A polycrystalline silicon film 106 with a thickness of 5000 Å is formed on the entire surface of 2,105 by thermal decomposition of monosilane (SiH4). Next, as shown in FIGS. 6A and 6B, the polycrystalline silicon wiring layer 106 is selectively etched by photolithography, and the gate electrode 107 and the polycrystalline silicon wiring layer 108 are selectively etched.
Determine.

Note that the polycrystalline silicon film 106 is etched using a nitric acid-glacial acetic acid-hydrofluoric acid based etching solution. In this state, as shown in FIG.
It intersects with 04. In addition, the polycrystalline silicon wiring layer 10
8 is the wiring area 1, as is clear from the plan view of FIG. 6B.
04, the Z wiring layer is etched so that the width thereof becomes narrower, that is, a portion of the wiring area 104 of the semiconductor substrate 101 is exposed. In this embodiment, a wiring layer 108 having a width of 8 mm is used as a wiring area 104.
At the intersection with the wiring Z layer 108, it is divided into three widths each, and a gap is provided inside the wiring Z layer 108. Figure 7 A, B
is a diagram for explaining the next step of FIGS. 6A and B,
7A is a sectional view taken along line aa' in FIG. 6B, and FIG. 7B is a sectional view taken along line bb' in FIG. 6B.

In the two groups shown in FIG. 7A, the insulating films on the other active regions are removed, leaving the gate insulating film 105 located under the gate electrode 107. Further, referring to FIG. 7B, only the insulating film 105 under the polycrystalline silicon film 108 is left and the other parts of the insulating film 105 are removed, and the semiconductor 2 substrate 105 is removed.
The surface of 1 is exposed. In this way, the regions 109 and 110 where the source and drain are to be formed are exposed, and
Impurities are diffused with a portion of the wiring area 104 where a wiring region is to be formed exposed, and after the diffusion, indentation is performed.
3. FIGS. 8A and 8B are diagrams showing the state after impurity diffusion and indentation, and correspond to FIGS. 7A and B, respectively. As shown in the figure, a semiconductor substrate 10
A source region diffusion layer 109', a drain region diffusion layer 110', and a wiring region diffusion layer 104' are formed on the exposed surface of 1. At this time, in the wiring area 104 where the polycrystalline silicon wiring layer 108 intersects with the insulating film 105, the impurity is pushed in from both ends of the narrow polycrystalline silicon wiring layer 108, so that the diffusion region spreads laterally. A continuous impurity diffusion region IQ4' is obtained as shown in FIG. 8B. Further, due to the diffusion and intrusion of the impurities, the polycrystalline silicon gate film 107 and the polycrystalline silicon film 108 become conductive and function as electrodes and wiring layers. In this example, boron trichloride was used as the impurity diffused into the N-type silicon substrate. (BC13) was used, and the layer resistance due to diffusion was set to 50 (Q/). Next, as shown in Figure 9,
An insulating film 1 with a thickness of 0.5 Buddha's skin is formed on the entire surface of the element by chemical bonding of monosilane (SiH4) and oxygen (02).
11 is formed, and the insulating film 111 is selectively etched by photolithography.

As a result, the polycrystalline silicon wiring layer 108 and the polycrystalline silicon gate electrode 107 are partially exposed, or the wiring region 104', the source region 109', and the drain region 110' are partially exposed. Provides for connections with aluminum metallization. In this state, the 10th
As shown, a metal coating 112, such as aluminum, is deposited on the surface of the element. After this, the 1st
As shown in the figure, the metal coating 112 is selectively etched by photolithography to form a wiring layer. Note that the aluminum metal film was etched using phosphoric acid. As described above, according to the semiconductor device having the structure of the present invention, it is possible to laminate a wiring region formed by diffusion on the surface of a semiconductor substrate and a polycrystalline silicon layer with an insulating film interposed therebetween, without increasing the number of steps. It is.

Therefore, a wiring structure is obtained in which the three wiring layers, the wiring area in the semiconductor substrate, the polycrystalline silicon wiring layer, and the metal film wiring layer, are overlapped in the same area through the insulating film, realizing a high-density integrated circuit. be able to.

[Brief explanation of the drawing]

1A and 1B are cross-sectional views and plan views showing the structure of a conventional semiconductor device, and FIGS. 2 to 11 are views for explaining an embodiment of the semiconductor device of the present invention in the order of manufacturing steps. In the figure, 101...semiconductor substrate, 10
2...Insulating film, 105...Insulating film, 10
7... Polycrystalline silicon gate electrode, 108...
...Polycrystalline silicon wiring layer, 104, 104'...
...Wiring area and wiring area, 111...
. . . Insulating coating, 112 . . . Aluminum metal wiring layer. Rhijiku' diagram Figure 2 Figure 3 Figure 4 Memurofu diagram Bi-related diagram Figure F

Claims (1)

[Claims] 1. A first wiring layer of an opposite conductivity type provided in a region of one conductivity type of a semiconductor substrate, and a semiconductor that intersects with the first wiring layer via an insulating film provided on the main surface of the semiconductor substrate. a second wiring layer including a second wiring layer, the second wiring layer at a portion where the first and second wiring layers intersect is divided into a plurality of parts, and includes a portion whose width is narrower than the other portions. A semiconductor device characterized by: