JPS6013208B2 - Arithmetic control method for multiprocessing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic control method in a multi-processing device, and more particularly, the present invention relates to a method for controlling arithmetic operations in a multiprocessing device, and more specifically, a method for dividing a processing device into an instruction unit, an arithmetic unit, and a storage control unit, and a resource sharing method in which a plurality of instruction units share other units. The present invention relates to an arithmetic control method for arithmetic units shared by a type multiprocessing device.

As is well known, in this type of resource-sharing multiprocessing device, each of the plurality of instruction units mainly retrieves instructions from the storage device, and also prepares the data necessary for the operation. When all are completed, a processing request is issued to the arithmetic unit.

One of the processing requests issued from each instruction unit is selected by an instruction selector, and the corresponding instruction unit is connected to an arithmetic unit. The arithmetic unit performs a desired operation using data prepared by the selected instruction unit, requests data itself if necessary, and stores the result of the operation in a register or a storage device. By the way, when a storage device has a two-layered structure of high-speed, small-capacity buffer storage and low-speed, large-capacity main memory, when data is in the buffer storage, it can be retrieved quickly, which improves the performance of the arithmetic unit. It is about the same level.

However, if it is not in the buffer storage, it is read from the main memory, which slows down the reading process. The above-mentioned instruction unit and arithmetic unit are designed so that when data is in the buffer storage, the arithmetic unit operates without any stagnation, and if the data is not in the buffer storage, the arithmetic unit is idle until the data arrives and the next operation is performed. It is controlled so that it does not proceed to processing. This includes:
{1} Stop the clock of the arithmetic unit. ■ Repeat the process over and over again. There are other methods, but since they are not directly related to the present invention, they will not be discussed further.
Below, the state where this processing unit is waiting for processing is called Fun.
We will call it action wait. This F plate cti
Onwait occurs both when the instruction unit reads data (hereinafter referred to as case A) and when the arithmetic unit reads data (hereinafter referred to as case B). That is, case A occurs in normal instruction processing, but case B occurs in variable length instruction processing. Now, the above Fumtion wait
Reducing the number increases the efficiency of the arithmetic unit, and thus increases the performance of the entire processing device.

In particular, in the case of a multiprocessing device, the processing request issued by one instruction unit (hereinafter referred to as an instruction stream) is
If uMtionwait occurs or is about to occur, switch to another instruction stream, and then resume processing of the stream before the switch after the data is read, to reduce the Factionwait. Performance can be improved. However, case A occurs at the end of an instruction, whereas case B occurs in the middle of an instruction, partly because it is difficult to process all instructions in one cycle in an arithmetic unit. Therefore, switching the instruction stream in case A is relatively easy, but switching in case B requires restarting the instruction from the middle, which is more difficult than in case A. An object of the present invention is to make it possible to easily switch the instruction stream even if an F-plate action wait occurs not only in case A but also in case B in a multiprocessing device in which a plurality of instruction units share an arithmetic unit. The objective is to provide an arithmetic control method.

Simply put, in order to achieve the above object, the present invention provides a group of work registers whose held data changes on a basic cycle basis, a status register that defines the state of the basic cycle, a control flip-flop, etc. for each instruction unit. The reason for this is that they were made independent and established as many as they were.

Below, two instruction units share an arithmetic unit.
The content of the present invention will be explained using a heavy processing equipment as an example.

FIG. 1 shows a schematic configuration of an embodiment of the present invention.

In the figure, 1 is a central processing unit, 2 is an input/output device, 3 is a storage control device, 8 is a main storage device, and the central processing unit 1
consists of instruction units 4a and 4b, an instruction selector 5, an arithmetic controller 6, and an arithmetic unit 7. Although not shown in the figure, the storage control device 3 includes a buffer storage. The instructions are read from the buffer storage of the storage controller 3 by the instruction units 4a and 4b and entered into the instruction units, where they are decoded and subjected to necessary preprocessing such as preparing operands, and then sent to the arithmetic controller. 6. Computed and processed by the computing unit 7. In this darkness, the instruction selector 5 selects either instruction unit 4a or 4b when the arithmetic unit 7 is open, or the arithmetic unit 7 selects the F plate action.
When a command is executed, control is performed such as switching to another command unit. The arithmetic controller 6 is a microprogram control device for controlling the operation of the arithmetic unit 7 using a microprogram, and includes a decoder for decoding instruction codes, as will be described later.
It includes a control logic section, a control storage device for storing microprograms, and the like. When a request to read an instruction or an operand is issued from the instruction units 4a, 4b, the arithmetic controller 6 determines whether the corresponding instruction or operand is in the buffer storage of the storage controller 3, and if so, moves the instruction or operand to the buffer storage. The data sent from is transferred to the instruction unit 4a, 4b or the arithmetic unit 7, and if there is no data,
A request is issued to the main storage device 8 to read data from the main storage device 8, and the data is transferred to the instruction units 4a, 4b or the arithmetic unit 7 via the storage control device 3. FIG. 2 shows a detailed configuration example of the arithmetic controller 6 and the arithmetic unit 7 shown in FIG. 1, and
The connection relationship between these and the instruction selector 5 is shown.

In the figure, the arithmetic controller 6 is a microphone. Program execution controller 10, control storage address register (CMAR)) 1
1a, 1 1b, control memory (CM) 12, control memory data register (CMDR) 13, address adder 1
4, etc., of which CMARs have a multiplexed structure equal to the number of instruction units. The arithmetic unit 7 includes operand buffer registers (OBR) 15a, 15b, work register A (WRA) 16a, 16b, work register B (WRB) 17a, 17b, and general register group (GR
)1 8a, 1 8b, adder 19, work register C
(WRC) 20, status register (STR) 21a
, 21b, etc., and all registers except for the adder 19 and WRC 20 have a multiplexed configuration. 1
00a and 100b are request signal lines from the instruction unit to the arithmetic unit, 101 is a signal line indicating the end of operation, 102 is a signal line indicating Function wait, 103 is a signal line indicating the selected instruction unit, and 104 is sent from the instruction unit. A control signal line 105 is a control signal line sent from the storage control device, and 106 is an output signal line decoding the microprogram.

50a and 50b are instruction obecode signal lines sent from each instruction unit 4a and 4b to the arithmetic unit;
5 1 b is the output line of CMARI 1 a, 1 1 b, 52 is the read data line of CM12, 53 is CMDR1
3 output line, 54 output line of address adder 14, 55
is the exposed data line from the storage control device 3, and 56 is the OBR.
1 5a, 1 5b output line, 57 is GR18a, 18
The logic data lines 58a and 58b of b are WRA16a,
16b output line, 59a, 59b are WRB17a, 17
b output line, 60 is the output line of adder 19, 61 is WRC
20, output lines of STRs 21a and 21b.

In this case, the arithmetic circuit section of the arithmetic unit 7 is made up of only the adder 19, but in reality it includes a shifter and other logic circuits. Command unit 4a
, 4b issues an instruction from the storage control device 3, and after completing the necessary preprocessing, issues a processing request to the arithmetic unit through the signal lines 100a and 100b, and also outputs the obecode of the instruction (actually, the obecode is modified). signal line 5
Outputs 0a, 50M.

The obe codes of the signal lines 50a and 50b are CMARI 1 a and 1 1 provided for each instruction unit, respectively.
Set to b. That is, CMARI1a, 11
Different values are set in b depending on the instruction.
On the other hand, the instruction selector 5 receives a trigger to start operation when the signal line 101 indicating the end of operation or the signal line 102 indicating the function is on,
Select one of 00a and 100b and connect the signal line 103
Output the selection results to . The microprogram execution controller 10 monitors desired control signals applied from the storage controller 3 and instruction units 4a and 4b through signal lines 105 and 104, and as a result turns on the signal line 101 or 102 to process the instructions. has ended or Funct
ionWait notifies the instruction selector 5 that the operation of the microprogram has been temporarily stopped. Further, the microprogram execution controller 10 selects the instruction selector 5 when the signal line 101 is on, or when the signal line 102 is on and the instruction stream to be switched is at an instruction break.
Depending on the state of the output signal line 103 of the instruction units 4a,
Select either CMARI1a or 11b corresponding to CMI4b and run the CMARI2 microprogram. Assume now that CMARI 1a corresponding to instruction unit 4a is selected.

In this case, the contents of CMARI1a are given to the CM12 as the output address of the CM12 through the signal line 51a, and the microinstructions read from the CM12 at that time are set in the CMDR13 through the signal line 52. The data set in the CMDR 13 is decoded by the microprogram execution controller 10, and the result appears on the decode output line 106. This decode output line 106 also includes information indicating the instruction stream selected by the instruction selector 5 in response to the state of the signal line 103. Therefore,
Since the instruction stream of instruction unit 4a is currently selected, OBR1 5a and WRA1 6a corresponding to instruction unit 4a are determined by decode output line 106.
, WRB17a, GR18a, STR21a are adder 1
9, the WRC 20 and the storage control device 3) are both controlled. During this time, if the microprogram does not branch, the contents of CMARI1a are stored in the address adder 14.
CMARI 1 through the signal line 54
It is set to a again and becomes the next read address for CM12. If the microprogram branches, C
Part of the data in MDR13 is sent to CMA as a branch address.
RI 1a is set. This is the case when the instruction selector 5 selects the instruction stream of the instruction unit 4a, but if the instruction stream of the instruction unit 4b is selected, similarly, the decode output line 106 of the microprogram execution controller 10 Instruction unit 4M corresponds to OBR1 5b, WRA1 6b, WRB1 7b
, GR18b, and STR21b are controlled.

The functions and general operations of each part in FIGS. 1 and 2 have been described above, and more detailed operations when an F-plate action wait occurs will be described later.

FIG. 3 shows an instruction selector 5 which is one of the features of the present invention.
This is a specific configuration example.

In the figure, 30 indicates two processing request signal lines 100a, 1
This is a selection circuit that selects one of 00b. The selection output of this selection circuit 30 is the signal line 1 indicating the completion of calculation.
01 is on and signal line 1 indicates F skin action wait.
It becomes valid when 02 is off, and is transmitted to the signal line 103. 3
1 is a circuit that loops the signal line 103 and inverts the state of the signal line 103 when the signal line 102 is turned on.

In other words, by this circuit 31, the FunctionWait
The instruction stream is switched when . Furthermore, in FIG. 3, when both signal lines 101 and 102 are off, the state of signal line 103 previously selected by selection circuit 30 is maintained. FIG. 4 shows a specific example of the configuration of the microprogram execution controller 10.

33 is a well-known microprogram decoder, and 32 is a well-known microprogram monitor.

An offer request to the storage control device 3 is set as one of the outputs of the decoder 33. The response from the storage controller 3 to this request is monitored by the signal line 105, and when it is determined by the signal line 105 that the target data is not in the buffer storage, the microprogram monitor 32 turns on the signal line 102. , F side ction
Wait is instructed. Also, the output of the decoder 33 is 2
The control signal line 106a or 106b is selected according to the stream selection indicated by the signal line 103, and is supplied to the registers on the corresponding stream side. The microprogram monitoring device 32 receives a computation end signal from the decoder 33 and sends the computation end signal onto the line 101. This signal is sent to the command selector 5. Next, F
The switch operation when an unction wait occurs will be explained with reference to FIG. In the figure, solid lines indicate data signals, and broken lines indicate control signals. First, when the signal line 101 is on, the instruction selector 5 operates, stream selection occurs, and the selection result is output to the signal line 103. As a result, one of the instruction units 4a and 4b is selected, and the signal line 50a
Alternatively, the instruction obecode is set to CMARI1a or 11b through 50b. In Figure 5, instruction unit 4
A case is shown in which CMAR1 1a corresponding to a is selected. As a result, the data is extracted from CM12 and the CM
DR1 Set to 3. The contents of CMDR13 are microphones. It is decoded by the program execution controller 10, and by this control signal, for example, WRA16a, WRB17
a, and the adder 19. In the next cycle, when attempting to transfer data from the OBR 15a to the WRB 17a by the signal on the signal line 106, the signal line 102 turns on.
Suppose that F skin CT onwait appears. At this time, the instruction selector 5 is activated again and switched to another instruction stream. This can be seen from the change in signal line 103. At this time, the CM corresponding to the instruction stream that has been processed so far
The contents of ARI1a are retained. Then, CMARlib corresponding to another stream becomes active. At this time, if another stream (the stream to be switched) is in the middle of instruction processing, the corresponding CMAR
A new obecode is not set to Olib, but if instruction processing is completed and the next instruction processing is required, a new obecode is set to CMARlib from the signal line 50b. Since FIG. 5 shows the former case, there is no setting to CMARI1b. Thus the commercial
Microinstructions are extracted from CM12 by ARI 1b, and sent to microprogram controller 1 via CMDR13.
It is decoded as 0 and outputs a control signal to the signal line 106.
The registers used for calculation at this time are WRA16b and WR.
B17, GR18b, STR21b, etc., which are different from the registers used before. Therefore, the registers WRA1 6a, WR used before switching
B1 7a, GR1 8a, STR21a as is)
Since the data is retained, processing can be easily restarted the next time it is switched. Thereafter, processing will continue in the same manner. As explained above, according to the present invention, it is possible to easily switch the instruction stream not only when Factionwait occurs at the end of an instruction, but also when it occurs in the middle of an instruction. .

For example, F-sactionWai occurs when the target data is not in the buffer storage and is read from the main memory.
Since t usually lasts eight cycles or more, switching to another instruction stream during this period is effective in increasing the operating efficiency of the arithmetic unit.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a multiprocessing device implementing the present invention;
FIG. 2 is a specific configuration diagram of the arithmetic unit in FIG. 1,
3 is a specific configuration diagram of the instruction selector in FIG. 2, FIG. 4 is a specific configuration diagram of the microprogram execution controller in FIG. 2, and FIG. 5 is for explaining the stream switch operation according to the present invention. This is a time chart. 4a, 4b...Instruction unit, 5...Instruction selector, 6... Arithmetic controller, 7... Arithmetic unit, 10... Microprogram execution Controller, 1
1a, 11b...CM address register, 12
...Control memory layer (CM), 13...CM data register, 14...Address adder, 15a
, 15b, 16a, 16b, 17a, 17b, 18a,
18b, 20, 21a, 21b...Regis evening, 19...
...Adder. Figure 1 Figure 3 Figure 2/Figure 4 Figure 5

Claims (1)

[Claims] 1. In a resource sharing type multiprocessing device in which a plurality of instruction units share an arithmetic unit, registers whose held data changes in units of basic cycles in the arithmetic unit are multiplexed and arranged by the number of the instruction units, and the arithmetic When a processing wait occurs in a unit, the instruction stream is switched in the basic cycle unit, the registers of the instruction unit corresponding to the newly selected stream are activated, and the data in the registers of the instruction unit corresponding to the previous stream is An arithmetic control method for a multiprocessing device that is characterized in that it is maintained as is.