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JPS6013299B2 - Heat treatment method for semiconductor devices - Google Patents
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JPS6013299B2 - Heat treatment method for semiconductor devices - Google Patents

Heat treatment method for semiconductor devices

Info

Publication number
JPS6013299B2
JPS6013299B2 JP7479777A JP7479777A JPS6013299B2 JP S6013299 B2 JPS6013299 B2 JP S6013299B2 JP 7479777 A JP7479777 A JP 7479777A JP 7479777 A JP7479777 A JP 7479777A JP S6013299 B2 JPS6013299 B2 JP S6013299B2
Authority
JP
Japan
Prior art keywords
heat treatment
diffusion
semiconductor
semiconductor wafers
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7479777A
Other languages
Japanese (ja)
Other versions
JPS548968A (en
Inventor
欣三 田尾
喜美男 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP7479777A priority Critical patent/JPS6013299B2/en
Publication of JPS548968A publication Critical patent/JPS548968A/en
Publication of JPS6013299B2 publication Critical patent/JPS6013299B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【発明の詳細な説明】 この発明は炉内に複数のウェーハを並列させて、不純物
拡散等の熱処理をおこなう方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of arranging a plurality of wafers in parallel in a furnace and performing heat treatment such as impurity diffusion.

従来、半導体ウェーハに不純物拡散による拡散層の形成
をおこなう場合、あるいは熱酸化膜を成長する場合、複
数個の半導体ウェーハを各々の表面を一定方向に向けた
状態で拡散ボート上に並べ、これを加熱炉内で1000
o0以上の高温で熱処理することがおこなわれているが
、この熱処理は半導体ゥェーハに所定の機能を具備させ
るまで数回おこなう必要がある。
Conventionally, when forming a diffusion layer on a semiconductor wafer by diffusing impurities or growing a thermal oxide film, multiple semiconductor wafers are lined up on a diffusion boat with their surfaces facing in a certain direction. 1000 in a heating furnace
Heat treatment is performed at a high temperature of o0 or higher, but this heat treatment must be repeated several times until the semiconductor wafer has a predetermined function.

しかし、この場合、前の熱処理工程で半導体ゥェーハの
裏面に不純物の拡散層が形成されることが多く、そのた
め、後の熱処理時にウェーハ表面特にウェーハ裏面から
、不純物の飛び散り(0心tdiffusion)が起
り易く、そのような飛び散り現象によって、得られる半
導体ウヱーハの特性に悪影響を及ぼすなどの問題があつ
た。たとえば、一伝導型を有する基板(たとえばP型基
板)表面の特定個所に反対の伝導型(N型)を有する不
純物源を被着し、熱拡散によってN型拡散層を形成する
場合、前の熱処理によって半導体ゥェーハ裏面に形成さ
れたN型不純物が対向する半導体ウェーハの表面に飛び
散り、所定の拡散層形成領域以外にもN型不純物の拡散
層が形成され、半導体ウヱーハが特性的に悪影響を受け
るのである。この発明は上記事情に鑑みてなされたもの
であって、上述の如き半導体ウェーハの熱処理時の飛び
散り現象によって生ずる悪影響を回避することができる
半導体ゥヱーハの熱処理方法を提供することを目的とす
る。
However, in this case, an impurity diffusion layer is often formed on the back surface of the semiconductor wafer during the previous heat treatment process, and as a result, impurity scattering (zero-core tdiffusion) occurs from the wafer surface, especially from the wafer back surface, during the subsequent heat treatment. However, such scattering phenomenon has a negative effect on the characteristics of the obtained semiconductor wafer. For example, when an impurity source having an opposite conductivity type (N type) is deposited on a specific location on the surface of a substrate having one conductivity type (for example, a P type substrate) and an N type diffusion layer is formed by thermal diffusion, the previous N-type impurities formed on the back surface of the semiconductor wafer due to heat treatment scatter to the surface of the opposing semiconductor wafer, and a diffusion layer of N-type impurities is formed in areas other than the predetermined diffusion layer formation area, which adversely affects the characteristics of the semiconductor wafer. It is. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for heat treatment of semiconductor wafers that can avoid the adverse effects caused by the scattering phenomenon during heat treatment of semiconductor wafers as described above.

すなわち、この発明は拡散ボートに複数の半導体ウェー
ハを並列し、これを拡散炉内で熱処理する方法において
、隣接する2枚の半導体ウェーハを各裏面を互いに対向
させて並列した状態で拡散ボートに配置し、不純物拡散
による拡散層の形成あるいは酸化膜の形成のための熱処
理をおこなうことを特徴とする半導体装置の熱処理方法
を提供するものである。
That is, the present invention is a method of arranging a plurality of semiconductor wafers in a diffusion boat in parallel and heat-treating them in a diffusion furnace, in which two adjacent semiconductor wafers are arranged in a diffusion boat in a parallel state with their back surfaces facing each other. The present invention also provides a method of heat treatment for a semiconductor device, characterized in that heat treatment is performed to form a diffusion layer or an oxide film by diffusion of impurities.

以下、この発明の図示の具体例を参照して説明する。Hereinafter, the present invention will be explained with reference to illustrated specific examples.

図中11は拡散炉であって、その中に複数個の半導体ウ
ェーハ12を戦直した拡散ボート13が収容されている
。これら半導体ウェ−ハ12は2個ずつ互いにその裏面
12aを対向させ、かつ「 この裏面12a間の間隔A
が半導体ウェーハ亀2の表面12b間の間隔8よりも狭
くなるようにして並列されている。このようにして半導
体ウェーハ12を拡散ボート13上に配列した状態で不
純物拡散等の熱処理をおこなう場合は、半導体ゥェーハ
12の裏面12aから不純物の飛び散りが生じたとして
も、このような不純物の飛び散りのほとんどは第2図に
示すように半導体ウェーハ裏面12a間で作用するに過
ぎず、又、半導体ウェーハ裏面12a相互の間隔が狭ば
まることにより、その分だけウヱーハ表面12b相互間
の間隔を従来のものよりも大きくとることができるため
、ウェーハ表面12bからの飛び散りの影響も少なくな
るため、半導体装置の特性を支配する半導体ウェーハ表
面12bへの影響は箸るしく緩和されるのである。
In the figure, reference numeral 11 denotes a diffusion furnace, and a diffusion boat 13 containing a plurality of semiconductor wafers 12 is housed therein. These semiconductor wafers 12 are arranged in pairs with their back surfaces 12a facing each other, and have a distance A between the back surfaces 12a.
are arranged in parallel so that the distance 8 between the surfaces 12b of the semiconductor wafers 2 is narrower than that between the surfaces 12b. When heat treatment such as impurity diffusion is performed with the semiconductor wafers 12 arranged on the diffusion boat 13 in this manner, even if impurities are scattered from the back surface 12a of the semiconductor wafers 12, such impurity scattering will be prevented. Most of them act only between the back surfaces 12a of the semiconductor wafers, as shown in FIG. Since it can be made larger than the conventional one, the influence of scattering from the wafer surface 12b is reduced, and the influence on the semiconductor wafer surface 12b, which governs the characteristics of semiconductor devices, is significantly reduced.

第3図は直径2インチのウェーハに拡散をおこなう場合
に本発明の方法に従って、半導体ウェーハ裏面間の間隔
Aを1.物駁とし、半導体ウェーハ表面間の間隔Bを6
.0肋として、不純物拡散をおこなって得られたダイオ
ードの特性を、従来の半導体ゥェーハ表面を一定方向に
向け等間隔で配列して同一条件で不純物拡散をおこなっ
て得られたダイオードの特性とをリーク電流IR評価法
によって比較して示したものである。
FIG. 3 shows the method of the present invention in which the spacing A between the backsides of semiconductor wafers is set to 1. As a matter of fact, the distance B between the semiconductor wafer surfaces is 6
.. The characteristics of a diode obtained by performing impurity diffusion as zero ribs are compared with the characteristics of a diode obtained by performing impurity diffusion under the same conditions with the surface of a conventional semiconductor wafer oriented in a certain direction and arranged at equal intervals. This is a comparison using the current IR evaluation method.

このうち、分布14は従来法の場合、分布15が本発明
の場合を示し、この結果から明らかなように、本発明で
得られる半導体装置は不純物の飛び散り現象による影響
が従来のものと比較して署るしく少なくなることが理解
できよう。なお、本発明において、拡散ボートに並列さ
れる半導体ウェーハの裏面間の間隔は表面間の間隔より
も狭く配列することを特徴とする。
Among these, distribution 14 shows the case of the conventional method, and distribution 15 shows the case of the present invention.As is clear from these results, the semiconductor device obtained by the present invention is less affected by the scattering phenomenon of impurities than the conventional method. As you can see, it becomes significantly less painful. The present invention is characterized in that the spacing between the back surfaces of the semiconductor wafers arranged in parallel on the diffusion boat is narrower than the spacing between the front surfaces.

同時に、半導体ゥェーハの裏面間の間隔は不純物の飛び
散り現象による悪影響を低減するうえで、できるだけ小
さくすることが好ましい。なお、上記実施例では直径2
インチのウェーハについて説明したが、ウヱーハの直径
が変れば、当然不純物飛び散りの影響度合が変るので、
上記間隔A,Bも変えることが好ましい。たとえば2.
5インチ口径のウヱーハの場合はA=1.5帆、B=9
物とし、3.0インチの口径のウェーハの場合はA=2
職、8=12側程度が適当であると言える。
At the same time, it is preferable to make the distance between the back surfaces of the semiconductor wafers as small as possible in order to reduce the adverse effects caused by the scattering phenomenon of impurities. In addition, in the above example, the diameter is 2
I explained about inch wafers, but if the diameter of the wafer changes, the degree of influence of impurity scattering will naturally change.
It is preferable that the above-mentioned intervals A and B also be changed. For example 2.
For a 5-inch diameter wafer, A = 1.5 sails, B = 9
For a wafer with a diameter of 3.0 inches, A=2
It can be said that 8 = 12 side is appropriate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法の−具体例を示すもので、拡散炉内
部の一部を示す断面図、第2図は第1図の姿部を拡大し
て示す側面図、第3図は本発明を従来例と比較して示す
線図である。 図中、11は拡散炉、12は半導体ウェーハ、12aは
半導体ゥェーハ裏面、12bは半導体ゥェ−ハ表面、3
は拡散ボートである。 第h図 第2図 第3図
Fig. 1 shows a specific example of the method of the present invention. Fig. 2 is a cross-sectional view showing a part of the interior of the diffusion furnace. Fig. 2 is a side view showing an enlarged view of the part shown in Fig. 1. FIG. 3 is a diagram showing the invention in comparison with a conventional example. In the figure, 11 is a diffusion furnace, 12 is a semiconductor wafer, 12a is the back side of the semiconductor wafer, 12b is the front side of the semiconductor wafer, 3
is a diffusion boat. Figure hFigure 2Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1 拡散ボートに複数の半導体ウエーハを並列し、これ
を拡散炉内で熱処理する方法において、隣接する2枚の
半導体ウエーハの各裏面を互いに対向させて並列しこの
裏面相互の間隙より表面相互の間隔を大とした状態で拡
散ボートに配置し、熱処理をおこなうことを特徴とする
半導体装置の熱処理方法。
1 In a method of arranging a plurality of semiconductor wafers in a diffusion boat and heat-treating them in a diffusion furnace, the back surfaces of two adjacent semiconductor wafers are arranged in parallel to face each other, and the distance between the front surfaces is smaller than the gap between the back surfaces. A method for heat treatment of a semiconductor device, characterized by placing the semiconductor device in a large state in a diffusion boat and performing heat treatment.
JP7479777A 1977-06-23 1977-06-23 Heat treatment method for semiconductor devices Expired JPS6013299B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7479777A JPS6013299B2 (en) 1977-06-23 1977-06-23 Heat treatment method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7479777A JPS6013299B2 (en) 1977-06-23 1977-06-23 Heat treatment method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS548968A JPS548968A (en) 1979-01-23
JPS6013299B2 true JPS6013299B2 (en) 1985-04-06

Family

ID=13557646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7479777A Expired JPS6013299B2 (en) 1977-06-23 1977-06-23 Heat treatment method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS6013299B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223606U (en) * 1988-08-01 1990-02-16
JPH04321221A (en) * 1991-04-20 1992-11-11 Komatsu Electron Metals Co Ltd Diffusion of semiconductor wafer

Also Published As

Publication number Publication date
JPS548968A (en) 1979-01-23

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