JPS6013307B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which a flip-chip transistor is bonded to a package or a carrier.

Below, we will discuss a wisteria-shaped Schottky barrier gate field effect transistor (hereinafter referred to as "GaAs") using gallium arsenide (GaAs).
The explanation will be given by taking the example of "SBFET").

Figures 1 and 2 are flip-chip type GaASSBF
The general configuration of ET is shown, with Figure 1 being a plan view and Figure 2 being a top view.
The figure is a sectional view taken along the Rolo line in FIG. 1.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is an active layer that is selectively epitaxially grown on this substrate 1, and 3 and 4 are formed on this active layer 2 in ohmic contact with it. 5 is a gate electrode formed on the active layer 2 between the source electrode 3 and the drain electrode 4 so as to have a Schottky contact therewith, and its bonding pad portion is formed on the substrate 1. be.

Thick plated electrodes 6, 7 and 8 are selectively formed on the bonding pads of the source, drain and gate electrodes 3, 4 and 5 by electrolytic gold plating.

Flip chip type Ga melon SB obtained as above
FETs are conventionally mounted on flip-chip carriers as shown in FIGS. 3 and 4.

Figures 3 and 4 show G
The configuration when an aAsSBFET chip is bonded is shown, FIG. 3 is a plan view thereof, and FIG. 4 is a sectional view taken along the line W- in FIG. 3. In FIGS. 3 and 4, reference numeral 9 denotes the source plating electrode 6 shown in FIGS. 1 and 2,
Flip chip type GaASSBFET chip "1" with drain thick plated electrode 7 and gate thick plated electrode 8
0' shows the main body of the flip chip carrier.
The source thick plated electrode 6 is adhered to function as a source electrode terminal that also serves as a heat sink, and the skin C substrate 1
1,! Thick plating electrodes 7 and 8 for the drain and gate are hot-pressed on the strip lines 12 and 14, which serve as the drain and gate electrode terminals, respectively.

Flip chip type Ga ship SBF configured as above
The operating mechanism of ET is well known, so I will not discuss it again.
p) type Ga mother SBFET uses lead wires for bonding, whereas “flip chip type GaAsSB
Since FETs do not use lead wires at all, the inductance component becomes extremely small.Especially when used as an amplifier, reducing source inductance directly leads to improving amplification gain, making it effective for increasing gain. It is.

However, on the other hand, in order to uniformly bond the chip 9 to the carrier 101, the thickness of the MC substrates 11 and 13 on each side of the drain and gate of the carrier 10 and the height of the protrusion on the source side must be adjusted as much as possible. The maximum tolerance is approximately 0.005 mm, which is an order of magnitude stricter than general machining accuracy, making it extremely difficult to manufacture. This method had the disadvantage of being difficult to mass-produce. This invention was made in view of the above points, and it is possible to improve mass production by heat-pressing an additional electrode onto the electrode of a chip or a thickly plated electrode, and by soldering the electrode terminal of a carrier and the additional electrode. The object of the present invention is to obtain a flip-chip type transistor device with excellent performance.

FIGS. 5a to 5d sequentially show the manufacturing process of a flip-chip type GaAsS8FET according to an embodiment of the present invention, and in the figures, the same reference numerals as in FIGS. 1 to 4 indicate the same or corresponding parts. .

In Figures 6a to 6d, this embodiment shows that the plated electrode 6 of the main body 10 is thicker than the thickness of the skin C substrates 11, 13 with strip lines 12, 14, respectively, as shown in Figure a. The protrusions 15 to be bonded are formed to have a high height, and thick plated electrodes 6, 7, 8 are formed on the source, drain, and gate thick plated electrodes 6, 7, and 8 of the chip 9, respectively, as shown in FIG. The additional electrodes 16, 17 and the hook 8 are formed by heat-pressing gold in the shape of a bong or protruding from the end surface of the electrode.

Next, as shown in FIG. By soldering while applying pressure, the solder pots 9 on each electrode terminal 15, 12 and 14 are formed as shown in Figure d.
, 20 and 21 are crushed, the height is automatically adjusted, and at the same time, a strong bushing is achieved. At this time, the additional electrode holes 6, 17, and 18 prevent excess solder from flowing out and adhering to portions of the chip 9 other than the thickly plated electrodes 6, 7, and 8. In this embodiment, even if there is a step between the upper surface of the protrusion 15 of the carrier body 10 and the upper surface of each MIC board 11, 13, the solder 19 interposed on the protrusion 15 strip lines 12, 14 , 20 and 21, the thick plated electrodes 6, 7 and 8 of the flip-chip type GaASSBFET chip 9 are connected to the corresponding protrusions 15 and strip lines 12 and 14, which are the electrode terminals of the main body IQ. It can be bonded uniformly, which eliminates the need to strictly maintain the machining accuracy of the carrier body 10 and ultimately the chip 9, and makes it possible to easily and stably manufacture this type of flip-chip type GaAsSBF8T with high gain with good reproducibility. Can be manufactured.

In the above embodiment, the additional electrodes are arranged on the source/drain and gate electrodes, but it may be applied only to the source electrode, and the number of additional electrodes is not limited to one or more. Furthermore, the material can be selected as appropriate depending on the application, such as gold or aluminum.

Furthermore, in the above embodiment, the case where the present invention was applied to a lateral Schottky barrier gate type field effect transistor using Ga pine was described, but it goes without saying that the present invention can be applied to all other flip chip type transistors.

[Brief explanation of the drawing]

Figure 1 shows a typical flip-chip type GaASSBFET.
A plan view showing the structure of the chip, FIG. 2 is a sectional view taken along the low D line in FIG. 1, and FIG. 3 is a conventional flip-chip type GaAsS.
A plan view showing the configuration of a BFET bonded onto a flip chip type G, FIG. 4 is a sectional view taken along line W-N in FIG. 3, and FIGS.
FIGS. 3A and 3B are cross-sectional views sequentially showing manufacturing steps according to an embodiment when applied to an aAsSBFET. FIGS. In the figure, 1 is a GaAs substrate, 2 is an active layer, 3 is a source electrode, 4 is a drain electrode, 5 is a gate electrode, 6 is a source thick plated electrode, a drain thick plated electrode, 8 is a gate thick plated electrode, 9 is a flip-chip type Ga fake SBFET chip, 10 is the carrier body, 11' is the drain side MIC
Board, 12 is the strip line, 13 is the gate side skin C.
14 is a strip line, 15 is a protrusion, 16 is an additional electrode on the source side, 17 is an additional electrode on the drain side, 18 is an additional electrode on the gate side, wings 9 are solder on the source side, 20 are solders on the drain side, and 21 are gate electrodes. The solder on the front side is shown. Note that the same reference numerals in each figure indicate the same or corresponding parts. 1st
Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. In a device in which a flip-chip transistor is mounted with a plurality of thick plated electrodes formed on a package or carrier, one of the package or carrier
The electrode terminal is formed higher than other electrode terminals, and
An additional electrode having a larger area than the thick plating electrode is provided on the thick plating electrode of the flip-chip transistor corresponding to the first electrode terminal, and molten solder is interposed between the additional electrode and the first electrode terminal, Press the flip-chip transistor against the package or carrier until the other thickly plated electrode of the flip-chip transistor electrically contacts the other electrode terminal of the package or carrier, crushing the molten solder. A method for manufacturing a semiconductor device characterized by the following.