JPS6013487B2 - Input/output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output circuit that can smoothly input and output signals and is suitable for concealing the key of an electronic device having a liquid crystal display device.

Recently, the development of LC (liquid crystal) has progressed, and electronic desktop calculators,
It is being put to practical use as a display element for electronic watches or measuring instruments, and attempts are being made to combine it with a 1-chip LSI (Large-Scale Integrated Circuit). ) number must be reduced as much as possible.

Figures 1 and 2 show a key input method in which the number of pins is reduced in a conventional calculator LSI that drives a light display tube, 1 is the light display tube, 2 is its segment electrode, 3
is a grid electrode, 4 is a filament, 5 is a filament power supply, 6 is a keyboard section, and 7 is an LSI having a logic circuit.
It is.

This reduces the number of pins by using the digit signal that drives the grid electrode 3 for key input, so that when key m is operated, key input K is input. A digital signal D, is input to the key 17, and by detecting this signal D inside the ridge 17, it is determined that the key G has been operated. However, when using a liquid crystal as a display element, due to the lifespan and switching characteristics of the liquid crystal, it is necessary to use AC lighting and drive with a signal that has a longer cycle than a light-receiving display tube, and the long cycle of this signal is a key factor. Since the response time is short compared to the touch time, the conventional method of reading the keys of the crab optical display tube cannot be applied, and it was necessary to create a signal exclusively for reading the keys separately from the signal for driving the liquid crystal. Figures 3 and 4 show how to read the keys of a calculator using a conventional liquid crystal display device.
The digit display is shown.

This is to connect digit selection signals LCD, -LCD4 and segment drive signals Sa, -Sp2 from the LSIII to each display section 12 in a time-division manner, and selectively display liquid crystal segments a to g, p. In this case, the voltages Va and Vb of the liquid crystal drive signals LCD, ~LCD4, Sa, and ~Sp2 are, for example, ±12 [V] due to the liquid crystal characteristics.
, ±6 [V], which is extremely high. Alternatively, the 111 must be operated at a low voltage to take advantage of the low power consumption characteristics of the liquid crystal, and therefore a complementary MOS etc. is used, but in that case the power supply voltage (-Vo.) of the LSIII is -6 [V] The degree is low. Further, the period of the liquid crystal driving digit signal LCD, etc. is very long as illustrated in FIG. For example, if the basic frequency of a calculator is 50k, then T, = 20 seconds, so L of the digit signal is 1280 x 20ms = 25.6ms. As mentioned above, the amplitude of the liquid crystal drive signal LCD, etc. is higher than that of the logic section of LSIII, and the period is longer than the key touch time, so the signal LCD, etc. It cannot be used as a direct key-down signal.

Therefore, the Shinchu V used inside the LSIII. . The timing signals D, ~Dn of the LSI are used as key reading signals.
Dedicated input K for external extraction and key logic for that purpose.
It becomes necessary to provide a ~Km terminal, but if, for example, 23 keys are required, n=5 and m=5, and 10 external lead-out pins are required for key input in addition to those for driving the liquid crystal. Therefore, in the case of an 8-digit display using the duty 1/4 method described above, there are 4 pins for digit selection signals, 16 pins for segment drive, and 10 pins for 1,000-reading.
If you add a power supply terminal, an oscillation terminal, etc., the number of pins on the BIII becomes extremely large. The present invention has been made in view of the above circumstances, and allows smooth input/output of signals, and eliminates the provision of numerous terminals dedicated to inputting keys of the LCD driving LSI, and instead uses one or two terminals dedicated to inputting the keys of the LCD The present invention aims to provide an input/output circuit that enables key reading by using a drive signal terminal as a key input.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a detailed circuit diagram of a key reading section of a calculator to which the present invention is applied, FIG. 6 is an overall mechanical diagram of this calculator, and FIG. 7 is a liquid crystal drive waveform diagram thereof. That is, the calculator of this embodiment has an 8-digit display using the 1/3 uniting method with a duty of 1/4, and corresponds to the calculator shown in FIGS. 3 and 4.
First, in the present invention, the timing signals used inside the melon 111, as shown in FIG.
, rD2t, are obtained. As shown in FIG. 5, N-channel MOS transistors TR, TR2,
P-channel MOS transistors TR3 and TR4 form a segment drive buffer circuit 14 having a complementary MOS configuration. In this circuit, when both of the pulses rD2L and rD2 are at the -Vb level, the transistors TR, TR4 are turned on by the output via the positive logic OR gate 15, so the transistors TR2 and TR3 act as mere inverters, and the segment drive signal A segment drive signal Sa is supplied to the terminal 16. Segment drive signal Sb,
~Sp2 are also supplied to the corresponding segment drive signal terminals. and pulse rD2t, or r
When D2t, is at the 10Vb level, the transistor TR
,,TR4 is turned off, but the source and drain of an N-channel MOS transistor TR5, which has a small mutual conductance gm and a sufficiently large on-resistance, are connected between the electrode that applies the bias voltage -Vb to the buffer circuit 14 and the output terminal. Therefore, if the transistor TR5 is turned on at the same time as the transistors TR, .TR4 are turned off, the segment drive signal Sa, .about.p2 is always at the 1 Vb level when the pulses rD2t, .rD2t are established, as shown in FIG. Here, the timing pulses rD2t,, rD2L'
Since the pulse length is sufficiently narrow compared to the segment drive signals Sa, ~Sp2, for example, 1'160 in this embodiment, it does not affect the liquid crystal display in any way, and the period is sufficiently small compared to the key touch time. Therefore, the segment drive signal becomes -Vb level once during one pulse. Then, each segment drive signal output terminal shown in FIG. 5 is connected to one input pulse rD.
2t,,rD2L positive logic NAND gate 1 9,,1
92 to 19,-, , 19, are connected to the other inputs. Further, the drain sides of the P-channel MOS transistors TR6 and TR7, whose sources are connected to the power supply Vb, are led out to the outside of the LSI via terminals 17 and 18, and connected to the keyboard section 13. That is, in this keyboard section 13, each segment drive signal line 20 is introduced from each external lead-out terminal 16 corresponding to the segment drive signals Sa, to Sp2 to the corresponding segment electrode of the liquid crystal display device, and these signal lines are connected to each other. Connect one ends of the corresponding number of keys (two in this case) to the terminals 17 and 18, and introduce signal lines 21 and 22 from the terminals 17 and 18 and connect the other ends of the keys thereto. put. In the above configuration, the keyboard section 13
When no key is operated, the terminals 17 and 18 of Melon 1 and each terminal 16 are not connected, so the pulse rD2t.
Or, since the segment drive signal which becomes -Vb level only when rD2t is at the 10Vb level is output from the segment drive signal output terminal, the L positive logic AND gate 19,
The output k of ~19i, ~k, is always at one Vb level.

Next, for example, when key ■ is operated, segment drive signal S
a, output terminal 16 and pulse rD2t, output terminal 17
However, since transistors TR, TR4 are off at the timing of pulse rD2tl, a current path occurs: power supply (10Vb) - transistor TR6 - transistor TR5 - power supply (-Vb). , the on-low resistance of transistor TR5 is transistor T
Because it is selected to be sufficiently large compared to that of R6,
The potential of the output terminal 16 of the segment drive signal Sa becomes approximately 10 Vb level. Therefore, since the output k of the gate 19 is at the 10 Vb level only when rD2 is established, if this is detected inside the LSI, it can be determined that the key has been operated. As explained above, according to the present invention, since input/output control is performed using the first, fourth, and fifth transistors, signals can be smoothly input/output to the input/output terminal, and the liquid crystal drive signal terminal can be input by key input. Since it can also be used as a key reading terminal, key reading can be performed by simply providing one or two timing signal deriving terminals dedicated to key reading.

Note that in the above embodiment, the segment drive signals Sa, ~Sp
Although the number of pins per pin was reduced by superimposing timing signals rD2L and rD2t on digit selection signal L
Timing signals rD2t,, rD on the CD,~LCD4 side
A similar effect can be obtained by superimposing the two.

Further, as the timing signals rD2t, , rD2t, any pulse can be used as long as the pulse is sufficiently narrow and regular, and the number of pulses can be changed according to the number of keys.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram to explain the key press method of a calculator using a crab light display tube, Fig. 2 is a waveform diagram showing its operation,
Figure 3 is a circuit diagram for explaining the key input method of a conventional calculator using a liquid crystal, and Figure 4 is a waveform diagram showing its operation.
5 and 6 are circuit diagrams showing one embodiment of the present invention, and FIGS. 7 and 8 are waveform diagrams showing its operation. 11... is 1, 12... is liquid crystal display section, 13
...Keyboard section, 14...Buffer circuit, 1
6-18... terminal, TR, ~TR7... transistor, 19, ~19,... gate circuit, rD2, r
D2t, ... timing signal. Figure 2 Figure 1 Figure 3 Figure 8 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1 a first power supply terminal, a second power supply terminal, the first power supply terminal,
a first conductivity type and a second conductivity type connected between a second power supply terminal;
a transistor, third and fourth transistors of the second conductivity type, an input/output terminal connected to a common drain terminal of the second and third transistors, and a gate of the second and third transistors. a fifth transistor of a first conductivity type connected between the first power supply terminal and the input/output terminal, a gate circuit connected to the input/output terminal, and a gate circuit connected to the input/output terminal; 4. Prepare a signal that simultaneously controls the fifth transistor, and output the signal input from the input terminal from the input/output terminal using the first to fourth transistors, and otherwise use the signal input from the input terminal. The feature is that while the inverter made up of the first to fourth transistors is stopped, the input/output terminal is set at a constant level using a fifth transistor, and an external signal is taken in from the input/output terminal using the gate circuit. input/output circuit.