JPS6014382B2 - data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device (channel) of an information processing device system, and in particular, the present invention relates to a data transfer device (channel) of an information processing device system, and particularly to a method for ensuring validity in a channel that performs a data transfer operation by being instructed to specify a main memory address of a data transfer destination and an amount of data to be transferred. Regarding the method of

Generally, in a channel, when a data transfer command word containing the main memory address to start data transfer and the total number of transferred words is given, data is transferred to the main memory at an appropriate frequency depending on the operating speed of the input/output device and the buffer capacity of the channel. is accessed.

In this case, the main memory address is updated every time one word (a unit of data read or written in one main memory access) is read or written, and then 1 is subtracted from the number of transferred words to determine the remaining number of transferred words. Updates ~ Next data transfer and access control to main memory. Accordingly, in this type of channel, the updating of the main memory address and the number of remaining transfer words are executed at each timing using a generally known addition/subtraction circuit, and the validity of the addition/subtraction results is not checked. Even if a parity check was performed, it was mainly a parity check using an addition/subtraction circuit with a parity prediction function.

This parity check method has disadvantages such as an increase in the amount of hardware required for the adder/subtractor circuit due to the parity prediction function, a decrease in calculation speed, and a lack of ability to detect multiple bit errors. The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to eliminate the above-mentioned drawbacks by checking the update results of both the data transfer destination address and the number of transferred words at once. However, it is an object of the present invention to provide a new data transfer device equipped with a validity check function that can detect multiple bit errors in update results without causing a large increase in hardware or a decrease in calculation speed. According to the above, in an information processing device that transfers data between an input/output device and a main memory device in ascending or descending order of main memory addresses by specifying a command word, a data transfer command word is transmitted every time a command for data transfer in ascending order is received. Each time a descending order data transfer command is received, the difference between the data transfer start address and the total number of words to be transferred is held until the data transfer by that command is completed. The main memory address updated according to the data transfer operation and the number of remaining transfer words are input, and the sum is calculated for ascending data transfer, the difference is calculated for descending data transfer, and the main memory address updated according to the data transfer operation and the number of remaining transfer words are input. an arithmetic circuit that outputs an output every time the main memory is accessed for the purpose of the present invention, and a comparison circuit compares the output of the arithmetic circuit with the contents of the constant register, and if a mismatch is detected, access to the main memory is restricted. As a result, stricter validity checks and prevention of failures from spreading can be easily realized.

Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a diagram showing the structure of a data transfer command word address in a data transfer command word address used in the present invention;
FIG. 2 is a diagram showing the structure of the data transfer start main memory address in the first data transfer command word and the total number of transfer words in the second data transfer command word used in the present invention.

The data transfer command word address included in the data transfer command word address shown in FIG.
In a channel that transfers data by automatically fetching a data transfer command word and a second data transfer command word from the main memory, the first data transfer command word contains a data transfer start main memory address, and the second data transfer command word Each command word includes the total number of transferred words. FIG. 3 is a block diagram showing one embodiment of the present invention.

In one embodiment of the present invention, the output of a register 101 that buffers data from the main memory input to an input terminal 100 and the output of an arithmetic circuit 109 are input, and a signal selected by a selection address signal 200 is sent to a register 103. A selection circuit 102 that outputs to register 104, register 105, and constant register 106, register 103, and register 1
04, a selection circuit 107 that receives the output signal of the register 105 and outputs the signal selected by the selection address signals 202 and 203 to the arithmetic circuit 109; and the register 105.
The output signal and the update constant designation signal 112 are input, and the signal selected by the selection address signal 201 is sent to the calculation circuit 1.
The selection circuit 108 that outputs to 09 and the selection circuit 107,1
08 is input, and the selection circuit 102 receives the value obtained by adding the value of the selection circuit 108 to the value of the selection circuit 107, or the value obtained by subtracting the value of the selection circuit 108 from the value of the selection circuit 107.
, inputs the output signals of the arithmetic circuit 109 output to the comparison circuit 110, the constant register 106, and the arithmetic circuit 109,
A comparison circuit 110 that outputs a comparison error signal 111 when the values of both signals do not match, and the comparison error signal 1
1 1 as an input, and a memory access control circuit 113 that controls the access operation to the main memory if there is a comparison error. Next, the operation of this embodiment will be explained.

In ascending data transfer, when the data transfer command storage address is taken from a predetermined main memory area, the data from the main memory is transferred to the register 103 via the input terminal 100, the register 101, and the selection circuit 102. Stored.

Based on the data transfer command address included in the data transfer command list address stored in the register 103, the register 103 issues a request to the main memory to read the first and second data transfer command words from the main memory.

Next, the selection circuit 107 selects the output of the register 103, the selection circuit 108 selects the update constant designation signal 112, the arithmetic circuit 109 adds these signals, and the result of the operation is sent to the register 103 via the selection circuit 102. Store in. When the first and second data transfer command words are sent from the main memory, input terminal IQ0, register 01, selection circuit 102
via the first data transfer command word register 104
Then, the second data transfer command word is stored in the register 105, respectively. Next, the selection circuit 107 selects the register 10
The selection circuit 108 selects the output of the register 105, and the arithmetic circuit 109 selects the data transfer start main memory address included in the first data transfer command word stored in the register 104 and the register 105. and the total number of transfer words included in the second data transfer command word stored in the second data transfer command word, and the calculated output is stored in the constant register 106 via the selection circuit 102.

Next, each time data is transferred to the main memory using the main memory address included in the first data transfer command word stored in the register 104, the selection circuit 107 selects the main memory address of the register 104. selects the update constant designation signal 112, adds these signals by the arithmetic circuit 109, stores the arithmetic output in the register 104 via the selection circuit 102, and the main memory address update ends.

When the main memory address update is completed, the selection circuit 107
The selection circuit 108 selects the number of words to be transferred from the register 105.
selects the update constant designation signal 112, subtracts the value of the selection circuit 108 from the value of the selection circuit 107 in the arithmetic circuit 109,
The calculation output is sent to the register 105 via the selection circuit 102.
The update of the remaining number of transfer words is completed. When the updating of the number of remaining transfer words is completed, the selection circuit 107 transfers the updated memory address of the register 104 to the selection circuit 108.
The updated number of remaining transfer words in the register 105 is selected, and the arithmetic circuit 109 adds them together.

The calculation output of the calculation circuit 109 and the value of the constant register 106 are compared in the comparison circuit 110, and if they do not match, a comparison error signal 111 is sent to the memory access control circuit 113 to prevent the main memory from being destroyed. Control access behavior. On the other hand, in descending order data transfer, the constant register 106 stores the addition result of the data transfer start main memory address included in the first data transfer command word in the ascending order data transfer and the total number of transfer words included in the second data transfer command word. Instead, the value obtained by subtracting the total number of transferred words from the data transfer start main memory address is stored in the constant register 106.
In addition, instead of storing the addition result of the main memory address and the update constant designation signal in the main memory address update in the ascending data transfer in the register 104, the update constant designation signal is subtracted from the main memory address, and the calculation is performed. Instead of storing the result in the register 104 and comparing the addition result of the updated main memory address and the updated number of remaining transfer words in the ascending order data transfer with the constant register 106,
As explained above, except for comparing the value obtained by subtracting the updated number of remaining transfer words from the updated main memory address with the constant register 106, the present invention performs the data transfer included in the data transfer command word. The sum or difference between the starting main memory address and the total number of transferred words is stored outside a constant register, and the sum or difference between the main memory address, which is updated each time a transfer is made, and the remaining number of transferred words is calculated, and the calculated output is used as described above. By comparing the main memory address with a constant register and restricting the access operation to the main memory if an error is detected in the updated main memory address and the number of remaining transfer words, the main memory, which is the main control operation of the channel, is A comprehensive check of updates to addresses and the number of messages left to be sent can be carried out at once, and as a result, the validity of channel operations can be confirmed and failures can be prevented from spreading when malfunctions occur.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an illustrative example, and it goes without saying that the present invention is not limited only to the embodiment described herein.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the structure of the data transfer command word address in the data transfer command statement address used in the present invention, and Figure 2 is the data in the first data transfer command word used in the present invention. FIG. 3 is a block configuration diagram showing an embodiment of the present invention, which shows the structure of the transfer start main memory address and the total number of transfer words in the second data transfer command word. 100...Input terminal, 101...Register for buffering data from main memory, 102...
Selection circuit, 103...Data transfer command register, 104...First data transfer command register, 105...Second data transfer command register, 106...Constant register, 107,
108... Selection circuit, 109... Arithmetic circuit, 110... Comparison circuit, 1 1 1...
・Comparison error signal, 1 12…. ...Update constant designation signal, 113...Memory access control circuit, 200...
... Selection address signal of selection circuit 102, 201.
...Selection address signal of selection circuit 108, 202
, 203... Selection address signal of the selection circuit 107. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In an information processing device that transfers data between an input/output device and a main memory device in ascending or descending order of main memory addresses by specifying a command word, each time an ascending order data transfer command is received, the data transfer command word is The sum of the included data transfer start main memory address and the total number of transferred words is calculated, and each time a descending data transfer command is received, the difference between the data transfer start main memory address and the total number of transferred words is calculated until the data transfer by that command is completed. The sum is calculated for data transfer in ascending order each time the main memory is accessed for data transfer by inputting the constant register to be held, the main memory address updated immediately after the data transfer operation, and the number of remaining transfer words. , for data transfer in descending order, has an arithmetic circuit that outputs a difference, and a comparator circuit that compares the output of the arithmetic circuit with the contents of the constant register, and transfers the data to the main memory according to the output of the comparator circuit. A data transfer device characterized by controlling access operations of.