JPS60150327A - Interpolation type A/D converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an interpolation type A/D converter, and particularly to an interpolation type A/D converter suitable for LSI implementation.

[Background of the invention]

Various types of A/D converters are known for converting analog signals into digital signals, and interpolation type A/D converters operate at a relatively low speed like audio encoders. As shown in FIG. 1, the interpolation type A/D converter converts the input analog signal Xn and the output qn of the local D/A converter 7 into an error voltage en ("Xn-q"
n) and then input to the integrator 4. The output of the integrator 4 indicates a cumulative error Σε□, and the comparator 5 determines whether this error is positive or negative. The output of comparator 5 is control clock 2
The signal is then input to the bidirectional shift register 6. Here, in the bidirectional shift register, the output of comparator 5 is positive (hereinafter "1'").
), then II I II is negative from the LSB side (hereinafter r
Shift 110" from the MSB side of the r O++)
Let them input. The local D/A converter 7 updates the quantization level (In) according to the contents of this bidirectional shift register.

Here, by making the sunblink frequency f5 sufficiently larger than the Nyquist frequency, the number of adoption steps of the local D/A converter can be reduced, and the output digital signal can be digitally averaged using an external circuit not shown here. By doing so, it is possible to equivalently obtain highly accurate A/D conversion results.

The interpolation type A/D converter has a larger number of D/A converter steps than the conventional Δ-M, Δ-Σ type A/D converter; The sampling frequency f9 can be lowered, and the operating characteristic specifications of operational amplifiers, etc. can be relaxed. However, in reality, the response is insufficient, and as a result of these eight measures, in order to improve the tracking of the D/A converter output with respect to (A Per-Cha
nnelA/D Convert, er llavin
g 15-5e15-5e μ-255Con+pa
nding IEEE,Transaction on
Covnunical;jonsVol, COM 2
4. Nol P33-42. , January 197
6). FIG. 2 shows a concrete configuration of the above-mentioned conversion) 1. 1
An analog signal is applied at the input terminal. 2 is a control clock input terminal, 3 is an inverting amplifier, 4 is an operational amplifier, 5
is a comparator, 6 is a bidirectional shift register, and 7 is a local D/A.
Converter, 8 to 10 are resistors (resistance value RI.

RI2. R, ), 11 is a capacitor (capacitance value C). Here, R3/R1 and Ryo/R2 become the high frequency gain of the integrator, realizing an instantaneous error (xn-qn) voltage switch, and performing integration with time constants R and C.

Therefore, the output voltage Vn of the operational amplifier 4 is R.

As =R2=R3=R, ■n=ε. +Σε. ......(1). The operations below the comparator are the same as in FIG.

Furthermore, the D/A converter 7 has conventionally used an R/2R ladder and a constant current source (current value I) (AnIntegr
Per-Channel PCM Enco
der Ba5ed 0nInterpolation
IEEE Journal of 5olid-3t
ate Circuits, Vol, 5C-14, No1
．． p14-20. February 1979).

The interpolation type A/D converter described above has the following problems.

(1) Sampling period Ts (”1/f −)
Optimization is required when the RC time constant is 1 to 1.5, and highly accurate R and C are required.

(2) Interpolation A for the purpose of increasing the sampling period T6
/D converter increases RC. For example, f −=
51.2 KHz, R, C=Ts, then R=
When IKΩ, C=2000PF, and if it is to be realized by LSI, R9 and C will be externally attached due to accuracy and the size of the element value.

(3) To suppress variations in local D/A converters,
High accuracy is higher than R/2R1 constant current.

(4) To realize the above resistance and constant current source in LSI,
1- It is necessary to add an adjustment circuit for the rimming circuit, which significantly increases the chip size.

(5) Since a large number of constant current sources are used, power consumption increases.

[Purpose of the invention]

An object of the present invention is to provide an economical interpolation type A/D converter that eliminates the need for large-value resistors and capacitors and can be expected to achieve better characteristics without using a constant current source.

[Summary of the invention]

In order to achieve the above object, in the interpolation type A/D conversion circuit, the local D/A converter is composed of a capacitor array and a resistor array, and the difference and integration circuits are composed of switched capacitor circuits.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail by way of examples.

FIG. 3 is a circuit diagram of one embodiment of the interpolation type A/D converter according to the present invention, and FIG. 4 is a timing diagram for explaining the operation of FIG. 3. In FIG. 3, 1 is an input terminal for an input analog signal (hereinafter referred to as xn), and 2-1, 2-2 are control clock signals (φ, respectively).

φ2) input terminal, 3 is not actually needed but is an inverting amplifier written in the explanation, 4-1.4-2 is an operational amplifier, 5 is a voltage comparator, 6 is a bidirectional shift register, 7 is a local D /
A converter, 8 is an inverter, 9-1 to 9-5 are switches, and 10-1 to 10-5 are capacitors. When the clock signal φ is at a high level (hereinafter referred to as 'J'), the switch 9
-1°9-4 is turned on and the output qn of the local D/A converter changes, the operational amplifier 4-1. ．． 4-2 each output v
, v becomes the following equation.

ill 211 v ”-(Xn-qn) ・・・・・・・・・・・・(
2) 11 v = (xn qn) + v ・・・・・・・・・・・・
・(3)a-1 At this time, the voltage ΔV between the input terminals of the comparator 5 is ΔV=V
-V = (xn (In) + [: (xn - Qn) + v
]・・・・・・・・・・・・・・・(4). Here, equation (3) is the cumulative error Σε. , (4) is ε. +Σ
ε. Therefore, FIG. 3 realizes the same function as the circuit shown in FIG. 2. Here, capacitors 10-1 to 10-3
The error voltage gain is determined by , and the integral gain is determined by 10-4 to 10-5.Since the capacitance ratio is much more accurate than the resistance ratio, a small value that can be easily incorporated into an LSI can be used. On the other hand, when the clock signal φ1 is at a low level (hereinafter referred to as "0"), the switches 9-2, 9-3 and 9-
5 is turned on, and the input and output of each operational amplifier are short-circuited. Even if the operational amplifier has an offset, the capacitors 10-3 and 10-4 are charged during this period, so the clock signal φ is "1'' when v, ll, v211
No offset effect occurs.

FIG. 5 shows a circuit diagram of an embodiment of the local D/A converter 6 constructed using a capacitor array and a resistor string. The input signal 6-1C or lower E,) has the polarity with the D/A converter, 6-2~
6-9 (hereinafter referred to as E1 to Ea) are the outputs of the 8-bit bidirectional shift register, with E□ as MSB and Ea as LSB.
shall be. 2 is a control clock signal (hereinafter referred to as φ), 4-3 is an operational amplifier, 9-9 to 9-36 are switches, 8-1 to 8
-11 is an inverter, 11-1 to 11-9 are AND circuits, and 10-6 to 10-12 are capacitors (each capacitance is C
, C, 2C, 4G, 8G, 16G, 32G) ■2-1~
12-5 is a resistor (resistance value is R94R, 8R, 16R respectively)
, 3R), 14 is an output terminal of the D/A converter, and 13 is a reference voltage (hereinafter referred to as V□A) input terminal. Here, the voltage of the signal line to which one ends of the switches 9-26 and 9-27 are commonly connected is vl, the switches 9-28 and 9-29.9. −
30 and 9-31.9-32 and 9-33.9-9 to 9-1
VI2.2, respectively. V.

V4. Let V. Now, E,==”1″*Et=E8
= "O", the switch 9-9 is turned on by the AND circuit 11-4 and becomes -vR"■nvv/32. On the other hand, at this time, the switch 9-26.9-28.9-31
．． 9-33 is turned on, V, = ■, v2 = Ov, v
3=v12. v4=Ov and RIF. In this state, when the clock signal φ becomes 111'1, the lower electrode of the capacitor 10-6 changes from ■3 to O■, but the lower electrodes of the capacitors 10-2 to 10-6 become E, ~E a = II Q II, so it does not change. Therefore, the output qn of the operational amplifier is given by the following equation.

'In=Va/32=Vyu,/32''...
・(5) Next, if Ea ~ E8="1", v, = v
.

V2=OV, V:I=VR=29/
32 V RIF -V 4=Ov, so when the clock signal φ becomes ll 177, qn becomes the following equation.

On the other hand, when F, == II Oyy, v, = ov
, v.

"V, V,, = OV, V4 = V-. Here,
When E1-F8=41 Q II.

'I n = VBgp/32'' --------・
,, (7) When E, ~E, = 111", then Vuip/32" = 1/3
Tosult, each output turn of the bidirectional shift register (
Output q of the D/A converter according to E1 to E8). is the 6th
The result will be as shown in the figure.

Here, the circuit shown in FIG. 5 includes the inverting amplifier 3 of FIG.
Operational amplifier 4-1. D/A converter 7, switch 9-3,
Includes capacitors 10-1 and 10-3. Therefore, the negative input terminal of the operational amplifier 4-3 in FIG. 5 is connected to the input terminal 1 of the input analog signal Xn shown in FIG.
If the capacitor 10-2 is added, the output qn of the output terminal 14 becomes the voltage qn in FIG. This can be easily achieved.

Although this embodiment is based on the premise of a local D/A converter having an 8-bit configuration, the number of bits is not particularly limited.

〔Effect of the invention〕

According to the present invention, the capacitance ratio has much higher precision than the resistance ratio, and the resistor string circuit used here does not require absolute precision, so capacitors and resistors with small areas can be used. Eliminates the need for external resistors and capacitors,
In addition to improving equipment costs and packaging density,
Since a constant current source circuit is also not required, there is an effect of reducing the power consumption of the LSI.

[Brief explanation of drawings]

Figure 1 is a general configuration diagram of an interpolation type A/D converter, Figure 2 is a configuration diagram of a conventional interpolation type A/D converter, and Figure 3 is an example of an interpolation type A/D converter according to the present invention. A configuration diagram of the embodiment, FIG. 4 is a timing diagram explaining the operation of FIG. 3, FIG. 5 is a circuit diagram of the local D/A converter in the embodiment of the present invention, and FIG. 6 is a local D/A conversion diagram. FIG. In FIG. 1, 1...analog signal input terminal, 2...
... Control clock signal input terminal, 3... Operational amplifier,
4... Integrator, 5... Comparator, 6... Bidirectional shift register, 7... Local D/A converter. In Fig. 2, 1...input analog input terminal, 2...
...Control clock signal input terminal, 3...Inverting amplifier,
4... Operational amplifier, 5... Comparator, 6... Bidirectional shift register, 7... Local D/A converter, 8-10
...Resistance, 11...Capacitor. In FIG. 3, 1... input analog signal input terminal;
2-1, 2-2... Control clock signal input terminal, 3.
... Inverting amplifier, 4-1.4-2... Operational amplifier, 5
...Comparator, 6...Bidirectional shift register, 7...
・Local D/A converter, 8... Inverter, 9-1 to 9
-5...Switch, 10-1 to 10-5...Capacitor. In FIG. 5, 2... Control clock signal input J terminal, 4... Operational amplifier, 6-1 to 6-9... Bidirectional shift register output terminal, 4... D/A converter output Terminals, 8-1 to 8-11... Inverter, 9-9 to 9-3
4... Switch, 10-6 to 10-12... Capacitor, 11-1 to 11-9... AND circuit, 12th
1 cause etc. 2 causes B Indication of written amendment case of 1984 Patent Application No. 5584 Name of the invention Interpolated form A/l) Relationship with the person who makes the converter amendment Patent applicant name Name (5101 Stock Company 1 Hitachi Works Fee
Assistant Director jE (D Column supplement 1 for the detailed description of the invention in the subject specification
1-Contents 1, My original claim! II+,! :・ On page 7, line 19, “
Ishidaba 8:;] is corrected to "if it occurs." 2. rV+=VJ in the same book 2, page 9, line 15
Correct it to "l=v". 3. Ibid., page 10, line 7' ” V, V 3
Correct ``'OVJ to r''V, V3 = OVJ by hIj. 4, same J-, ;j), "A" on the third line of page 11, "If you add, the output terminal of" is corrected to "If you add A, four, and h, the output terminal of FIG. 5." I-1 d

Claims (1)

[Claims] an integrating circuit section that detects and integrates the error between the input signal and the feedback signal; a comparator that compares and determines whether the output of the integrating circuit is positive or negative; and a bidirectional shifter 1 that digitally integrates the output of the comparator.
- An interpolating A/D converter comprising a register and a D/A converter that converts the output of the bidirectional shift register into an analog signal and generates the feedback signal, in which a plurality of the D/A converters are used. interpolation type A/ D converter.