JPS6016038B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter referred to as IG
This invention relates to a large-capacity, high-speed storage device whose main component is a FET (hereinafter referred to as FET).

In a memory device that has an IGFET as its main component and is an integrated circuit, it is necessary to charge and discharge the capacitance of the digit line, which inevitably increases as the capacity increases, during readout. It accounts for a large proportion.

Therefore, in order to obtain a high-speed, large-capacity storage device, it is necessary to shorten the charging and discharging time of the digit line. To achieve this, the first step is to reduce the capacitance of the digit line as much as possible. Second, a large current is passed during charging and discharging. A third method is to detect small voltage changes in the digit line. The first method is contrary to the idea of increasing the capacity of the storage device, and is not easily realized because it is related to the structure of the storage element itself. The second method is limited by the ability of the storage element to flow current, and therefore cannot be implemented depending on the type of storage element. For the above reasons, the third method, that is, the method of detecting minute voltage changes on the digit line with high sensitivity and high speed, is important. Hereinafter, an electrically programmable read-only memory device (hereinafter referred to as EPROM) using a floating gate avalanche injection type insulated gate field effect transistor (hereinafter referred to as FAMOS) as a memory element will be explained as an example of a conventional memory device. Reveal shortcomings.

FIG. 1 is a partial circuit diagram of a conventional EPROM.

The first point B, , B8, . . . of the digit line serves as a memory element.
...Ba, B22. FAMOS, M, . ,,M,. 2...,M,2,,
M22,... Pond,. , Ma2,..., the X address line X supported and competed with the control electrode of the FAMOS,
, IGFETS for Y address switching connected to
．． , S, 2, ..., the Y address switching IGF
At the common drain of the ET, the IGFETQ, . ,Q2,
．． . . ., and write information lines D,, D2, . . . Write power supply P, IGFETs Q, 2, Q22, inserted to separate the power supply CC from the write power supply during writing.
IGFETQ, 2, Q22, ...... and the isolation signal line connected to the gates of the same IGFETs.
At the respective drains of Q, 2, Q22, . . ., the third point U,, U2, . and the elements RL, RL2, . . . , the elements U, U2, .
... Inverting multipliers 1, 12, ... Z0 with input points
...and the output of the inverting multiplier ○,,02,...
...consists of... The operation of this example is as follows. Note that descriptions of write operations and the like that are not directly related to the present invention will be omitted. Also, for convenience of explanation, FAMOS, IGF
All ETs are of N-channel type, the box Z source is positive, and the logic is positive logic.

When reading, one each of the × address line and Y address line is “
1” and others are “0” For example, X, and Y are “1” and others are “0”
”, FAMOSM, . . . is selected.

At that time, the same FAMOSM,. , the same FAMOSM, . , is determined whether it is suitable or not. Note that during reading, the signal on the separation signal line R is “1”.
”, the IGFETs Q, 2, Q22, . . . are conducting, and conversely, the write data lines D, D2, . . .
The signals of IGFETQ, . ,2Q,2,・
... is non-conducting. The reversely selected FAMOSM, . ，
If the conductivity of FAMOSM, . , and the voltage on the digit line decreases. 3 On the contrary, FAMOSM,. ，
If is non-conducting, the capacitance of the digit line is equal to the load resistance element R
is charged through L, and the voltage on the digit line increases.

FAMOSM selected as above. A multiplier 1, which inverts the voltage of the digit line that changes depending on the conduction or non-conduction of ,
This storage device functions by increasing the amount of data. The above is the basic operation of this example, but as described below, in a configuration like this example based on the conventional technology, a large capacity and high speed EPR
You can't get OM. In general, the current that can be passed through a FAMOS is from several tens of μA to at most a hundred and several tens of μA, as long as the FAMOS is limited to a practical size.
The equivalent resistance of the load resistance element is RL, the capacitance of the digit line is Cd, the power supply voltage is Vcc, the voltage of the digit line is Vd, and IGFETQ,2 and IGFETS, . If we ignore the resistance of FAMOSM, . , is non-conductive, Vd, = Vcc (11 e c Uryu L)...
...(11 However, the initial value of the voltage Vd of the digit line (time t
=0) was set to 0 considering the worst condition.

On the other hand, when the FAMOSM river is conducting, Vd: V
cc-RLION (11e before c)...{2) However, the initial voltage of the digit line Vd is Vc considering the worst condition.
c.

Each can be expressed as Also, from the equation 2), it is possible to find the time until the voltage Vd of the digit line reaches a constant value Vd*, for example, Vcc = 5 (v), RL = 50 kilohms, Cd = 10 picofurad, loN = 50. microphone.

If ampere, Vd* = 3.5 (v), charging time =
602 nanoseconds.Discharge time W=458 nanoseconds.

It is possible to make the value somewhat farther than the value in the above example by adjusting the value of R and Vd*, but as long as the power supply voltage Vcc, digit line capacitance Cd, and FAMOS current ION are about the same as in the example above, it will not be large. No intermediate speed improvement can be expected. The operation of the inverting multiplier 1 is to detect that the digit line voltage VQ has become close to the above-mentioned constant value Vd*.
, it is not possible to improve the operating speed of this example by increasing the performance of . As described above, this example of the prior art cannot be used with a large-capacity, high-speed EPROM. SUMMARY OF THE INVENTION An object of the present invention is to provide a large-capacity, effective, high-speed storage device that eliminates the above-mentioned drawbacks. A memory device according to the present invention includes at least a plurality of memory elements, an address line, a digit line, and a detection means for detecting a voltage of the digit line that changes depending on the storage contents of the memory element. The memory element is a memory element in which it is determined whether or not a current can be passed through the memory element itself according to the stored content, and a push-pull type inverting multiplier that receives the digit line as an input is provided as the detection means,
The input and output of the inverting multiplier are short-circuited through an element having a resistive component at least during the readout period, and the output voltage becomes higher than a certain value in the direction of the power supply compared to the input voltage. At least one insulated gate field effect transistor is connected between the input and output of the inverting multiplier.

Next, examples according to the present invention are shown in FIGS. 2, 3, and 4.
This will be explained with reference to the figures.

FIG. 2 is a circuit diagram showing an embodiment according to the present invention.
The portion labeled C is exactly the same as the portion labeled MC in FIG. 1, which is a circuit diagram of a memory circuit according to the prior art, so a description thereof will be omitted. According to the present invention, the configuration of the embodiment includes a plurality of FAMOS as memory elements connected in a matrix, and one FAMOS is inversely selected in response to an address signal and electrically connected to a digit line DL. Block MC
and a push-pull type inverting multiplier IV whose inputs are the digit line DL, a feedback resistor RF connected between the digit line DL and the output S of the inverting multiplier IV, and a source and a drain connected to the digit line DL. and an enhancement type feedback IGFETQF whose gate is connected between the output point S of the inverting amplifier. Note that although the drawings and explanations refer to only one output, it goes without saying that the same number of circuits as the number of outputs are required. Next, the operation of the embodiment according to the present invention will be explained with reference to FIGS. 2, 3, and 4.

Note that FIG. 3 is a schematic diagram of the input/output characteristics of the inverting amplifier IV,
FIG. 4 shows the digit line D corresponding to FIGS. 2 and 3.
2 is a schematic diagram of the voltage waveforms at the output point S of the inverting multiplier IV; First, a case will be described in which the selected FAMOS (in the MC block) is non-conductive and therefore the digit line DL is charged.

Assuming that the address changes and charging starts at time t, the value of the voltage VoL of the digit line DL at time t is assumed to be 0 (v) considering the worst condition. At that time, the output voltage Vs of the inverting amplifier W is the voltage Vcc of the power supply CC or a value close to it (corresponding to point a in Figure 3 and point bs in Figure 4). In this case, [Vs - VoL] is for feedback. Because it is sufficiently higher than the threshold voltage VTh of IGFETQF,
A very large current flows through the ETQF to the digit line DL.
flow to rapidly fill the large capacity added to the Therefore, the voltage V on digit line DL. L rises rapidly. Note that, as will be described later, the current flowing through the feedback IGFET QF has little to do with the operation during discharging, which is different from the prior art example described above. Therefore, the equivalent resistance value RT of the feedback IGFETQF can be designed to be as small as necessary for charging. When the voltage VoL on the digit line DL rises to the voltage corresponding to point b in FIG. 3, the output voltage Vs of the inverting multiplier increases due to the change in the voltage VoL on the digit line, as is clear from FIG. The increase rate changes by -A times.

If A is designed to be 30, the voltage of the digit line VoL
When the value changes by 0.1 (v), there will be a change of about 3 (v). In this way, when the voltage VoL of the digit line rises and reaches point c in Fig. 3 (point COL in Fig. 4, time etc.), [
Vs-VDL] is the threshold voltage V of FETQF for feedback.
It becomes equal to Th, and the feedback IGFETQF becomes non-conductive. Therefore, from now on, the current charging the digit line will flow only through the feedback resistor RF. feedback resistance RF
As will be described later, is directly related to the discharge speed, and considering that the higher the RF, the higher the discharge speed, it is not possible to reduce it by considering only the charging speed.In this regard, the example of the prior art described above cannot be considered. The same is true for load resistance. That is, the voltage of the digit line corresponding to point c in FIG. 3 is VoLc, the voltage of the output S of the inverting multiplier is Vsc,
The power supply voltage is set as Vcc, and the voltage when the voltage VoL of the digit line and the output voltage Vs of the inverting multiplier become equal (point d in Figure 3, points ds and doL in Figure 4) is set as Vr, and point c is reached. Based on time, VS is Vr+A (Vr-V.

LC) e-application t=state magazine vThe magazine t...[3'
Expressed as, the vibration is almost the same as that of the feedback IGFETQF,
The value voltage is VTh, and the time constant is extremely small compared to a simple CR, approximately 1/1 of the multiplication rate A of an inverting multiplier. It's speed.

When the charging of the digit line is completed as described above, equilibrium is achieved at the point where the voltage of the digit line and the voltage of the output of the inverting multiplier match. Next, the address changes (corresponding to the 4th figure Riko)
When a suitable FAMOS is selected, the FNMOS current I
In this case, the capacity of the digit line is discharged by turning on, and the voltage of the digit line decreases. It becomes approximately RF+ION, and the time constant becomes approximately three times three times as in the case of charging.

In this case as well, the speed is extremely high as is clear compared to the previous formula 2'. Above, the initial value of the voltage of the digit line is 0 (v
) is mainly charged through the feedback IGFETQF, further charged through the feedback resistor RF, and then the FAMOS
The process of conduction and discharge of the inverting multiplier and the corresponding change in the output voltage of the inverting multiplier have been described, but in both processes, the inverting multiplier operates at a significantly higher speed than the conventional example.

In order to make this point clearer, specific numerical values will be set and explained. Digit line capacitance Cd = 10 picofarand power supply voltage Vcc = 5 (v) Feedback IGFETQ
Equivalent resistance when F is applied Rg = 2 kg (Q) Feedback resistance RF = 50 kg (0) Inverting multiplier increase rate A = 30 Assuming that, charging time through FET QF for feedback is 320 nanoseconds. Charging time through feedback resistor RF: 17 nanoseconds FAMOS
It can be seen that the discharge time is 17 nanoseconds, which is 27 times higher than the sound of one stitch compared to the conventional example.

An inverting multiplier can function in any configuration, but the lower the output resistance of the inverting multiplier, the smaller the capacitance between the input and output of the inverting multiplier, and the smaller the Miller capacitance attached to the input. The smaller the better.

It is also desirable that the intensifier be as large as possible without causing oscillation. The push-pull type inverting multiplier of this embodiment was adopted to satisfy the above conditions. In a normal B/D type inverter (the inverter configured by Q, Q2 in Figure 2), a load IGFET (
(Q, in Figure 2) becomes larger, and the drive IGFET (Q2 in Figure 2) becomes larger in order to increase the power increase rate (the power increase rate is generally determined by the ratio of the size of the drive FET and the load IGFET). (If you increase the ratio in the function, the increase rate will also increase) Therefore, the capacity added between the input and output, that is, the points DL and U in Figure 2 increases, and this capacity is multiplied by the increase rate when viewed from the DL point. In the push-pull type inverting intensifier adopted in this embodiment, which has a very large effect (Miller effect), the above-mentioned drawbacks can be minimized.

In other words, the capacitance between the input and output is determined by the sizes of Q2 and Q4 in Figure 2, but the inverter configured by Q and Q2 is a shallow depletion type IGFET Q3.
Since the load capacity is relatively small since it only drives
, and Q2, it is not necessary to make Q2 so large. Also, Q3 is a shallow depletion type IGFET, and when Q4 is conductive, a voltage is applied to the gate of Q3 to reduce the current.
There is no need to increase the ratio between Q3 and Q3. Therefore, since Q2 and Q4 are small, the capacitance between the input and output, which is approximately determined by the sum of Q2 and Q, can be made sufficiently small.Therefore, the influence of the Miller effect can be reduced, and the output resistance is small, making it suitable for high-speed inversion. It becomes a booster.

As detailed above, the memory device according to the present invention operates completely statically, so there is no need for any timing signals, and moreover, by the action of the feedback IGFET, the memory device according to the present invention automatically operates at the most sensitive point of the inverting multiplier. Because it is biased, even slight voltage fluctuations on the digit line are detected.

Therefore, it is possible to provide a storage device that operates at extremely high speed.

The present invention is of a static type and is applied to a large 0 capacity high speed memory device, and is further suitable for a memory device such as an EPROM in which a large current cannot be taken when the memory element is turned on. Although the above embodiments have been described using an EPROM as an example, the present invention is effective as long as the memory element operates depending on its conduction or non-conduction, and therefore is not limited to EPROMs.

Furthermore, the configuration of the inverting amplifier is not particularly limited as has been omitted in the above explanation, and the feedback resistor does not need to be a pure resistor, but may be a depletion type FE.
Of course, it may be a nonlinear child with T etc. 0,000. Further, the feedback FET constituting the push-pull type inverting amplifier is not limited to the shallow depletion type, but may be an enhancement type or depletion type IGFET.

[Brief explanation of the drawing]

FIG. 1 is a partial circuit diagram of a storage device according to the prior art, FIG. 2 is a circuit diagram showing an embodiment of a storage device according to the present invention, and FIG.
The figure is a schematic diagram showing the input/output characteristics of the inverting amplifier IV, and FIG. 4 is a schematic diagram of voltage waveforms at various parts used to explain the operation. Q in the figure. ,Q,2,S,,,S ratio is IGFET,M,
,,,M,. 2, M goods,,M. 22 is FAMOS, 1,
are inverting intensifiers, R, . is a load resistance element. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a memory device including at least a plurality of memory elements, an address line, a digit line, and a detection means for detecting a voltage of the digit line that changes depending on the memory content of the memory element, the memory element changes depending on the memory content. The storage element is a storage element in which it is determined whether or not a current can flow through the storage element itself, and an inverting amplifier to which the digit line is input is provided as the detection means, and the input and output of the inverting amplifier are at least The readout period is short-circuited through an element having a resistance component, and at least one insulated gate field effect transistor is connected so as to become conductive when the output voltage becomes higher than the input voltage by more than a certain value in the direction of the power supply. A storage device characterized in that a push-pull type inverting amplifier is used as the inverting amplifier in a configuration connected between an input and an output of the inverting amplifier.