JPS6042553B2 - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS6042553B2 JPS6042553B2 JP55115181A JP11518180A JPS6042553B2 JP S6042553 B2 JPS6042553 B2 JP S6042553B2 JP 55115181 A JP55115181 A JP 55115181A JP 11518180 A JP11518180 A JP 11518180A JP S6042553 B2 JPS6042553 B2 JP S6042553B2
- Authority
- JP
- Japan
- Prior art keywords
- digit line
- voltage
- inverting amplifier
- famos
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 3
- XUFQPHANEAPEMJ-UHFFFAOYSA-N famotidine Chemical compound NC(N)=NC1=NC(CSCCC(N)=NS(N)(=O)=O)=CS1 XUFQPHANEAPEMJ-UHFFFAOYSA-N 0.000 description 20
- 238000010586 diagram Methods 0.000 description 8
- 238000007599 discharging Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/067—Single-ended amplifiers
Landscapes
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Description
【発明の詳細な説明】
本発明は絶縁ゲート型電界効果トランジスタ（以下ＩＧ
ＦＥＴと記す）を主な構成要素とした大容量、高速度の
記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter referred to as IG
This invention relates to a large-capacity, high-speed storage device whose main component is a FET (hereinafter referred to as FET).
ＩＧＦＥＴを主な構成要素とし、集積回路化した記憶装
置においては、大容量になるに従つて必然的に増加する
ディジット線の容量を読み出し時に充放電する必要があ
り、その充放電時間が読み出し時間のうち大きな割合を
占めている。In a memory device that uses IGFET as a main component and is integrated into an integrated circuit, it is necessary to charge and discharge the digit line capacitance, which inevitably increases as the capacity increases, at the time of reading, and the charging and discharging time is shorter than the readout time. It accounts for a large proportion of the total.
従つて高速度にして大容量の記憶装置を得るためにはデ
ィジット線の充放電時間を短かくする必要がある。その
ためには第１にディジット線の容量を出来る限り小さく
する。第２の充放電時に大きな電流を流す。第３にディ
ジット線の小さな電圧変化を検出する等の方法が考えら
れる。第１の方法は記憶装置の大容量化と相反する方法
であり、しかも記憶素子自体の構造に直接に関係してい
るため容量には実現出来ない。第２の方法は記憶素子の
電流を流す能力によつて制限されるゆえ記憶素子の種類
によつて実現出来ない。以上の理由により第３の方法、
つまりディジット線の微小電圧変化を感度良く高速度に
検出する方法が重要となる。以下従来技術による記憶装
置として浮遊ゲートアバランシユ注入型絶縁ゲート電界
効果トランジスタ（以下ＦＡＭＯＳと記す）を記憶素子
とした電気的にプログラム可能な読み出し専用記憶装置
（以下ＥＰＲＯＭと記す）を例に説明し欠点を明らかに
する。第１図は従来技術によるＥＰＲＯＭの一部回路図
である。Therefore, in order to obtain a high-speed, large-capacity storage device, it is necessary to shorten the charging and discharging time of the digit line. To achieve this, first, the capacitance of the digit line should be made as small as possible. A large current is passed during the second charging and discharging. A third method is to detect small voltage changes in the digit line. The first method is contrary to increasing the capacity of the storage device, and moreover, it cannot be realized in terms of capacity because it is directly related to the structure of the storage element itself. The second method is limited by the ability of the storage element to flow current, and therefore cannot be realized depending on the type of storage element. For the above reasons, the third method
In other words, it is important to have a method for detecting minute voltage changes in the digit line with high sensitivity and high speed. Hereinafter, an electrically programmable read-only memory device (hereinafter referred to as EPROM) using a floating gate avalanche injection type insulated gate field effect transistor (hereinafter referred to as FAMOS) as a memory element will be explained as an example of a conventional memory device. Reveal shortcomings. FIG. 1 is a partial circuit diagram of a conventional EPROM.
記憶素子としてディジット線の第１の点Ｙ３、、、Ｂ、
Ｏ、・・・・・・、Ｂ。、、Ｂ、２・・・・・・、に並
列に接続されたＦＡＭＯＳ９Ｍｌｌｌ９Ｍ１１２゜＊゛
゜゜゜、Ｍ１２１、Ｍ１２２、＊１’・・・Ｍ２１１、
Ｍ２１２、・・・・・・、前記ＦＡＭＯＳの制御電極に
ノ接続されたＸアドレス線、Ｘ、、Ｘ。、・・・・・・
、Ｙアドレスを指定するＹアドレス線Ｙ、、Ｙ２、・・
・・・・、前記ＦＡＭＯＳの共通ドレインと直列に接続
された前記Ｙアドレス線のうち１本をゲートに接続した
Ｙアドレス切換え用ＩＧＦＥＴＳ、、、５、０、・・・
・・・、５２、７・・・・・・、前記Ｙアドレス切換え
用ＩＧＦＥＴの共通ドレインでディジット線の第２の点
Ａｌ、Ａ２９・・・・・・の電圧を書き込み時に書き込
み情報に応じて充分高くするべく接続されたＩＧＦＥＴ
Ｑ、、、Ｑ。、、 ・・・・・，及び書き込み情報線Ｄ
ｌ，Ｄ２，・・・・書き込み電源Ｐ１書き込み時に電源
ＣＣと前記書き込み電源を分離すべく挿入されたＩＧＦ
ＥＴＱｌ２，Ｑ２。，．．．と、同１ＧＦＥＴＱ１２，
Ｑ２２，・・のゲートに接続された分離用信号線Ｒ１前
記１ＧＦＥＴＱ１２，Ｑ，！２，・・・・のそれぞれの
ドレインでディジット線の第３の点Ｕｌ，Ｕ２・・・・
・と電源ＣＣの間に接続される負荷抵抗として働く抵抗
成分を持つた素子ＲＬｌ，ＲＬ２，・・，前記Ｕｌ，Ｕ
２・・・・・・点を入力とした反転増巾器１１，１２，
・・・・及び前記反転増巾器の出力０１，０２・・・・
・・より構成される。本例の動作は以下のとおりである
。なお本発明と直接関係しない書き込み動定等に関して
は説明を省略する。又説明の都合上ＦＡＭＯＳ，ＩＧＦ
ＥＴは全てＮチャンネル型とし電極は正とし、さらに論
理は正論理とする。読み出し時、ｘアドレス線、Ｙアド
レス線の各々１本が゜゜１゛に他が“゜０゛、例えばＸ
１とＹ１が゛゜１゛に他が゜゜０゛になるとＦＡＭＯＳ
Ｍｌｌｌが選択される。The first point Y3, ,B, of the digit line serves as a storage element.
O......B. ,, B, 2......, FAMOS9Mlll9M112゜*゛゜゜゜, M121, M122, *1'...M211,
M212, . . ., X address line, X, , X connected to the control electrode of the FAMOS. ,・・・・・・
, Y address line Y specifying the Y address, , Y2,...
. . . Y address switching IGFETS whose gate is connected to one of the Y address lines connected in series with the common drain of the FAMOS, 5, 0, . . .
..., 52, 7..., the voltage at the second point Al, A29... of the digit line at the common drain of the Y address switching IGFET is set according to the written information when writing. IGFET connected to high enough
Q,,,Q. ,, ..., and write information line D
l, D2, . . . IGF inserted to separate the power supply CC and the write power supply at the time of writing the write power supply P1
ETQl2,Q2. 、． ．． ．． and the same 1GFETQ12,
Isolation signal line R1 connected to the gates of Q22, . . . 1GFET Q12, Q, ! The third point Ul, U2,... of the digit line at each drain of 2,...
・Elements RLl, RL2, . . ., the elements RLl, RL2, . . . , the elements RLl, RL2, .
2...Inverting amplifiers 11, 12, with input points
...and the outputs 01, 02 of the inverting amplifier...
...consists of... The operation of this example is as follows. Note that descriptions of writing movement determination and the like that are not directly related to the present invention will be omitted. Also, for convenience of explanation, FAMOS, IGF
All ETs are of N-channel type, have positive electrodes, and have positive logic. At the time of reading, one of the
When 1 and Y1 become ゛゜1゛ and the others become ゜゜0゛, FAMOS
Mllll is selected.
そのとき同ＦＡＭＯＳＭｌｌｌに書込れている情報によ
つて同ＦＡＭＯＳＭｌｌｌが導通するか否かが決定され
る。なお読み出し時には分離用信号線Ｒの信号は“１゛
であり、ＩＧＦＥＴＱｌ２，Ｑ２２，・・・は導通して
おり、逆に書き込みデータ線Ｄｌ，Ｄ２・・・・・の信
号は“０゛でありＩＧＦＥＴＱｌｌ９Ｑｌ２・・・・・
・は非導通である。選択されたＦＡＭＯＳＭｌｌｌが導
通すればディジット線（第１、第２、第３のディジット
線を総称）に付加されている容量Ｃｄにたくわえられて
いた電荷はＦＡＭＯＳＭｌｌｌを通して放電されディジ
ット線の電圧は低下する。逆にＦＡＭＯＳＭｌｌｌが非
導通であれば、ディジット線の容量は負荷抵抗素子ＲＬ
ｌを通して充電され、ディジット線の電圧は上昇する。
以上の如く選択されたＦＡｒｌ−４０ＳＭ１１１の導通
、非導通に応じて変化するディジット線の電圧を反転増
巾器１１に．より増巾する事により本記記憶装置は機能
する。以上が本例の基本動作であるが、以下に述べる如
く従来技術による本例の如き構成では大容量にして高速
度のＥＰＲＯＭを得る事は出来ない。一般にＦＡＭＯＳ
に流し得る電流はＦＡＭＯＳを実・用的な大きさに制限
する限り数十μＡから高々百数＋ＰＡであるが、その電
流をＩ。Ｎｌ負荷抵抗素子の等価抵抗をＲし、ディジッ
ト線の容量をＣｄ、電源電圧を■ＣＣｌディジット線の
電圧をＶｄとし、ＩＧＦＥＴＱｌ２及びＩＧＦＥＴＳｌ
ｌの抵抗を無視すれば、充電、つまりＦ，ＡＭＯＳＭｌ
ｌｌが非導通の場合、但しディジット線の電圧■ｄの初
期値（時間ｔ＝０）は最悪条件を考えＯとした。At that time, it is determined whether or not the FAMOS Mll is conductive based on the information written in the FAMOS Mll. At the time of reading, the signal on the isolation signal line R is "1", and the IGFETs Ql2, Q22, ... are conductive, and on the other hand, the signals on the write data lines Dl, D2, ... are "0". Yes IGFETQll9Ql2...
・ is non-conducting. When the selected FAMOS Mll becomes conductive, the charge stored in the capacitor Cd added to the digit line (the first, second, and third digit lines are collectively referred to) is discharged through the FAMOS Mll, and the voltage of the digit line decreases. . Conversely, if FAMOS Mll is non-conductive, the capacitance of the digit line is equal to the load resistance element RL.
The voltage on the digit line increases.
The voltage of the digit line, which changes depending on whether the FArl-40SM111 selected as described above is conductive or non-conductive, is applied to the inverting amplifier 11. This storage device functions by increasing the width. The above is the basic operation of this example, but as described below, it is not possible to obtain a large-capacity, high-speed EPROM with the configuration of this example based on the prior art. Generally FAMOS
As long as the FAMOS is limited to a practical size, the current that can be passed through the FAMOS ranges from several tens of μA to a hundred plus PA at most, but the current is I. The equivalent resistance of the Nl load resistance element is R, the capacitance of the digit line is Cd, the power supply voltage is ■CCl, the voltage of the digit line is Vd, IGFETQl2 and IGFETSl
If the resistance of l is ignored, charging, that is, F, AMOSMl
When ll is non-conductive, however, the initial value (time t=0) of the digit line voltage d is O considering the worst condition.
一方放電、つまりＦＡＭＯＳＭｌｌｌが導通の場合、
〜ノｄ１〜ＢＬ但しディジッ
ト線の電圧■ｄの初期は最悪条件を考えＶｃｃとした。On the other hand, if discharge, that is, FAMOS Mll is conductive,
~d1~BL However, the initial voltage of the digit line d was set to Vcc considering the worst condition.
と各々表わせる。Each can be expressed as
又（１），（２）式より逆にディジット線の電圧Ｖｄが
一定値Ｖｄ幻こなるまでの時間を求める事が出来、例え
ばＶｃＯ＝５（Ｖ）、ＲＬ＝５０キロオーム、Ｃｄ＝１
０ピコファラッド、ＩＯＮ＝５０マイクロアンペア、■
ｄ水＝３．５（Ｖ）とすれば充電時間忙＝６０２ナノ秒
放電時間ｍｌ＝４５８ナノ秒
となる。Also, from equations (1) and (2), it is possible to find the time until the voltage Vd of the digit line reaches a constant value Vd, for example, VcO = 5 (V), RL = 50 kilohms, Cd = 1.
0 picofarad, ION=50 microampere, ■
If d water = 3.5 (V), charging time = 602 nanoseconds and discharge time ml = 458 nanoseconds.
ＲＬ．Ｖｄ来の値を調整することによつて多少は上例の
値より速くする事は可能であるが電源電圧ＶｃＯ、ディ
ジット線の容量Ｃｄ，．ＦＡＭＯＳの電流１。Ｎが上例
程度てある限り、大巾な速度の向上は望めない。なお反
転増巾器１１の動作はディジット線の電圧■ｄが前記一
定値Ｖｄ木近くになつた事を検出するもので、反転増巾
器１１の性能を上ける事によつて本例の動作速度を向上
させる事は出来ない。以上述べた如く従来技術による本
例は大容量にして高速度のＦＰＲＯＭには適さない。本
発明の目的は前述の欠点を除去した大容量化して有効な
高速度の記憶装置を提供することにある。本発明による
記憶装置は、複数の記憶素子とアドレス線とディジット
線と前記記憶素子の記憶内容に応じて変化する前記ディ
ジット線の電圧を検出するための検出手段とを少なくと
も含む記憶装置において、前記記憶素子は記憶内容に応
じて記憶素子自体に電流を流し得るか否かが決定される
記憶素子であり、前記検出手段として前記ディジット線
を入力とする反転増巾器を設け、同反転増巾器の入力と
出力が少なくとも読み出し期間は抵抗成分を持つ素子を
介して短絡され、さらに前記入力の電圧に比べて出力の
電圧が電源方向に一定値以上高くなつたとき導通する如
く少なくとも１個の絶縁ゲート型電界効果トランジスタ
を前記反転増巾器の入力と出力の間に接続して構成され
る。R.L. It is possible to make it somewhat faster than the value in the above example by adjusting the value of Vd, but the power supply voltage VcO, the digit line capacitance Cd, . FAMOS current 1. As long as N remains at the same level as in the above example, no significant speed improvement can be expected. The operation of the inverting amplifier 11 is to detect when the voltage d of the digit line approaches the constant value Vd tree, and by improving the performance of the inverting amplifier 11, the operation of this example is It is not possible to improve the speed. As described above, this example of the prior art is not suitable for a large capacity, high speed FPROM. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-capacity, effective, high-speed storage device that eliminates the above-mentioned drawbacks. A memory device according to the present invention includes at least a plurality of memory elements, an address line, a digit line, and a detection means for detecting a voltage of the digit line that changes depending on the storage contents of the memory element. The memory element is a memory element in which it is determined whether or not a current can be passed through the memory element itself depending on the stored content, and an inverting amplifier that receives the digit line as an input is provided as the detecting means, and the inverting amplifier The input and output of the device are short-circuited through an element having a resistance component at least during the readout period, and at least one element is connected so as to become conductive when the output voltage becomes higher than the input voltage by more than a certain value in the direction of the power supply. An insulated gate field effect transistor is connected between the input and output of the inverting amplifier.
次に本発明による一実施例を第２図、第３図および第４
図を参照して説明する。Next, an embodiment according to the present invention is shown in FIGS. 2, 3, and 4.
This will be explained with reference to the figures.
第２図は本発明による実施例を示す回路図であるが、Ｍ
Ｃと表示した部分は従来技術による記憶回路の回路図第
１図のＭＣと表示した部分と全く同様であるため説明も
省略する。本発明による一実施例の構成は、マトリクス
状に接続された記憶素子としての複数個のＦＡＭＯＳと
アドレス信号に対応して１個のＦＡＭＯＳが選択され、
ディジット線ＤＬと電気的に接続される機能ブロックＭ
Ｃと前記ディジット線ＤＬを入力とする反転増巾器１Ｖ
１前記ディジット線ＤＬと前記反転増巾器１Ｖの出力Ｓ
の間に接続された帰還抵抗ＲＦとソースを前記ディジッ
ト線ＤＬに、ドレインとゲートを共通に前記反転増巾器
の出力Ｓ点の間に接続されたエンハンスメント型の帰還
用ＩＧＦＥＴＱＦとにより構成される。FIG. 2 is a circuit diagram showing an embodiment according to the present invention.
The portion labeled C is exactly the same as the portion labeled MC in FIG. 1, which is a circuit diagram of a memory circuit according to the prior art, so a description thereof will be omitted. The configuration of an embodiment according to the present invention includes a plurality of FAMOSs as memory elements connected in a matrix, and one FAMOS selected in response to an address signal.
Functional block M electrically connected to digit line DL
Inverting amplifier 1V with C and the digit line DL as inputs
1 Output S of the digit line DL and the inverting amplifier 1V
and an enhancement type feedback IGFET QF whose source is connected to the digit line DL and whose drain and gate are commonly connected between the output point S of the inverting amplifier. .
なお図及び説明は１本の出力についてのみ述べるが、出
力の本数と同じ個数の回路が必要であることはもちろん
である。次に本発明による実施例の動作を第２図、第３
図及び第４図を参照して説明する。Note that although the drawings and explanations refer to only one output, it goes without saying that the same number of circuits as the number of outputs are required. Next, the operation of the embodiment according to the present invention is shown in FIGS. 2 and 3.
This will be explained with reference to the figures and FIG.
なお第３図は前記反転増巾器１Ｖの入出力特性の略図、
第４図は第２図、第３図に対応する前記ディジット線Ｄ
Ｌと前記反転増巾器１■の出力点Ｓの電圧波形の略図て
ある。先ず選択されたＦＡＭＯＳ（ＭＣブロック内）が
非導通であり、従つてディジット線ＤＬが充電される場
合について説明する。Note that FIG. 3 is a schematic diagram of the input/output characteristics of the inverting amplifier 1V,
FIG. 4 shows the digit line D corresponding to FIGS. 2 and 3.
The voltage waveforms at the output point S of the inverting amplifier 1 and the inverting amplifier 1 are schematically shown. First, a case will be described in which the selected FAMOS (in the MC block) is non-conductive and therefore the digit line DL is charged.
時間ｔ１でアドレスが変わり充電が開始されたとする。
又ディジット線ＤＬの電圧■Ｄしの時間ちでの値は最悪
条件を考慮してＯ（Ｖ）とする。その時反転増巾器１Ｖ
の出力電圧■は電源ＣＣの電圧■。。又はそれに近い値
となつている（第３図ａ点、第４図Ａ，点に対応）、こ
の場合〔Ｖ，−ＶＯＬ〕が帰還用１ＧＦＥＴＱｐのしき
い値電圧■Ｔｈより充分大きいため、前記帰還用ＩＧＦ
ＥＴＱｐを通して極めて大きな電流がディジット線ＤＬ
に付加される大きな容量を急速に充電すべく流れる。そ
のためディジット線ＤＬの電圧■ＤＬは急速に上昇する
。なお前記帰還用１ＧＦＥＴＱＦを通して流れる電流は
後述する如く放電時の動作にはほとんど関係しないこと
が前述の従来技術による例の場合と異なる。そのため帰
還用ＩＧＦＥＴＱＦの等価抵抗値ＲＴは充電に必要なだ
け小さく設計する事が出来る。ディジット線ＤＬの電圧
■ＤＬが第３図ｂ点に対応する電圧まで上昇すると、第
３図より明らかな如く、反転増巾器の出力電圧■，はデ
ィジット線の電圧■Ｄしの変化の前記反転増巾器の増巾
率−Ａ倍だけ変化する。Assume that the address changes at time t1 and charging starts.
Further, the value of the voltage of the digit line DL at the time D is set to O (V) considering the worst condition. At that time, the inverting amplifier 1V
The output voltage ■ is the voltage ■ of the power supply CC. . or a value close to it (corresponding to point a in Figure 3 and point A in Figure 4). In this case, [V, -VOL] is sufficiently larger than the threshold voltage ■Th of the feedback 1GFET Qp, so the above IGF for return
An extremely large current flows through ETQp to digit line DL.
flows to quickly charge the large capacity added to the Therefore, the voltage DL on the digit line DL rapidly rises. Note that the current flowing through the feedback 1GFET QF has little to do with the operation during discharging, as will be described later, which is different from the prior art example described above. Therefore, the equivalent resistance value RT of the feedback IGFETQF can be designed to be as small as necessary for charging. When the voltage DL on the digit line DL rises to the voltage corresponding to point b in Figure 3, as is clear from Figure 3, the output voltage XX of the inverting amplifier is equal to the change in the voltage DL on the digit line D. The amplification rate of the inverting amplifier changes by -A times.
Ａを３０に設計したとすれば、ディジット線の電圧■。
Ｌが０．１（■変化するのに応じて約３（■変化するこ
とになる。かくして、ディジット線の電圧Ｖ。Ｌが上昇
し、第３図Ｃ点（第４図Ｃ。Ｌ．点、時間Ｔ３）に達す
ると、〔■９−■０Ｌ〕が帰還用１ＧＦＥＴＱｐのしき
い値電圧■Ｔｈと等しくなり帰還用１ＧＦＥＴＱＦは非
導通になる。従つてこれより先ディジット線の容量を充
電する電流は帰還抵抗ＲＦを通してのみ流れることにな
る。帰還抵抗ＲＦは後述する如く、放電時の速度と直接
関係しておりＲｐが大きいほど放電速度が大きい点を考
慮すると、充電速度のみを考えて小さくする事は出来な
い。この点に関しては前述した従来技術による例の負荷
抵抗の場合と同様である。すなわち、前記第３図のＣ点
に対応するディジット線の電圧を■。ＬＯ、反転増巾器
の出力Ｓの電圧を■ＳＣｌ電源電圧を■。。、ディジッ
ト線の電圧ＶＤＬと反転増巾器の出力電圧Ｖ，が等しく
なつた時（第３図ｄ点、第４図Ｄ，、ＤＯＬ点）の電圧
をＶｒとおき、Ｃ点に達した時間を基準にとると、と表
わせ、振巾にほぼ帰還用１ＧＦＥＴＱＦのしきい値電圧
■Ｔｈとなり、時定数は単純なＣＲに比べてほぼ反転増
巾器の増巾率Ａ分の１と極めて小さく、従つて従来技術
による例での（１）式と比較して明らかな如く極めて高
速度てある。以上の如くしてディジット線の充電が完了
すると、ディジット線の電圧と反転増巾器の出力の電圧
が一致した点で平衡する。If A is designed to be 30, the voltage of the digit line ■.
As L changes by 0.1 (■), it will change by about 3 (■).Thus, the voltage V on the digit line increases. , time T3), [■9-■0L] becomes equal to the threshold voltage ■Th of the feedback 1GFETQp, and the feedback 1GFETQF becomes non-conductive.Therefore, the capacitance of the digit line is charged before this point. The current will flow only through the feedback resistor RF.As will be explained later, the feedback resistor RF is directly related to the discharging speed, and considering that the larger Rp is, the faster the discharging speed is. This point is similar to the case of the load resistor in the prior art example described above.In other words, the voltage of the digit line corresponding to point C in FIG. When the voltage of the output S of the amplifier is set to ■ SCl power supply voltage is If we take the voltage at point ) as Vr and take the time when it reaches point C as a reference, then the amplitude is approximately the threshold voltage of the feedback 1GFETQF ■Th, and the time constant is approximately equal to that of a simple CR. The amplification rate of the inverting amplifier is extremely small, 1/A, and therefore the speed is extremely high as compared to equation (1) in the example of the prior art.As described above, the digit line is charged. When this is completed, equilibrium is achieved at the point where the voltage on the digit line and the voltage at the output of the inverting amplifier match.
ノ 次にアドレスが変わり（第４図Ｔ５に対応）導通す
るＦＡＭＯＳが選択されるとＦＡＭＯＳの電流１。Next, when the address changes (corresponding to T5 in FIG. 4) and the FAMOS that conducts is selected, the FAMOS current becomes 1.
Ｎによつてディジット線の容量が放電され、ディジット
線の電圧は低下してゆく。この場合については、の如く
表わせ、振巾はほぼＲＦＸＩＯＮとなり時定
８ＣｄＲＦ数は充電の場合と同様にほぼ了と
なる。The capacitance of the digit line is discharged by N, and the voltage of the digit line decreases. In this case, the amplitude is approximately RFXION and the time is constant.
The number of 8CdRF is almost completed as in the case of charging.
この場合も前（２）式と比較して明らかな如く極めて高
速度である。以上、ディジット線の電圧の初期値が０（
Ｖ）から主として帰還用１ＧＦＥＴＱｐを通して充電さ
れ、さらに帰還用抵抗ＲＦを通して充電され次にＦＡＭ
ＯＳが導通し放電される過程とそれに供つて変化する反
転増巾器の出力電圧について述べたが、そのいづれの過
程においても従来技術による例に比べて著しく高速度に
動作する。In this case as well, the speed is extremely high as is clear compared to the previous equation (2). Above, the initial value of the voltage of the digit line is 0 (
V) is mainly charged through the feedback 1GFET Qp, further charged through the feedback resistor RF, and then FAM
The process in which the OS is turned on and discharged and the output voltage of the inverting amplifier that changes accordingly have been described, and in both processes, the device operates at a significantly higher speed than in the prior art example.
この点をより明確にするため具体的に数値を設定して説
明する。ディジット線の容量Ｃｄ＝１０ピコファラッド
電源電圧ＶＯ。In order to make this point clearer, specific numerical values will be set and explained. Digit line capacitance Cd = 10 picofarad Power supply voltage VO.
＝５（Ｖ）帰還用１ＧＦＥＴＱＦの導通時の等価抵抗Ｒ
ｑ＝２キロ（Ω）帰還用抵抗ＲＥ，＝５０キロ（Ω）
反転増巾器の増巾率Ａ＝３０
と仮定すれば、
帰還用１ＧＦＥＴＱＦを通しての充電時間〉２０−）−
ノ秒帰還用抵抗ＲＦを通しての充電時間′−１７）ノ秒
ＦＡＭＯＳを通しての放電時間〜１７ケノ秒となり、従
来技術による例の場合に比べて１皓〜２７倍も高速であ
ることが判る。= 5 (V) Equivalent resistance R of 1GFETQF for feedback when conducting
Assuming that q = 2 kg (Ω), the feedback resistor RE, = 50 km (Ω), and the amplification rate of the inverting amplifier A = 30, then the charging time through the feedback 1GFET QF〉20-)-
It can be seen that the charging time through the feedback resistor RF'-17) seconds and the discharging time through the FAMOS is ~17 seconds, which is 1 to 27 times faster than the example according to the prior art.
以上詳述したごとく本発明による記憶装置は完全にスタ
ティックに動作するため、タイミング信号等は全く不要
であり、しかも帰還用１ＧＦＥＴの作用により反転増巾
器の最も高感度の点に自動的にバイアスされるため、デ
ィジット線のわずかな電圧変動も検出される。As detailed above, since the storage device according to the present invention operates completely statically, there is no need for any timing signals, and moreover, it is automatically biased to the most sensitive point of the inverting amplifier due to the action of the feedback 1GFET. Therefore, even slight voltage fluctuations on the digit line are detected.
そのため極めて高速度に動作する記憶装置を提供出来る
。なお本発明はスタティック型にして大容量、高速度の
記憶装置に・適しており、さらには記憶素子の導通時の
電流を大きくとれないような記憶装置、例えばＥＰＲＯ
Ｍに好適である。以上の実施例はＥＰＲＯＭを例にとり
説明したが、記憶素子がその導通、非導通によつて動作
するものである限り本発明は有効であり、従つてＥＰＲ
ＯＭに限るものではない。Therefore, it is possible to provide a storage device that operates at extremely high speed. The present invention is suitable for static type large-capacity, high-speed storage devices, and is also suitable for storage devices that cannot draw a large current when the storage element is conductive, such as EPRO.
Suitable for M. Although the above embodiments have been explained using an EPROM as an example, the present invention is effective as long as the memory element operates depending on whether it is conductive or non-conductive.
It is not limited to OM.
又反転増巾器の構成については前述の説明でも省略した
如く特に制限あるものではないし、帰還用抵抗について
は純抵抗である必要もなく、デイプレツシヨン型“ＩＧ
ＦＥＴ等若干の非線型の素子であつてもよいことはもち
ろんである。Furthermore, the configuration of the inverting amplifier is not particularly limited as has been omitted in the above explanation, and the feedback resistor does not need to be a pure resistor, but may be a depletion type "IG".
Of course, it may be a slightly nonlinear element such as a FET.
第１図は従来技術による記憶装置の一部回路図、第２図
は本発明による記憶装置の一実施例を示す回路図、第３
図は反転増巾器１Ｖの入出力特性を示す概略図、第４図
は動作説明に用いる各部の電圧波形の概略図である。
図中）Ｑｌｌ９Ｑｌ２９Ｓｌｌ９Ｓｌ２い″。FIG. 1 is a partial circuit diagram of a storage device according to the prior art, FIG. 2 is a circuit diagram showing an embodiment of the storage device according to the present invention, and FIG.
The figure is a schematic diagram showing the input/output characteristics of the inverting amplifier 1V, and FIG. 4 is a schematic diagram of voltage waveforms at various parts used to explain the operation. In the figure) Qll9Ql29Sll9Sl2''.
Claims (1)
、前記記憶素子の記憶内容に応じて変化する前記ディジ
ット線の電圧を検出するための検出手段とを少なくとも
含む記憶装置において、前記検出手段として前記ディジ
ット線を入力側に接続した反転増幅器を備え、同反転増
幅器の入力と出力が少なくとも読み出し期間は抵抗成分
を持つ素子を介して短絡され、さらに前記入力の電圧に
比べて出力の電圧が電源方向に一定値以上高くなつた時
、導通する如く少なくとも１個の絶縁ゲート型電界効果
トランジスタを前記反転増幅器の入力と出力の間に接続
したことを特徴とする記憶装置。1. In a storage device including at least a plurality of storage elements, an address line, a digit line, and a detection means for detecting a voltage of the digit line that changes depending on the storage content of the storage element, the detection means The digit line is connected to the input side of an inverting amplifier, and the input and output of the inverting amplifier are short-circuited through an element having a resistive component at least during the readout period, and the output voltage is lower than the input voltage. At least one insulated gate field effect transistor is connected between the input and output of the inverting amplifier so as to become conductive when the direction increases above a certain value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55115181A JPS6042553B2 (en) | 1980-08-21 | 1980-08-21 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55115181A JPS6042553B2 (en) | 1980-08-21 | 1980-08-21 | Storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5740795A JPS5740795A (en) | 1982-03-06 |
| JPS6042553B2 true JPS6042553B2 (en) | 1985-09-24 |
Family
ID=14656353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55115181A Expired JPS6042553B2 (en) | 1980-08-21 | 1980-08-21 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042553B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0537450U (en) * | 1991-10-22 | 1993-05-21 | 愛知製鋼株式会社 | Delivery stand of long material end face grinding machine |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60101797A (en) * | 1983-11-07 | 1985-06-05 | Hitachi Ltd | semiconductor memory circuit device |
-
1980
- 1980-08-21 JP JP55115181A patent/JPS6042553B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0537450U (en) * | 1991-10-22 | 1993-05-21 | 愛知製鋼株式会社 | Delivery stand of long material end face grinding machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5740795A (en) | 1982-03-06 |
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