JPS601637B2 - automatic rhythm playing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic rhythm performance device capable of performing break performances.

When using an automatic rhythm performance device built into an electronic organ, etc., in order to change the performance during the performance, a break function is used that performs the performance only when the switch is operated, and stops the performance when the switch operation is interrupted. There are things I would like to perform.

The present invention allows such a break performance to be performed using a start key switch that is turned on only when pressed.If the break switch is turned on during the main performance and the start key switch is turned on and off, The main performance is performed only when it is on, and when it is off, the main performance is immediately interrupted, and the break switch is turned on during the intro performance.
To provide an automatic rhythm performance device in which when the start key switch is operated, an intro break performance is performed once, and thereafter a main performance break performance is performed.

This will be explained below according to the drawings.

In FIG. 1, 1 is a clock pulse generator that generates a clock pulse corresponding to the beat of the smallest rhythm unit;
2 is a frequency divider C, which sequentially divides the frequency of the clock pulse.
C2: A counter circuit composed of . . . 3 is each frequency divider C of the counter circuit 2.
, , C2 . . . The decoder is composed of a group of AND circuits that receive the output signals as input, and generates a step signal of a rhythm pattern. 4 is a rhythm pattern generation circuit which receives as input the rhythm pattern step signal generated by the decoder 3 and the rhythm designation signal selected by the switch group 5 and generates a desired rhythm pattern; 6 is a main performance circuit; A signal prohibition circuit 7 is an intro signal prohibition circuit, and the main performance signal prohibition circuit 6 and the intro signal prohibition circuit 7 are selectively controlled by the output signal of the first flip-flop 8 for controlling the intro performance. Either the signal or the intro signal is supplied to the sound source circuit 9.

FIG. 2 is a circuit diagram of the control section of the automatic rhythm playing device of the present invention, where 10 is a start key switch that turns on only when pressed, and is connected to the set terminal S of a second flip-flop 11 that generates a start signal. ing.

Further, the output terminal Q of the second flip-flop 11 is connected to the start input terminal 13 of the automatic rhythm generation unit 12, which is composed of the counter circuit 2, etc., and is connected to the reset terminal R.
are connected to the stop switch 14, respectively.

Further, one end of the reset terminal R is connected to the start key switch 1 via a break switch 15 and an inverter 16.
The river is connected. 17 is automatic rhythm performance unit 1
2's intro input terminal 18.
It's a switch.

Next, the operation of the present invention will be explained with reference to the time chart of FIG.

When starting the main performance without performing an intro performance, only the start key switch 10 is turned on.

Then, a set signal is applied to the second flip-flop 11, which sets the second flip-flop 11 to generate a start signal, and connects the start input terminal 13 to ul''.
signal, clock pulse generator 1 and frequency divider C, .
Reset the IJ set terminals R and R of C2・・・・・・・・・・・・ from the 1″ signal to the 0″ signal. , and the clock pulse generator 1 and frequency dividers C, , C2...
...... to operate. The clock pulses of the clock pulse generator 1 are passed through frequency dividers C, , C2...
The frequency is divided by ..., decoded into an address signal by the decoder 3, and applied to the rhythm pattern selection circuit 4.
The desired rhythm signal is selected. At this time, the first flip-flop 8 is set, and the output terminal is "1".
Since the HI'' clock pulse from the start input terminal 13 and the HI'' clock pulse from the clock pulse generator 1 pass through the fifth band circuit 26 to the main performance signal inhibition gate circuit 61. Since the rhythm signal is added to the tone generator circuit 9 and the actual performance signal inhibition gate circuit 6 is passed through, the rhythm signal is added to the tone generator circuit 9 and the actual performance is performed. Next, to perform an intro performance prior to the main performance, turn on the intro switch 17 (Fig. 3A), and the signal "1" is added to the intro input terminal 18.
It is applied to the input terminal of the second AND circuit 20 for a short time via the differentiating circuit 19.

On the other hand, at this time, nl is inverted by the second inverter 21.
'' signals are applied to the other input terminals of the second AND circuit 20, these signals pass through the second AND circuit 20 and are applied to the reset terminal R of the first flip-flop 8 (FIG. 3B), The first flip-flop 8 is reset and the output becomes a "0" signal (Fig. 3C). When the start key switch 10 is pressed (turned on) in this state, the second flip-flop
Since the 1" signal is applied to the set input of the flip-flop 11 and the 0" signal is applied to the reset input via the inverter 16, the output of the second flip-flop 11 becomes the l"l1" signal (the Figure 2D).

The output of the second flip-flop 11 is applied to the second inverter 21 from the start input terminal 13 and inverted to a "0" signal, so that the clock pulse generator 1 and the frequency divider C, , C2, . Therefore, the clock pulse signal from the clock pulse generator 1 is transmitted to the frequency divider C, , C2...
..., and the frequency-divided signal is decoded into an address signal by a decoder 3 and sent to a rhythm pattern selection circuit 4, where a desired rhythm signal is selected.
By the way, as mentioned above, since the output terminal of the first flip-flop 8 is a 0" signal and the start input terminal 13 is a 1" signal, the clock pulse from the clock pulse generator 1 is a "1" signal. Then, the fourth AND circuit 22 is turned on, and a -1'' signal is applied to the intro signal prohibition circuit 7, which activates the intro signal prohibition circuit 7, passes the intro signal, activates the sound source circuit 9, and performs the intro signal. play.

Next, when the output of the frequency divider Cn changes from the 1'' signal to the 0'' signal (FIG. 3E), it passes through the first inverter 23, the first differentiating circuit 24, and the OR circuit 25 to the first flip-flop. A set signal is applied to the set terminal S of the flip-flop 8, and the first flip-flop 8 is set to the output terminal Q.
, 1″ signal.

Then, this time, the 1'' signal is applied only to the actual performance signal inhibition circuit 6 via the fifth AND circuit 26, the actual performance signal inhibition circuit 6 is activated, the actual performance signal is passed through, and is added to the sound source circuit 9. During the main performance, the break switch 15 is turned on and the start key switch 10 is turned on to perform a break performance.

That is, when the break switch 15 is turned on, the second flip
A 1'' signal is applied to the reset terminal R of the flop 11, making the output terminal of the second flip-flop 11 a 0'' signal. Therefore, I of clock pulse generator 1 and frequency divider C, , C2...
A reset signal is applied to the J set terminal, and the clock pulse generator 1 and frequency dividers C, C2...
...stops the operation and interrupts the performance. When the start key switch 10 is turned on again, the second flip-flop 11 is set and its output terminal becomes the toe 11'' signal.

The 1'' signal is also applied to the second inverter 21 from the start input terminal 13 and inverted as described above.Therefore, the clock pulse generator 1 and the frequency dividers C, C2, . . .
・・・・・・・・・・・・Glue set terminal R, R・・
Since the YES0'' signal is applied to the clock pulse generator 1 and the frequency divider C,
, C2..., the reset is released and the operation resumes. At this time, even if the intro switch 17 continues to be on, the reset signal will not be applied to the reset terminal R of the first flip-flop 8 due to the presence of the second differentiating circuit 19, so the first flip-flop 8 will not be set. Retain state. Therefore, the actual performance signal prohibition circuit 6 remains in the passing state, so that the actual performance is performed. When the pressing force of the start key switch 10 is released, the second flip-flop is activated via the inverter 6 and the break switch 15 in the same manner as described above. A reset signal is applied to the reset terminal R of the second flip-flop 11, thereby resetting the second flip-flop 11 and interrupting the main performance.

By repeating this operation, the signal shown in FIG. 3 is eventually supplied to the sound source circuit, and a percussion instrument sound such as a bass drum sound is generated. By the way, if the break operation is performed by turning on the break switch 15 together with the intro switch 17 before the main performance, the intro break performance will be performed at the first on/off of the start key switch 10, but the subsequent start key switch 10 When turning on and off, a break performance of the main performance is performed as described above. In other words, the intro switch 17
is turned on, the first flip-flop 8 is reset, and when the start key switch 10 is turned on in the intro performance state, the clock pulse generator 1 and the frequency divider C,
, C2...... are operated to perform an intro performance.

Next, when the pressing force on the start key switch 10 is released and turned off, the second flip-flop 11 is reset, and the clock pulse generator 1 and frequency dividers C, C2...
Stops the operation of ・・・・・・ and interrupts the intro performance. At the same time, when the start input terminal 13 changes from the 1'' signal to the 0'' signal, the output of the second inverter 21 changes from the 0'' signal to the 1'' signal, so that signal is sent to the third differentiator circuit. 27 and the OR circuit 25, a set signal is applied to the set terminal S of the first flip-flop 8, and the first flip-flop 8 is set. Therefore, the intro prohibition circuit 7 is cut off, and the main performance signal is prohibited. The circuit 6 is brought into a passing state. Therefore, when the start key switch 10 is turned on next time, the main performance is performed, and when the start key switch 10 is turned off, the main performance is interrupted. If the set signal is not applied to the first flip-flop 8 via the third differentiating circuit 27 when the start input terminal 13 changes from the 1'' signal to the 0'' signal as described above, Break performance is usually short and the frequency divider Cn is 0.
``Because the break occurs before it becomes a bond, the first flip-flop 8 is not set and only the intro performance continues forever.

As described above, in the automatic rhythm performance device of the present invention, if the break switch is turned on during the main performance, and the start key switch is turned on and then turned off, the automatic rhythm performance device performs the break performance of the main performance, and performs the break performance during the intro performance. If you perform the above operations, 1
Since it is possible to play the intro break only in the first performance, and then play the main performance break from the next time onwards, it is possible to perform the break performance with excellent operability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an automatic rhythm performance device of the present invention, FIG. 2 is a control circuit diagram of the automatic rhythm performance device for explaining the circuit of the present invention, and FIG. 3 is a time chart of output signals of each part. 1... Clock pulse generator, 2...
・Counter circuit, 3...Decoder, C,,C2...
... Frequency divider, 4 ... Rhythm pattern generation circuit, 6 ... Main performance signal prohibition circuit, 7 ... Intro signal prohibition circuit, 8 ... Intro control circuit. First flip-flop, 9... Sound source circuit, 10...
...Start key switch, 11...Second flip-flop for performance control, 15...Break switch,
17...Intro switch. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 A clock pulse generation circuit that generates a clock pulse corresponding to the beat of the smallest rhythm unit;
A counter circuit having a frequency divider that sequentially divides pulses, a decoder that receives the output signals of each stage of the counter circuit as input signals, and a rhythm signal decoded by the decoder.
A rhythm pattern generation circuit that receives a step signal and a rhythm designation signal as input and generates a predetermined rhythm pattern signal, and a main performance signal prohibition that passes or blocks the rhythm pattern signal for the main performance among the rhythm pattern signals. an intro signal prohibition circuit for passing or blocking an intro rhythm pattern signal among the rhythm pattern signals, a sound source circuit driven by the passed rhythm pattern signal, and the clock pulse generation circuit. a memory circuit that generates a start signal to start the operation of the circuit and the counter circuit; and a memory circuit that is forward-rotated by the signal from the memory circuit to pass through the main performance signal prohibition circuit, and is inverted by the signal from the intro switch and is an intro-signal prohibition circuit. a memory circuit that puts the memory circuit into a passing state, a start key switch that rotates the memory circuit in the normal direction, a break switch that is connected to the start key switch via an inverter and applies a reset signal to the memory circuit, and a frequency divider for the counter circuit. An automatic rhythm playing device comprising a differentiating circuit which applies an output signal of the above to a set terminal of the memory circuit.