JPS601707B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an external input signal to a storage device such as a random access memory, and relates to means for increasing the packaging density of the storage device.

Dynamic random access memory (RAM)
is the central processing unit (CPU) in a computer system.
It is in high demand as internal memory.

The storage capacity of this RAM is about 22 bits.
It is housed in a pin package. The storage capacity of this RAM is expected to increase with the development of IC technology,
An increase in storage capacity leads to an increase in the number of row addresses and column addresses of memory cells, which in turn leads to an increase in the number of pins of a package. For this reason, there has been a problem that the package becomes larger and the packaging density decreases. Therefore, conventional methods for increasing the packaging density of RAM include inputting the row address signal and column address signal of the memory cell chronologically from the same pin, and replacing chip selection signals (CS, CE, etc.) with row address strobe signals ( RAS) and column address strobe signal (CAS).

By such means, a RAM with a storage capacity of 1 bit and housed in a 16-pin package was developed. However, it is still insufficient in terms of packaging density, and it is desired that a RAM with even higher packaging density will appear. The present invention was made in consideration of these circumstances, and its purpose is to increase the storage capacity, reduce the number of input/output pins, and provide a storage device with increased packaging density. It is about providing.

The details of the present invention will be explained below with reference to the drawings.

Figure 1 is a schematic diagram of the RAM configuration, and 1 in the figure indicates address signals input from each terminal, RAS, CAS, CS, (CE).
This is a signal input section that serves as a buffer that receives signals. The internal signal generator 2 is controlled by the signal input to the signal input section 1.
is activated and provides a predetermined control signal to the input signal detection circuit 3. This input signal detection circuit 3 has two MOBs, for example.
It is composed of a flip-flop or the like in which the drains and gates of transistors are interconnected, and a row address signal and a column address signal are obtained from the input address signal. These row and column address signals are transmitted to a memory cell array 4 in which memory cells are arranged in a matrix.
and select memory cells. Data is written into or read from the selected memory cell by means not shown. Conventionally, RA with this kind of configuration
In M, if the address signal is a column address signal, R
A RAS signal as shown in FIG. 2a was input to the AS signal input terminal, indicating that the address signal was a column address signal.

When the address signal is a row address signal, a CAS signal as shown in FIG. 2b is input to the CAS signal input terminal, indicating that the address signal is a row address signal. And these RAS and CAS signals are usually
It was a TTL level signal. The first embodiment of the present invention is a ternary level CE signal which is a combination of a RAS signal and a CAS signal.
After creating a (chip-ine-*pull) signal and inputting this CE signal from one terminal, the RAS
The signal is separated into two systems of binary logic, a signal and a CAS signal, and is operated in the same way as the conventional one.

That is, the CE signal has the MOS level and T as shown in FIG. 2c.
"MOS shown in d and e of the same figure"
It includes a level RAS signal and a TTL level CAS signal. Such a CE signal is in the HIGH level state of a three-valued bell during normal stand/up mode. When this CE signal falls to an intermediate level, that is, becomes a HIGH level of the TTL level, the internal signal generation circuit 2
detects that the RAS signal is input. The column address of the memory 4 is specified by detecting this RAS signal. Next, C
When the E signal has three levels and reaches the LOW level of the bell, the internal signal generating circuit 2 detects that the CAS signal has been input. The row address of the memory 4 is specified by detecting this CAS signal. In other words, conventional RA
It exhibits the same function as the S signal and CAS signal. According to this storage device, the number of signal input terminals can be reduced from two pins for RAS signals and CAS signals to only one pin for CE signals.

Therefore, if the one pin reduced above is used for addressing as shown in the following table, the storage capacity can be increased.

That is, as shown in this table, the conventional device uses 7 of Ao, A, . . . A6 for rows and columns as address signals.
Can take a bit value.

Therefore, the storage capacity was 27×27, ie, 16 total 4 bits. However, in this device, it is possible to set the length to 65536 bits. When a 16-pin package is used in this way, the storage capacity can be greatly increased from the conventional one bit to six bits. Incidentally, inputting and operating such a CE signal can be easily performed by slightly modifying a conventional device.

FIG. 3 shows a specific circuit diagram of the internal signal generating circuit 2. As shown in FIG. In the figure, 31 to 35 indicate MOS transistors, and symbols A, B, and C indicate each node.

Conventionally, when a HIGH level signal of the RAS signal is input to such a circuit 2, both transistors 32 and 33 are turned on, but by setting a difference in conductance between the transistors 32 and 33 in advance, the node B does not exceed the threshold voltage of transistor 34. This can be achieved by making the channel width of transistor 33 sufficiently larger than the channel width of transistor 32. Here, when the RAS signal becomes LOW level, the transistor 33 is turned off. By this OFF operation of the transistor 33, a bootstrap is applied to the node A, and the potential of the node B is approximately the power supply voltage V.
It becomes DD. Therefore, the transistor 34 is turned on and the signal ◇ is output from the node C. Now, if we consider replacing the RAS signal with the CE signal of the present invention, this can be achieved by adjusting the conductance ratio of transistors 32 and 33 and the conductance ratio of transistors 34 and 35.

That is, when the CE signal is at HIGH level, node B,
When C is at a LOW level and the CE signal is at an intermediate level, nodes B and C are set at a HIGH level.
In this case, it is effective to implant impurities into the channels of the transistors 33 and 35 to increase the threshold voltage. That is, by using the circuit shown in FIG. 3 whose threshold value is set to three values and set between the HIGH level and the intermediate level of the CE signal of the bell, the RAS signal can be obtained from the CE signal. It is also connected in parallel with this circuit, and has basically the same configuration as in Figure 3.
If a value is set between the intermediate level and the LOW level of the CE signal, the CAS signal can be extracted from the CE signal. In this manner, the storage device of the present invention can be formed from a conventional device using relatively simple means. Next, a second embodiment of the present invention will be described. In this embodiment, the RAS signal and the CAS signal are shared with part of the address signal.
It is a bell signal. That is, the conventional RAS signal and CAS signal are input from independent terminals, as shown in FIGS. 4a and 4b, respectively. And the above RAS
Based on the signal and the CAS signal, an address signal is input as shown in FIG. Note that the shaded area in FIG. 4c indicates don't care. Therefore, in this embodiment, TTL
The input device for the address signal expressed in level is inputted as a three-level bell signal which is an integrated form of the RAS signal and CAS signal expressed in MOS level. Shown in d and e. R like this
According to the AS signal, when the signal that was at HIGH level during standby becomes an intermediate level, a TTL level address signal is read.

In addition, the CAS signal is HIGH during standby.
When the signal that was at the level becomes an intermediate level, the address signal is read in the same way as in the case of the RAS signal described above. Reading of address signals that operate in this manner will be explained using the address buffer shown in FIG. 5 as follows. In the figure, 51 to 69 indicate MOS transistors, J,,◇2,? 3 and x4 are internal signals that control column addresses, and 5, 06, J7, and J8 are internal signals that control row addresses. That is, transistor 5
When the RAS signal input to gate 1 changes from HIGH level to intermediate level or LOW level, the output Ad
Contradictory signals are output from and Ad. In other words, the signals ○, ? as shown in FIG. 6 supplied from the internal signal generating circuit 2 2, 03, 04 (○5, ?6, 07, J8), the transistors 51 to 69 are activated one after another. The transistor 51 is turned ON when the RAS signal is at an intermediate level or higher, and turned OFF when the RAS signal is at a LOW level.
Address signal Ad by ON or OFF operation of 1
and Ad are output. Of course, this operation is similar in the case of a CAS signal as well. Note that the transistor 51
The threshold level can be set in the same manner as in the first embodiment described above. As described above, according to the book barrel, the RAS signal can be input from the address signal input terminal, and the CAS signal can also be input from the address signal input terminal.

Therefore, the purpose of the signal input terminal can be set as shown in the table below. Therefore, the storage capacity can be greatly increased from 27×27 bits to 64K bits, that is, from 1 bit to 64K bits as described above. As described above, according to the means of the present invention, the number of input terminals of the storage device can be reduced as explained using the first and second embodiments, and the removed terminals can be used to input address signals. It can be increased by 1 bit. Therefore, a storage device with a large capacity of 6 bits in a 16-pin package can be realized, and the packaging density can be significantly improved.
Therefore, when used as an internal memory of a CPU, it can be used extremely well to expand its functions. Note that the present invention is not limited to the above embodiments, and can be implemented with various modifications.

For example, not only 16-pin RAM but also 22-pin RA
It goes without saying that the present invention can be similarly applied to M, and the form of the input signal does not matter whether it is positive logic or negative logic. Furthermore, various circuit configurations can be applied to the internal signal generation circuit 2 and the address buffer. Furthermore, in addition to adjusting the conductance of the threshold levels of the MOS level and the TTL level by implanting impurities as explained above, the signal level can also be suppressed to 4.0 V depending on the specifications, for example, the HIGH level of the TTL level. good.

[Brief explanation of drawings]

Fig. 1 is a schematic configuration diagram of a RAM, Fig. 2 is a signal waveform diagram for explaining one embodiment of the present invention, Fig. 3 is a circuit diagram of an internal signal generation circuit, and Fig. 4 is a diagram of another embodiment of the present invention. FIG. 5 is a circuit diagram of the address buffer, and FIG. 6 is an internal signal waveform diagram for controlling the operation of the address buffer shown in FIG. 5. 1...Signal input section, 2...Internal signal generation circuit,
3...Input signal sensing circuit, 4...Memory,
31-35, 51-69...MOS transistors. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. A memory device formed of one chip that selects memory cells arranged in a matrix by specifying a row address and a column address, and controls input/output of signals of the selected memory cells. A storage device characterized in that it has means for converting at least a part of the input signal from outside the chip into a ternary level signal, and separating this ternary level signal into two systems of binary logic signals inside the chip. . 2. The storage device according to claim 1, wherein the ternary level signal is a chip selection signal including two signal components: a row address strobe signal and a column address strobe signal. 3. The three-level signal is a signal including two systems of signals, a row address strobe signal and a part of a row address signal, and a signal including two systems of signals, a column address strobe signal and a part of a column address signal. A storage device according to claim 1.