JPS601791B2 - solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the characteristics of a solid-state imaging device including a delay circuit using a charge transfer element as a delay line.

Solid-state image sensors have recently attracted attention as image sensors that convert optical images of objects into television signals.

Color cameras using this solid-state image sensor are roughly divided into three types depending on the number of solid-state image sensors used: a single-chip color camera, a two-chip color camera, and a three-chip color camera. Since sensitivity, resolution, S/N, and stability are the main performance factors to be evaluated, a large number of various cameras have been proposed that can better achieve these performances. Among these, there is a color camera that uses an output signal from a solid-state image pickup device and a signal delayed by one horizontal scanning period (hereinafter referred to as IH) from a conventional signal to separate and combine color signals.

An example of this color camera is shown in FIG. 1, and a mosaic color filter used in this color camera is shown in FIG. In Fig. 2, the symbol G is the green filter 13 that transmits green light, the symbol R is the red filter 14 that transmits red light, and the symbol B is the filter 14 that transmits blue light. This is a blue filter 15. In one row (referred to as the N-th row), G and R are arranged alternately for each pixel, and the row before the N-th row (row N-1) and the row after the N-th row (row
In the N11th row), G and B are arranged alternately for each pixel. Moreover, when focusing only on G, the G on the Nth row is arranged between the G on the N-1th row and the G on the N+1th row, that is, in a checkered pattern. In this way, in a mosaic color filter, filters for colored light that requires high resolution, for example, green, are generally arranged in a checkered pattern. (For example, JP-A-51-1
12228 Tokusei Sho 53-71522) The color solid-state image sensor 1 shown in FIG. 1 is a solid-state image sensor equipped with a mosaic color filter shown in FIG. and is supplied to the IH delay circuit 3. The IH delay circuit 3 is a delay circuit using a charge transfer element.
The shape of this output signal (hereinafter referred to as the IH delayed signal) is PAM (P mountain se Amplitude Mo) in the same way as the original signal.
d-mountation) signal.

This IH delay signal is supplied to a clamp circuit 4 for DC regeneration, and then supplied to a gate circuit 6, a switch circuit 8, and a switch circuit 9. On the other hand, the original signal DC-regenerated by the clamp circuit 2 is supplied to a gate circuit 5, a switch circuit 8, and a switch circuit 9. The gate circuit 5 gates only the G signal from the original signal, and the gate circuit 6 gates only the G signal from the IH delay signal.
The signals are mixed in a mixing circuit 7 to produce a G signal. On the other hand B
As can be seen from the configuration of the mosaic color filter 12 shown in FIG. 2, signals can only be obtained from the color solid-state image sensor 1 every other row, so the rows without the B signal are IH delayed signals obtained by delaying the original signal by IH. I'm getting it from That is, the switch circuit 8 operates to switch between the original signal and the IH delayed signal for each IH, and the output of the switch circuit 8 is sent to the sample and hold circuit 1.
A continuous B signal is obtained by sampling and holding only the B signal. Since the R signal is synthesized in the same manner as the B signal, the explanation will be omitted. When separating and combining color signals from the color solid-state image sensor 1 with such a configuration, the most important thing to be careful about is that the black level obtained when the light incident on the color group image sensor 1 is blocked is clamped. Original signal obtained from the output of circuit 2 and clamp circuit 4
This means that it must match the IH delay signal obtained in . If a black level mismatch occurs between these signals for some reason, the mixing circuit 7
The G signal obtained from the sample and hold circuit 10 generates synchronous noise with a frequency that is half the horizontal transfer frequency of the color solid-state image sensor 1, and the B signal obtained from the sample and hold circuit 10 and the signal obtained from the sample and hold circuit In the R signal, synchronized noise having a frequency of 1/2 of the horizontal scanning frequency is generated, which significantly deteriorates the image quality of the color television signal synthesized from these color signals. The causes of variations in the black level of the original signal and the IH delay signal include variations due to the temperature of the DC voltage of the clamp circuits 2 and 4, and variations due to the temperature of the current in the charge transfer element used in the IH delay circuit 3. Examples include fluctuations and fluctuations in signal input timing due to temperature fluctuations at the signal input section of the charge transfer element.

The generation of synchronous noise due to temperature fluctuations in the DC voltage in the clamp circuit is not caused by the temperature fluctuation value of the DC voltage of clamp circuit 2 or clamp circuit 4 alone becoming the synchronous noise level, but by the DC voltage caused by these clamp circuits. The difference in voltage temperature fluctuation values becomes the level of synchronous noise. Therefore, the parts constituting the clamp circuits 2 and 4, especially semiconductor parts that are easily affected by temperature, should be made with uniform temperature characteristics, and when mounted on a printed board, these parts should be used as much as possible. By arranging them close to each other, the synchronization noise level can be reduced to a level that poses no problem in practice. However, since the temperature fluctuation of the black level due to the IH delay line itself becomes a synchronous noise level, it is necessary to suppress it to a level as low as possible.

The value of the floor current generated in a charge transfer device at room temperature varies depending on the conditions for manufacturing the charge transfer device and the driving frequency, but it ranges from several mV to several tens of hV. The rate of change in this floor current with respect to temperature increases approximately twice as much as the temperature increases by 1020 degrees. Therefore, for example, if there is a floor current of 1 skin V at room temperature, a rise in temperature of 1000 degrees will result in a floor current of 2 skin V, and the above-mentioned synchronous noise will increase by 10 hV. This is because if the standard signal level of the original signal is 20V, the S/N of synchronous noise will be 2, and the allowable limit of S/N of synchronous noise is generally said to be 4MB. This value is quite bad and poses a practical problem. Furthermore, since the material of the charge transfer element is a semiconductor in the signal input section of the charge transfer element, the input characteristics may change depending on the temperature. In this way, the PAM signal from the solid-state image sensor,
A PAM that delays this signal by IH using a charge transfer element.
When calculating the signal as a PAM signal, temperature fluctuations in the black level of the charge transfer element used as the IH delay line generate synchronous noise, which is a major cause of deterioration of the image quality of the television signal. It had become.

An object of the present invention is to provide a solid-state imaging device that improves these drawbacks, and its operating principle will be explained in detail.

Up to now, methods for inputting signals to charge transfer devices include dynamic current injection method, diode cutoff method,
A potential balancing method is known.

(For example, C.R.SEQU state ANDM.F.TOMP
Written by SETT CHARGE TRANSFER DEVEI
CES P48-P52) FIG. 3 is a diagram for explaining these signal input methods. Figure 3A shows what is called the dynamic current injection method, in which a constant voltage is applied to the gate electrode IG, and a signal is applied to the input diode.Of course, a signal is applied to the gate electrode IG, and a constant voltage is input. A diode may also be applied.

In either case, the amount of signal charge input to the charge transfer element is determined by the voltage difference between the input diode m and the gate electrode IG. Figure 3B shows what is called the diode cutoff method or voltage input method, in which this signal is applied to the input diode, a pulse is applied to the gate electrode, and the pulse is used to connect the input diode m and the transfer electrode 2. In this method, a signal charge corresponding to the potential difference between the input diode ID and the transfer voltage Z is injected into the charge transfer element by opening and closing. FIG. 3C shows the so-called charge balance method or charge preset method, in which a pulse is applied to the input diode ID, a constant voltage is applied to the first gate electrode GI, and the second gate electrode G2 1
A signal is applied to the input diode I, and a signal charge corresponding to the potential difference between the first gate electrode GI and the second gate electrode G2 is applied to the input diode I.
In this method, charge is injected from the input diode ID into the charge transfer element using a pulse applied to D. Therefore, for example, in this potential balance method, if the signal to be applied to the second gate electrode G2 is applied to the second gate electrode G2 via the clamp circuit, the DC voltage applied by the clamp circuit when there is no signal is A constant electric tree (hereinafter referred to as bias charge) corresponding to the potential difference between the constant voltage applied to the first gate electrode GI and the constant voltage applied to the first gate electrode GI is input to the charge transfer element. This amount of bias charge can be freely changed by changing the DC voltage applied by the clamp circuit or the constant voltage applied to the first gate electrode GI. Therefore, the amount of charge corresponding to the floor current that changes due to temperature within the charge 3 transfer element can be canceled out by the bias charge described above. This will be explained in more detail with reference to FIG. Figure 4 shows the input/output characteristics when a signal is input to the charge transfer element using the potential balance method.
), and the vertical axis is the amplitude of the output signal. Curve A is a characteristic curve at room temperature, and curve B is a characteristic curve at a certain temperature TH higher than room temperature.
It has moved upward in parallel by an amount corresponding to o). Here V. o is the voltage level corresponding to the floor current at room temperature,
V. , is the voltage level corresponding to the clear current at the temperature TH. If (G2-GI) is now set to VG at room temperature, the output level at that time will be Vo. This Vo is the V for the floor current. It is the sum of o and the bias charge. That is, the bias charge is injected in an amount corresponding to (Vo-V.o). If the temperature reaches TH in this state, the input/output characteristics will be curve B, so the output level will be V. That is, the floor current increases by (V., -V.o) due to the rise in temperature, which causes the output level to increase by (V, -Vo). In order to reduce this increase, (G2-GI) is decreased, and VG in Figure 3 is
, the output level of curve B is the same as the output level at room temperature, V'
It is possible to obtain the same output level at all times by canceling out the fluctuations in floor current due to temperature changes. In addition, in order to detect the floor current generated in the charge transfer device, the output signal of the solid-state image sensor that is input to the charge transfer device must be detected at a portion that does not include the video information signal. It is necessary to gate the output signal of the charge transfer device corresponding to the portion that hardly contains .

Such a signal is present during the blanking period. That is, when driving the solid-state image sensor, the horizontal transfer register is always operated outside the horizontal transfer register, and the vertical transfer register stops operating for a predetermined period of the vertical blanking period, and a signal is sent from the vertical transfer register to the horizontal transfer register. If you make sure that this is not the case, the signal output from the solid-state image sensor during this period will not contain any video information.
The signal contains almost no emotional current. Furthermore, in a reel image sensor in which the number of elements in the horizontal transfer register is greater than the number of elements in the corresponding vertical transfer register row, the signals obtained from the elements of the horizontal transfer register in the portion that do not correspond to the vertical transfer register row contain video information. The signal contains almost no ground current. This signal normally determines the frequency of the horizontal transfer register clock pulses as present during the horizontal line erase period. Therefore, the floor current generated in the charge transfer element does not include the video information that exists during a predetermined period of the blanking period of the output signal of the solid-state image sensor, and the output of the charge transfer element corresponds to a portion that does not include almost any floor current. By gating and integrating the signal, the fat current can be detected as a DC voltage. At this time, when detecting during the vertical blanking period (or horizontal blanking period), the detection repetition period is every vertical scanning period (or one horizontal scanning period), so the time constant when integrating is detected. It is necessary to make it sufficiently larger than the repetition period of . As explained above, a portion of the signal within the blanking period of the output signal of the charge transfer element is gated to detect the dark current generated within the charge transfer element and convert it into a DC voltage according to its level. By applying the input signal to the first gate electrode G2 or applying it to the second gate electrode G2 via a clamp circuit for clamping the input signal, it is possible to automatically compensate for changes in the floor current.

The above explanation has been about temperature compensation of the current in the case of signal input using the potential balance method, but as is clear from the explanation of the signal input method in Figure 3, the same applies to the dynamic current injection method and the diode cutoff method. It is possible to compensate for the B sound current, and also to compensate for not only the temperature compensation for the fat current but also the change in the amount of bias charge caused by a temperature change in the signal input characteristics for injecting the bias charge.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing embodiments.

FIG. 5 is a diagram showing one embodiment of the present invention, showing only the color separation part of a color solid-state imaging device using one solid-state imaging device, and omitting the signal processing circuit and color encoder circuit. be. The output signal of the color solid-state image sensor 16 (
The original signal (hereinafter referred to as the original signal) is supplied to an intensifier 17 and a delay circuit 21 for delaying the original signal by a small amount of time. This delay circuit 21 is used to input transfer pulses (not shown) applied to the charge transfer element 23 and sampling pulses (charge transfer element 23 An inverting amplifier is also included to invert the polarity of the source signal. The output signal of the delay circuit 21 is supplied to a clamp circuit 22, clamped to the DC voltage output from the multiplier 31, and supplied to the second gate electrode through the terminal 43 of the charge transfer element 23. A constant DC voltage is applied to the first gate electrode from the reference voltage generation circuit 33 through the terminal 42, and a sampling pulse is applied to the input diode through the terminal 41. The method of inputting such a signal at the input section of the charge transfer element 23 is the input method using the above-mentioned potential balance method, and the amount of bias charge is determined by cutting off the light incident on the color solid-state image sensor 16 and inputting the signal to the reference voltage generation circuit 32. It can be set arbitrarily by varying the DC voltage. The purpose of injecting this bias charge is that good signal linearity cannot be obtained in areas where the input voltage is small, that is, areas where the amount of input charge is small, as can be seen from the input/output characteristics obtained by the potential balance method as shown in Figure 4. This is to set the operating point at a portion where good linearity can be obtained, and to cancel out changes in floor current caused by temperature changes and changes in signal input characteristics at the input section, as described above. The original signal is obtained at the terminal 44 of the charge transfer element 23, and the IH delayed signal obtained by IH delay is obtained. A reference level that does not change even with changes in ambient conditions such as the above is clamped to the reference voltage from the reference voltage generation circuit 32 for providing bias charge and is supplied to the gate circuit 29. In the gate circuit 29, the terminal 45
gate a signal corresponding to the floor current and bias charge generated in the charge transfer element included in the IH delay signal by a gate pulse (present only during the vertical blanking period or horizontal blanking period) supplied to the IH delay signal; This gated signal is converted into a direct current voltage corresponding to this signal in an integration and holding circuit 30 and held, inverted and multiplied by an intensifier 31 and supplied to a clamp circuit 22 . Therefore, if the current included in the output signal of the charge transfer element 23 increases (or decreases; the same applies hereinafter) due to temperature, the output DC voltage of the integrating and holding circuit 30 increases (decreases), and this voltage 31 and applied to the second gate electrode from the terminal 43 via the clamp circuit 22, in order to reduce (increase) the potential difference between the first gate electrode and the second gate electrode, that is, the amount of bias charge injection. The output signal decreases (increases) and the change in floor current can be canceled out. That is, when light incident on the color solid-state image sensor 16 is blocked, the signal level (black level) of the black portion from the reference level of the IH delay signal can always be kept constant.

The IH delay signal thus compensated is supplied to a clamp circuit 26 through an intensifier 25. On the other hand, intensifier 1
The original signal amplified in step 7 is supplied to a clamp circuit 18. The clamp circuit 18 applies a certain DC voltage to the original signal, and the clamp circuit 26 applies a certain DC voltage to the IH delay signal, so that the clamp circuit 18 or the clamp circuit 26 Adjust the clamp voltage. The green signal, green signal, and red signal are separated from the original signal and IH delayed signal adjusted in this way, and the method of separation is the same as that described in FIG. 1, so a description thereof will be omitted.

FIG. 6 is a diagram showing another embodiment of the present invention, and the difference from the embodiment explained in FIG. 5 is that the method of generating the control voltage to be supplied to the clamp circuit 22 is different. Components that are the same as those in FIG. 5 are indicated by the same symbols.

That is, the IH delay signal obtained at the terminal 44 of the charge transfer element 23 is supplied to the gate circuit 47 through the buffer multiplier 24. At this time, the buffer multiplier 24 is a direct-coupled multiplier, and the terminal 4
The DC component of the IH delay signal obtained in step 4 is also transmitted as is. However, if this DC component changes due to fluctuations in ambient temperature, it is necessary to supply it to the gate circuit 47 via the clamp circuit 46. Gate circuit 47
In this case, the IH
The dark current signal of the charge transfer element 23 included in the delayed signal is gated, and this gated signal is sent to the integration and holding circuit 48.
The voltage is converted into a DC voltage corresponding to the clear current, held, and supplied to one input terminal of the differential multiplier 49. Another input terminal of the differential multiplier 49 is supplied with a reference DC voltage from a reference voltage generation circuit 50 for setting the amount of bias charge. The difference signal between these two input signals is amplified and supplied to the clamp circuit 22. Therefore, if the current included in the output signal of the charge transfer element 23 changes due to temperature fluctuation, the DC voltage of the output of the differential multiplier 49 changes in accordance with this change, is applied to the second gate electrode of the charge transfer element 23,
It operates to cancel out the change in floor current. The parts other than the part that generates the control voltage are the same as the first embodiment, so the explanation will be omitted. As described above, according to the present invention, there is no output bell fluctuation caused by temperature fluctuations of the charge transfer element used as a delay line, and a stable output signal is always obtained, resulting in good image quality with reduced synchronous noise. A solid-state imaging device can be realized. Note that the charge transfer device that can be used in the present invention may be formed on the same chip as the two-dimensional solid-state image sensor, or may be formed on a separate chip.

Further, it is clear that the gate circuit and the integration and holding circuit may be a sample and hold circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a color solid-state imaging device for explaining the conventional technology, and FIG. 2 is a block diagram of an example of a color solid-state imaging device. 3A to 3C are diagrams for explaining the signal input method of the mist transfer element, Figure 4 is a diagram showing the input/output characteristics of the charge transfer element, and Figure 5 is a diagram of the solid state according to the present invention. A block diagram of the first embodiment of the imaging device, and FIG. 6 is a block diagram of the second embodiment. 1. ．． ．． ．． ．． ．． Color solid-state image sensor, 2, 4... Clap circuit, 3... IH delay circuit, 5, 6...
...gate circuit, 7...mixing circuit, 8,9...switch circuit, 10,11...sample hold circuit, 12...
...Mosaic filter, 13...Green filter, 14...Red filter, 15...
...Blue filter, 16...Color solid-state image sensor, 17,25...Intensifier, 18,26...
・Clamp circuit, 19, 27... Gate circuit, 20...
Mixing circuit, 21...delay circuit, 22...clamp circuit, 23...charge transfer element, 24...
Equilibrium multiplier, 28...clamp circuit, 29...gate circuit, 30...integration and holding circuit, 31...
Multiplier, 32, 33...Reference voltage generation circuit, 34,
36... Switch circuit, 35, 37... Sample hold circuit, 38, 39, 40, 41, 42,
43, 44, 45... terminal, 46...
Clamp circuit, 47... Gate circuit, 48...
... Integral and holding circuit, 49... Differential multiplier,
50...Reference voltage generation circuit, 51...
terminal. 2 figures, 3 figures, 4 figures, 5 figures, 6 figures

Claims (1)

[Claims] 1. In a solid-state video device that synthesizes a video signal from a video signal obtained from a two-dimensional solid-state image sensor and a delay signal from a delay circuit including a charge transfer element that delays this signal by one horizontal scanning period, The method further includes means for gating a part of the blanking period, converting the gated signal into a DC voltage, and supplying the converted DC voltage to the charge transfer element via a clamp circuit. Characteristic solid-state imaging device.