JPS6018944B2 - Pulse detection circuit - Google Patents
Pulse detection circuitInfo
- Publication number
- JPS6018944B2 JPS6018944B2 JP11862380A JP11862380A JPS6018944B2 JP S6018944 B2 JPS6018944 B2 JP S6018944B2 JP 11862380 A JP11862380 A JP 11862380A JP 11862380 A JP11862380 A JP 11862380A JP S6018944 B2 JPS6018944 B2 JP S6018944B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- output
- amplifier circuit
- logarithmic amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 title description 15
- 238000010586 diagram Methods 0.000 description 9
- 238000005259 measurement Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
【発明の詳細な説明】
本発明はパルス信号の検出回路に関し、特にモノパルス
の到来時間を測定するためのパルス検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse signal detection circuit, and more particularly to a pulse detection circuit for measuring the arrival time of a monopulse.
従来、この種のパルス検出回路は第１図に示すように、
増幅回路１１と電圧比較回路１２とから構成されており
、入力パルス１１０を増幅回路１１で増幅し一定の電圧
△Ｖを検出し・ベルとして電圧比較回路１２で出力パル
ス１１２を得る回路であった。したがって、第２図に示
すように入力パルス１１０のピーク値が変動すると出力
パルス１１２の縁端が真の到来時刻ｔェ０に対しＬある
し・はらと変動することになる。入力パルスのピークの
値に応じて検出された時刻ｔが変動すると、例えばパル
スの伝搬時間から距離を測定する距離計などでは測定誤
差を生ずることになる。一方、パルスの繰返しが多い場
合には、第１図に示す増幅回路１ １をＡＧＣ増幅回路
にすることで、この種の測定誤差を軽減することが可能
であるが、パルスの繰返しが少ない場合、あるいは単発
のパルスで距離を測定する場合にはＡＧＣ増幅回路を使
用することが困難である。Conventionally, this type of pulse detection circuit, as shown in Figure 1,
It was composed of an amplifier circuit 11 and a voltage comparator circuit 12, and the input pulse 110 was amplified by the amplifier circuit 11, a constant voltage ΔV was detected, and the output pulse 112 was obtained from the voltage comparator circuit 12 as a bell. . Therefore, as shown in FIG. 2, if the peak value of the input pulse 110 fluctuates, the edge of the output pulse 112 will fluctuate from L to F with respect to the true arrival time te0. If the detected time t varies depending on the peak value of the input pulse, a measurement error will occur in, for example, a distance meter that measures distance from the propagation time of the pulse. On the other hand, when there are many pulse repetitions, it is possible to reduce this type of measurement error by replacing the amplifier circuit 1 shown in Fig. 1 with an AGC amplifier circuit, but when there are few pulse repetitions, it is possible to reduce this type of measurement error. , or when measuring distance using a single pulse, it is difficult to use an AGC amplifier circuit.
本発明は入力パルスのピーク値に変動があっても、常に
入力パルスのピーク値の数分の１（例えば１／２）を検
出レベルとして入力パルスを検出することにより、上記
欠点を解決し、ピークの変動があっても時間変動ないこ
パルスを検出できるようにしたパルス検出回路を提供す
るものである。The present invention solves the above-mentioned drawbacks by always detecting input pulses at a detection level of a fraction (for example, 1/2) of the peak value of the input pulse even if the peak value of the input pulse varies. The present invention provides a pulse detection circuit that can detect time-varying insulating pulses even if there are peak fluctuations.
上記目的を達成するため本発明によるパルス検出回路は
、入力パルス信号を増幅する対数増幅回路の出力を遅延
させた信号と、対数増幅回路の出力とを一定の偏椅電圧
をもって比較する如く構成している。次に本発明の実施
例について図面を参照して説明する。In order to achieve the above object, the pulse detection circuit according to the present invention is configured to compare a signal obtained by delaying the output of a logarithmic amplifier circuit that amplifies an input pulse signal with the output of the logarithmic amplifier circuit with a constant bias voltage. ing. Next, embodiments of the present invention will be described with reference to the drawings.
第３図は本発明の実施例を示すブロック図であり、２１
は入力パルス１２０を増幅する対数増幅回路、２２は対
数増幅回路２１の出力１２１を一定時間遅延する遅延回
路、２３は遅延した信号を一定電圧△Ｖだけ偏崎する加
算回路、２４は加算回路２３の出力１２３と対数増幅回
路の出力１２１とを比較して出力パルス１２４を得る電
圧比較回路である。第４図は対数増幅回路２１の入出力
特性の一例を示す図、第５図は第４図に示すブロック図
の各部波形を示す図である。FIG. 3 is a block diagram showing an embodiment of the present invention, and 21
22 is a delay circuit that delays the output 121 of the logarithmic amplifier circuit 21 for a certain period of time; 23 is an adder circuit that biases the delayed signal by a certain voltage ΔV; 24 is an adder circuit 23 This is a voltage comparison circuit that obtains an output pulse 124 by comparing the output 123 of the logarithmic amplifier circuit with the output 121 of the logarithmic amplifier circuit. FIG. 4 is a diagram showing an example of input/output characteristics of the logarithmic amplifier circuit 21, and FIG. 5 is a diagram showing waveforms of various parts of the block diagram shown in FIG. 4.
対数増幅回路の出力は、対数の性質から、入力電圧が２
倍変化した場合、例えば０．５ボルトから１ボルトに２
倍変化しても、０．０５ボルトから０．１ボルトに２倍
変化してもその出力の差△Ｖは常に等しい電圧値である
。Due to the logarithmic nature, the output of a logarithmic amplifier circuit is
If the change is doubled, for example from 0.5 volts to 1 volt,
Even if the voltage changes by a factor of two or from 0.05 volts to 0.1 volts, the output difference ΔV is always the same voltage value.
第５図に示すように、パルスの検出出力１２４は対数増
幅回路の出力１２１を検出レベルとして、同出力１２１
を一定時間遅延した後一定電圧△Ｖを加算した信号１２
３を検出することにより得られる。As shown in FIG. 5, the pulse detection output 124 uses the output 121 of the logarithmic amplifier circuit as the detection level.
Signal 12 which is obtained by adding a constant voltage △V after delaying for a certain time
It can be obtained by detecting 3.
ここで加算する電圧△Ｖを対数増幅回路２１の入力の２
倍の変化に対応した出力電圧差と等しい値に選んでおく
ものとすれば、入力パルス１２０のピーク値の２分の１
の値を検出レベルとして入力パルス１２０を検出するこ
とになり、したがって、入力パルスのピーク値が変化し
ても検出出力１２４のパルスの後縁の時亥比，は変化し
ない。なお、電圧△Ｖの値は任意に選ぶことが出来、こ
の電圧値に対応して入力パルスのピーク値の１／Ｎ（Ｎ
：正数）を検出レベルとすることが出来る。The voltage △V to be added here is
If the value is chosen to be equal to the output voltage difference corresponding to the change in the value of 1/2 of the peak value of the input pulse 120,
The input pulse 120 is detected using the value of as the detection level. Therefore, even if the peak value of the input pulse changes, the time ratio of the trailing edge of the pulse of the detection output 124 does not change. Note that the value of the voltage △V can be arbitrarily selected, and 1/N (N
: positive number) can be set as the detection level.
本発明は以上説明したように、入力パルスの個々のパル
スに対しピーク値の数分の１の値を検出レベルとして検
出するように構成することにより、入力パルスのピーク
値に変動があっても時間変動ないこパルスを検出できる
効果がある。As explained above, the present invention is configured to detect a value that is a fraction of the peak value for each input pulse as the detection level, so that even if there is a fluctuation in the peak value of the input pulse, This has the effect of detecting time-varying electric pulses.
さらに入力パルスの増幅に対数増幅回路を用いるので、
広いダイナミックレンジが得られる効果がある。Furthermore, since a logarithmic amplifier circuit is used to amplify the input pulse,
This has the effect of providing a wide dynamic range.
第１図は従来のパルス検出回路を示すブロック図、第２
図は同各部波形を示す図、第３図は本発明の一実施例を
示すブロック図、第４図は第３図に示す対数増幅回路の
入出力特性を示す図、第５図は第３図の各部波形を示す
図である。
２１…・・・対数増幅回路、２２・・・・・・遅延回路
、２３・・・・・・加算回路、２４・・・・・・電圧比
較回路。
第１図第２図
第３図
第４図
寿Ｓ図Figure 1 is a block diagram showing a conventional pulse detection circuit, Figure 2 is a block diagram showing a conventional pulse detection circuit.
3 is a block diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing input/output characteristics of the logarithmic amplifier circuit shown in FIG. 3, and FIG. It is a figure which shows the waveform of each part of a figure. 21... Logarithmic amplifier circuit, 22... Delay circuit, 23... Addition circuit, 24... Voltage comparison circuit. Figure 1 Figure 2 Figure 3 Figure 4 Kotobuki S diagram
Claims (1)
の対数増幅回路の出力を所定時間遅延させる遅延回路と
、前記対数増幅回路の出力と前記遅延回路の出力とを一
定の偏倚電圧をもつて比較する比較回路とを備えて成る
ことを特徴とするパルス検出回路。1. A logarithmic amplifier circuit that logarithmically amplifies an input pulse signal, a delay circuit that delays the output of the logarithmic amplifier circuit for a predetermined time, and a comparison between the output of the logarithmic amplifier circuit and the output of the delay circuit with a constant bias voltage. What is claimed is: 1. A pulse detection circuit comprising: a comparison circuit that performs
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11862380A JPS6018944B2 (en) | 1980-08-28 | 1980-08-28 | Pulse detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11862380A JPS6018944B2 (en) | 1980-08-28 | 1980-08-28 | Pulse detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5742860A JPS5742860A (en) | 1982-03-10 |
| JPS6018944B2 true JPS6018944B2 (en) | 1985-05-13 |
Family
ID=14741102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11862380A Expired JPS6018944B2 (en) | 1980-08-28 | 1980-08-28 | Pulse detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6018944B2 (en) |
-
1980
- 1980-08-28 JP JP11862380A patent/JPS6018944B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5742860A (en) | 1982-03-10 |
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