JPS6019142B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device,
In particular, the present invention provides an optimal method for application to diodes having passivation films, vertical junction field effect transistors (hereinafter referred to as V-FETs), and the like.

Conventionally, this type of V-FET includes one in which a large number of source regions are formed between mesh-like gate regions, and a PN junction between the gate and the semiconductor substrate is covered with a Si02 film.

A so-called self-alignment method is used for this manufacturing. That is, first, as shown in FIG. IA, a Si02 layer 2, a Si3N4 layer 3, and a Si02 layer 4 are sequentially grown on the main surface of an N-type semiconductor substrate 1, and then predetermined portions of these three layers are etched away as shown in FIG. IB. A mesh-shaped gate 5 is formed, and then P-type impurities are diffused through the gate to form a mesh-shaped P-type gate region 6 in the semiconductor substrate 1.

Next, the Si3N4 layer 3 and Si02 around the gate region 6 are
A predetermined portion of the layer 4 is removed by etching as shown in FIG. 1C to open a window for isolation, thereby forming a cutout 7 that is connected to the outermost opening 5.

Next, in the state shown in FIG. IC, the Si02 layers 2 and 4 are etched using an etching solution capable of removing only Si02 and using the Si3N4 layer 3 as a mask.

As a result, the Si02 layer 4 is completely removed and also the Si02 layer 4 is completely removed.
The Si02 layer 2 under the i3N4 layer 3 is over-etched as shown in FIG. ID. The Sj3N4 layer 3 acts as a mask, but the Sj3N4 layer 3, which cannot be removed by this mask,
The i02 layer 2 remains with a small width of about 1 French, and this Si0
The second layer and the Sj3N4 layer 3 remain as if they were mushrooms. Next, using the Si02 layer 2 as a mask, the semiconductor substrate 1 including the gate region 6 is removed by etching to a predetermined depth, thereby forming a mesh-like recess 8 defined by the Si02 layer 2.

Next, the surface of the semiconductor substrate 1 is steam oxidized to grow a Si02 layer 9 in the recess 8 as shown in the younger IF diagram.

This Si02 layer is formed at the same height as the original substrate surface, and therefore has a thickness of about 5000Δ. Next, after removing the Si02 layer 2 and the Si3N4 layer 3 on the surface by etching, N-type impurities are diffused using the Si02 layer 9 as a mask, as shown in the plexus IG diagram.
A thin N0 type source region 10 is formed in a mesh shape between the i02 layers 9.

At this time, the back surface of the semiconductor substrate 1 is also doped with N type impurities to form an N+ type drain region 11. Next, a predetermined portion of the outermost Si02 layer 9 is removed by etching.
As shown in Figure I, the gate electrode 1 is placed on this removed part.
2, and a source electrode 1 is also deposited on the source region 10.
3 to cover the drain electrodes 14 on the drain regions 11, respectively.

In this way, a multi-channel V-FET can be manufactured, and the surface of this FET, especially the end of the PN junction between the source region 10 and the semiconductor substrate 1, is covered with the Si02 layer 9, and this Si02 layer is used for passivation. will appear. However, during operation of this FET, Si02
The disadvantage is that the positive charges present in the layer 9 cause an undesirable memory effect, resulting in the formation of channels on the substrate side, and that the polarization in the shielding resin causes the charges to be fixed.

As a result, the withstand voltage at the bonding surface decreases, and reliability deteriorates due to the influence of the external electric field. However, the green resistance of the Si02 layer 9 is not very good, which is disadvantageous in terms of stability and reliability, and thermal distortion is likely to occur at the boundary between these layers due to the difference in thermal expansion coefficient with the semiconductor substrate 1. It is also conceivable to use a silicon polycrystalline layer (hereinafter referred to as poly-Si layer) as a passivation film instead of Si02.

This poly Sj has a lower resistance than Si02 and does not cause the charge induction or fixation phenomenon seen in Si02, which makes it possible to improve the breakdown voltage and achieve high breakdown voltage in ICs. Charge movement in the semiconductor substrate occurs through the layers, causing various problems such as an increase in reverse leakage current. However, since the step of forming the poly-Si layer is performed after all of the above-mentioned diffusion steps have been completed, it is necessary to deposit the source electrode by opening a window in the poly-Si layer. As shown in FIG. 1G, the width of the source region is extremely narrow and minute, about 1 mm, so it is extremely difficult to open the window using the photomask method. Therefore, another method is expected that takes advantage of the advantages of the poly-Si layer and provides passivation with excellent characteristics.

The present invention was invented to correct the above-mentioned defects, and includes a step of selectively forming a mask layer on the surface of a semiconductor layer having an exposed junction, and a step of selectively forming a mask layer on the surface of a semiconductor layer having an exposed junction. a step of forming a polycrystalline silicon layer containing 40 to 5 t% of oxygen atoms formed by chemical vapor deposition on the surface of the semiconductor layer containing the mask layer; and removing a predetermined portion of the semiconductor device. This method not only simplifies the process by easily depositing the electrodes, but also provides extremely stable and reliable passivation. Next, embodiments of the present invention will be described with reference to FIGS. 2 to 4.

Figures 2 and 3 show a first example in which the present invention is applied to a V-FET.
This is an example of the following.

In this embodiment, intermediate steps are the same as the conventional example.

That is, since the steps shown in FIGS. IA to IE are the same in this embodiment, their explanation will be omitted, and common parts in the subsequent steps will be given the same reference numerals. The etching depth of the semiconductor substrate 1 shown in FIG. IE is 5000A or more,
For example, let it be 5000A.

As a subsequent step, first, only the Sj3N4 layer 3 is removed by etching, and then, as shown in FIG. Δ or more, for example, a poly-Si layer 29 of about 5000 Å is grown in a vapor phase using an apparatus to be described later. This poly-Si layer has an average grain size of 1000
It consists of grains of 0A or less, and it seems that there is no Si02 that completely surrounds the grains between these grains and the semiconductor substrate 1. Poly-Si
The oxygen atoms in layer 29 are 40-5 t% (atomic %)
It is preferable that the amount of oxygen atoms is small, and polySi
The bonding force at the grain boundaries of Si02 is strong, making the removal process described below difficult, and if too much Si02 is present, moisture resistance and, ultimately, reliability deteriorate, as with Si02. Further, it is preferable that the poly-Si layer 29 be thicker in order to reduce the capacitance between the gate region and the source electrode described later, but if it is too thick, the removal process described later becomes difficult; Preferably one Buddha. When the poly-Si layer 29 is then immersed in a hydrofluoric acid solution in the state shown in FIG.
The poly-Si on the i02 layer 2 is also removed.

In this case, since the poly-Si layer 29 contains oxygen atoms in the above-mentioned range and has an appropriate thickness, the poly Sj' on the Si02 layer 2 can be easily removed. As a result, 2nd B
As shown in the figure, a mesh-like entrance 25 can be formed in the portion where the Sj02 layer 2 was present. Then open □25
The N-type impurity is diffused into the semiconductor substrate 1 through the second
As shown in Figure C, a thin mesh-like N0 type source region 10 is formed between the poly-Si layers 29.

At this time, the poly-Si layer 29 functions as a mask against impurity diffusion, and the reason for this is that although pure poly-Si exhibits a diffusion coefficient comparable to that of single crystal, it contains oxygen in the above range. This is because the diffusion coefficient becomes extremely small. Note that at the same time as this source diffusion, the back surface of the semiconductor substrate 1 is also doped with impurities, thereby forming an N+ type semiconductor layer drain region 11. Next, a predetermined portion of the outermost poly-Si layer 29 is treated with, for example, HF and NH.
A gate electrode 12 consisting of a mountain is deposited from this removed portion to the surface of the poly-Si layer 29, as shown in FIG. 2D. A source electrode 13 and a drain region 14 made of AI are deposited thereon.
Note that the ends of the PN junction between the gate region 6 and the semiconductor substrate 1 are all covered with a poly-Si layer 29. Note that when forming the poly-Si layer 29, a vapor phase growth apparatus shown in FIG. 3 may be used. The furnace 20 of this apparatus includes a gas source 21 for monosilane (SiH4), a gas source 22 for dinitrogen monoxide (N20), and a gas source 23 for ammonia (NH3) to supply predetermined gases thereto. and a gas source 24 for nitrogen (N2) gas as a carrier gas are connected via regulating valves, flow meters, etc., respectively.

The semiconductor substrate 1 in the state shown in FIG.
The semiconductor substrate 1 is heated to a temperature of qo. This temperature is the temperature when SiH4 is used as the silicon supply source, and when another silane gas is used, it may be determined by appropriately considering the reaction temperature of the gas. A gas source 24 within the furnace 20
The Si ratio and N20 are introduced from gas sources 21 and 22, respectively, along with the carrier gas. In this case, SjH4
is combined from a gas source 21 with an inert gas at a concentration of 5%. As a result, decomposition occurs on the semiconductor substrate 1, and polycrystalline silicon containing oxygen atoms due to dinitrogen monoxide (N20) can be formed on the surface of the semiconductor substrate by chemical vapor deposition. In this case, the proportion of oxygen atoms in polycrystalline silicon can be determined by selecting the flow rate ratio of N20 and SiH4. In this example, N
A poly Sj layer 29 doped with about 4 t% of oxygen atoms is obtained by setting the ratio of 20/SiH4 to about 5. Note that, in addition to N20, nitrogen oxides such as N◯ and N02 can be used as the supply source of oxygen atoms, but in this case, the amount of doping of oxygen atoms can be easily controlled. Also, silicon halide, such as SIC14, may be used instead of SjH4, but it requires growth at a higher temperature (110,000 ℃) than SiH4, so SiH
4 is preferably used. According to the manufacturing method described above, there is no need to open a window in the poly-Si layer 29 when depositing the source electrode on the fine source region, and therefore the electrode can be provided by simply depositing the source electrode 10 on the surface. This makes it possible to greatly simplify the process.

In addition, since the surface of the semiconductor substrate 1, especially the PN junction end between the reverse biased gate region 6 and the semiconductor substrate 1, is covered with the poly-Sj layer 29 containing a predetermined amount of oxygen, it has the above-mentioned characteristics of poly-Si. , this drawback can be avoided. That is, since the resistance is higher than that of pure poly-Si, there is no charge movement, and reverse leakage current can be significantly reduced, making it possible to prevent deterioration due to external electric fields and temperature fluctuations. Furthermore, fluctuations in properties due to moisture are extremely reduced, and moisture resistance can be improved.
Next, a second embodiment in which the present invention is applied to a mesa type transistor will be described with reference to FIG.

First, as shown in FIG. 4A, a P-type base region 33 is grown on an N-type semiconductor substrate 31 that will become a collector region, and a Si02 layer (not shown) is uniformly formed on this base region. The Si02 layer is partially removed by conventionally known photo etching to form the Si02 layer 32 in a predetermined pattern.

Next, mesa etching is performed using this Si02 layer as a mask, thereby forming the base region 33 as shown in FIG. 4B.
The end of the PN junction between the collector region 31 and the collector region 31 is exposed to the surface.

Then, in the same manner as described in the first example, 40 to 5
A poly-Si layer 39 containing approximately t% of oxygen atoms is formed to a thickness of about 5000 Å by chemical vapor deposition as shown in FIG. 4C.

Next, in the same manner as described in the first embodiment, Si02
Layer 22 and the poly-Si above it are simultaneously removed to form a poly-Si layer.
A closure 35 is formed in layer 39.

In this case, the above-mentioned exposed PN junction end is made of poly-Si.
Leave it covered with layer 39. Next, as shown in FIG. 4E, an electrode 34 is applied to the closure 35, and at this time, a metallurgical N-type emitter region 36 is formed at the contact surface with the base region 33.

According to this embodiment, even when the electrode contact area is much wider than that of the first embodiment, that is, in the case of a mesa type transistor, the manufacturing process is easy, and the reverse biased P
Since the N-junction is covered with the poly-Si layer 39, it is possible to obtain excellent stability and reliability as in the first embodiment.

Although the present invention has been described above based on embodiments, it will be understood that further modifications can be made based on the technical idea of the present invention.

For example, in the first embodiment, Si3 shown in FIG.
The semiconductor substrate 1 may be etched after the N4 layer 3 is removed. Further, another poly-Si layer containing nitrogen may be formed on the poly-Si layers 29 and 39. This poly-Si layer is easily formed by supplying NH3 from the gas source 23 in the apparatus shown in FIG. 3, and preferably has a nitrogen atom content of 3 t% or more. When this poly-Si layer was formed to form a double structure, the green resistance was greatly improved, and this was evidenced by the extremely small fluctuation in reverse VR when treated with steam. Furthermore, when the Si02 layer is present in the poly-Si layers 29 and 39, the water resistance or charge resistance is further improved compared to the case where the poly-Sj layer is exposed on the surface. In this case, defects due to Sj02, which have been observed in the past, did not occur because the poly-Si layers 29 and 39 blocked the charge bond between Si02 and the substrate. It has also been found that the stability and reliability are further improved even when Si02 is further coated on top of the double-layered structure. Furthermore, although the second embodiment has shown the outline of mesa etching, it will be easily understood that this can be applied to the case where a large number of mesa structures are simultaneously formed within the same substrate. Note that the present invention is of course applicable to the manufacture of integrated circuits. As described above, the present invention covers the mask layer formed on the surface of the semiconductor layer and the exposed junction with a poly-Si layer containing 40 to 5 t% of oxygen atoms, which is formed by chemical vapor deposition. At the same time, since the poly-Si above is removed, there is no need to etch the poly-Si in minute areas, and it is sufficient to simply attach the electrodes, thereby simplifying the manufacturing process.

In addition, since poly-Si can be left on the surface, this poly-Si covers the bond, and therefore, compared to conventional passivation using Si02, deterioration due to external electric fields, humidity, temperature, etc. is extremely reduced, resulting in excellent stability and reliability. equipment can be provided.

[Brief explanation of drawings]

FIG. 1 shows a conventional example, and is a schematic sectional view showing a V-FET manufacturing method in order of steps. Figures 2 and 3 show a first example in which the present invention is applied to a V-FET.
FIGS. 2A to 2D show examples of V
- A schematic cross-sectional view showing the FET manufacturing method step by step; FIG. 3 is a schematic view of a vapor phase growth apparatus used to form a poly-Si layer. FIG. 4 shows a second embodiment in which the present invention is applied to a mesa transistor, and is a schematic cross-sectional view showing a method for manufacturing a mesa transistor in order of steps. Also, in the symbols used in the drawings, 2 is the Si02 layer, 3 is the S
i3N4 layer, 4 is Si02 layer, 6 is gate region, 9 is S
10 is a source region, 11 is a drain region, 29 is a poly Sj layer, 32 is a Si02 layer, 33 is a base region, 36 is an emitter region, and 39 is a poly Si layer. Fig. IA Fig. IB Fig. IC Fig. ID Fig. IE Fig. IF Fig. IG Fig. IH Fig. 2A Fig. 2B Fig. 2C Fig. 2D Fig. 3 Fig. 4A Fig. 4B Fig. 4C Fig. 4D Figure 4E

Claims (1)

[Claims] 1. A step of selectively forming a mask layer on the surface of a semiconductor layer having an exposed junction, and a step of forming a mask layer on the surface of the semiconductor including the exposed junction and the mask layer by chemical vapor deposition. A semiconductor device comprising the steps of forming a polycrystalline silicon layer containing 40 to 50 at% oxygen atoms, and removing a predetermined portion of the polycrystalline silicon layer thereon together with the mask layer. manufacturing method.