JPS6019516B2 - Screen editing method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a screen editing method in a display device.

In recent years, when information is processed by an information processing device, a CRT display device, for example, has been adopted as an output device so that the device and an operator can perform the processing in a conversational manner.

With this type of CRT display device, an operator can correct the displayed content, that is, information, while looking at the display screen.
Constructed for editing. However, in the past, when editing a screen, if the number of characters in the corrected line increases due to modification or addition of display data, and you want to move part of it to the next line, the top or bottom line of the screen must be deleted. The display above the corrected line is shifted upward by one line, or the display below the corrected line is shifted downward by one line, and the characters to be moved to the corrected line are displayed on the empty line. Editing of the display screen is performed in this way, but conventionally, the line to be erased during editing is set in advance to either the top or bottom line of the screen, so the top line or bottom line of the screen must be edited. When doing so, the modified line may be deleted, which is a problem. The present invention has been made in view of the above points, and when editing the screen, the top line,
It is an object of the present invention to provide a screen editing method that can determine which bottom line is to be erased and can reliably prevent the correction line from being erased.

An embodiment of the present invention will be described below with reference to the drawings.

First, the overall configuration will be explained with reference to Figure 1.
1 is a CPU (central processing unit), and this CPU is connected to 1/0 ports 4 and 5 via an address bus 2 and a data bus 3.
is connected. Also, this 1/0 boat 4 and 5 have CP
An enable signal is given from the UI via the enable line 6a. A CRT display section 7b is connected to the 1/0 boat 4 via a display control section 7a, the details of which will be described later, and a key input section 8 is connected to the 1/0 boat 5. Further, a main memory 10 is connected to the CPUI via an address bus 2, a data bus 3, a control bus 9, and an enable line 6b. The above CPUI' outputs address data via address bus 2 and 1/0 port 4.
, 5, addresses the main memory 10, and then sends and receives data via the data bus 3, that is, the key input section 8
It accepts input data from the main memory 1O', sends display data to the display control section 7a, and writes and reads data to and from the main memory 1O'. Further, display data inputted from the key input section 8 is sent from the CPUI to the display control section 7a via the 1/0 port 4, written in the fresh memo section in the display control section 7a, and displayed. After confirming the display, the data input to the IJ fresh memory is sent to the main memory 01 and written therein. Next, details of the display control section 7a will be explained with reference to FIG. The 1/0 boat 4 outputs a read/write command R/W, a select signal S, register designation signals C, C2, and data from the data bus 11 according to commands from the CPUI. Data output via the R/W and data bus 11 is sent to the refresh memory 12. Then, the select signal S is supplied to the selector 13, and the register designation signal C and the data output from the data bus 11 are supplied to the cursor address register 14. In addition, register designation signal C2
The data output from the data bus 11 is supplied to the sweep pointer 15. This sweep pointer 15
The contents set are sent to the row designation counter 8 via an AND circuit 17 gate-controlled by a vertical synchronization signal from the scanning section 16. The output of the row designation counter 18 is sent to the display address counter 20 via an AND circuit 19 gate-controlled by a horizontal synchronization signal from the scanning section 16. This display address counter 20
The contents of the cursor address register 14 are added to the match circuit 21, selected by the selector 13, and sent to the refresh memory 12 to designate its output address or write address. The data read from the refresh memory 12 is also sent to the character generator 22. When character data is input from the refresh memory 12, the character generator 22 generates a dot pattern corresponding to the character data according to a signal provided from the scanning section 16 via the decoder 23. The dot pattern output from the character generator 22 is converted into serial data by a P-S (parallel-serial) conversion register 24, and sent to the CRT display section 7b as a video signal via an OR circuit 25. The scanning unit 16 includes a pulse generator 31 that generates a reference pulse signal, an octal dot counter 32 that counts the pulse signals output from the pulse generator 31, and an output of the dot counter 32 that counts the output of the dot counter 32. It consists of an 8G Hayabusa character counter 33, a 12-decimal raster counter 34 that counts the output of this character counter 33, and a 2K Hayabusa row counter 35 that counts the output of this raster counter 34.
The signal output from the dot counter 32 for each character is sent to the display address counter 2 as a count up signal and is also applied to the AND circuit 26. Further, the output of the character counter 33 is taken out as a horizontal synchronizing signal, sent to the CRT display section 7b, and added to the AND circuit 19. Further row counter 3
The output of 5 is taken out as a vertical synchronizing signal, sent to the CRT display section 7b, and also applied to the AND circuit 17. The contents of raster counter 34 are then added to decoder 23. This decoder 23 includes output lines a to d, and outputs a signal from each output line a to d according to the contents of the raster counter 34. That is, when the count content of the raster counter 34 is "0" to "8", a "1" signal is output from the output line a of the decoder 23, and when the count content reaches "10", a "1" signal is output from the output line c.
” signal, and when the count reaches 111, a “1” signal is output from the output line d. Also, the content of the raster counter 34 is output as is from the output line b of the decoder 23, and the character generator The output signal of the output line a of the decoder 23 is applied to the AND circuit 27 along with the output of the pulse generator 31, and the output of the AND circuit 27 is sent to the P-S conversion register 24 as an operation signal. Also, decoder 2
The signal output from the output line c of No. 3 is applied to the matching circuit 21, and the signal output from the output line d is applied to the AND circuit 26. The output signal of this AND circuit 26 is applied to the row designation counter 18 as a count up signal. The scanning unit 16 is configured to display one character in a 7×9 dot matrix, with 80 characters per line and 2 letters per screen. Moreover, each row is a raster Lo to L, . Consisting of IZ rasters (horizontal scanning lines), characters are displayed in rasters L to L8, raster L, . to display the cursor and select the raster L, L, . is displayed as empty. Next, the operation of the present invention configured as described above will be explained.

The sweep pointer 15 is set to 1 by a command from the CPUI.
Data specifying the read start line of the refresh memory 12 is set via the /0 port 4. For example, if display is to be started from address 0 of the refresh memory 12, that is, from the first row, the sweep pointer 15 is set to "0". The contents of the sweep pointer 15 are transferred to the row designation counter 8 via the AND circuit 17 in synchronization with the vertical synchronization signal. Furthermore, this row specification counter 18
The contents of are transferred to the display address counter 20 via the AND circuit 19 in synchronization with the horizontal synchronizing signal. The contents of the display address counter 20 are sent to the refresh memory 12 via the selector 13, and specify the top address of the display start line. The above selector 13 is 1/0 from CPUI
It operates in response to a select signal S applied via the port 4, and in display mode selects the output of the display address counter 20 and applies it to the refresh memory 12. Since the content of the display address counter 20 is initially "0", the character data at address 0 of the refresh memory 12 is read out and sent to the character generator 22. At this point, the content of the raster counter 34 is "0" and the data is sent to the character generator 22 via the decoder 23.
generates a dot pattern of character data for raster L. This dot pattern is sent to the P-S conversion register 24, and the contents of the raster counter 34 are changed from "0" to "
8'', it is converted into serial data in synchronization with the pulse signal output from the AND circuit 27. This si I
J Aldata is CR from OR circuit 25 as a video signal.
It is sent to the T display section 7b and displayed. Then, the data for one character is transmitted from the OR circuit 25 to the CRT display section 7.
When the signal is sent to b, the dot counter 32 outputs a "1" signal, and the display address counter 20 counts up by "11." This designates the next address in the refresh memory 12, and new character data is Thereafter, the contents of the display address counter 20 are counted up in the same manner, and the contents of the refresh memory 12 are sequentially retrieved.When scanning for one raster is completed, a horizontal synchronizing signal is output from the character counter 33. The gate of the AND circuit 19 is opened, the contents of the row designation counter 18 are again set to the display address counter 20', and the same operation as above is repeated.Then, the above operation is performed for one row, and the raster counter 34 is When the content becomes "11", a "1" signal is output from the output line d of the decoder 23 to the AND circuit 26. Therefore, the pulse output from the dot counter 32 is output to the row designation counter 18 via the one-raster period AND circuit 26. That is, the contents of the line designation counter 18 are counted up by "80". The contents of the row counter 18 are sent to the display address counter 20 via the AND circuit 19 in response to the horizontal synchronization signal, and are sent to the display address counter 20 in the refresh memory 12.
Specify the start address of the next line. In this way, the contents of the row designation counter 18 are sequentially counted up, and the rows to be read from the refresh memory 12 are sequentially designated. When the stored contents of the refresh memory 12 for one screen are read out, a vertical synchronizing signal is output from the row counter 35, the gate of the AND circuit 17 is opened, and the contents of the sweep pointer 15 are transferred via the AND circuit 17 to the row designation counter 18. is set again. As a result, the row designation counter 18 returns to its initial state and designates the first row of the refresh memory 12. Thereafter, the contents of the refresh memory 12 are retrieved by similar operations and displayed on the CRT display section 7b. FIG. 3 shows an example of the display.
Note that in the display data, a start mark ">" is displayed on the first line of each data block. Therefore, when writing new data, modifying data, etc., a cursor is displayed at the data writing or modification position.

The address of the cursor display is set in the cursor address register 14 from the CPU via the 1/0 port 4. Then, the contents of the cursor address register 4 and the contents of the display address counter 20 match, and the contents of the raster counter 34 become "10", and a "1" signal is output from the output line d of the decoder 23. The output of the matching circuit 21 becomes "1". The output of this matching circuit 21 is sent to the CRT display section 7b via the OR circuit 25, and the last output L is sent to the CRT display section 7b. The cursor is displayed at . When writing data, a select signal S is sent from the CPU via the 1/0 port 4 to the selector 13, and the selector 13 is switched to the cursor address register 4 side.
At the same time, a write command and data are given to the refresh memory 12 from the CPU via the 1/0 port 4,
Data is written to the address specified by the cursor address register 4. Next, the control operation of the CPU when modifying display data will be explained with reference to the flowchart of FIG.

Figure 4 shows a flowchart for inserting one character on the cursor by shifting the character to the right of the cursor by one character. Check to see if there is a start mark on the top. In other words, since the start mark is not modified, the check in step A above is performed, and if there is a start mark, the force-sol address M stored in main memory 01 is checked as shown in step B.
Add c to 11. Then, the new cursor address Mc is set to 0 in the main memory as shown in step C.
, and set it in the cursor address register 14 via the 1/0 port 4. This will display the cursor next to the start mark. If the cursor is initially displayed at the start mark position as described above, the cursor is advanced by one character without performing any correction processing, and the process ends. Therefore, even if correction data is input while the cursor is displayed at the start mark position, the input data becomes invalid, and the start mark can be prevented from being erased. Further, in step A, if there is no start mark on the cursor, the process proceeds to step D, where the cursor address Mc stored in the main memory 10' is written into the storage area M, in the main memory 10'.

Next, the process proceeds to step E, where it is determined whether the cursor address Mc and the sweep pointer Ms stored in the main memory 10 are equal. As a result of this determination, if cursor address Mc and sweep pointer Ms are not equal,
As shown in step F, the cursor address Mc is transferred to the cursor address register 14. The force set in this cursor address register 4 - sol address Rc
The cursor is displayed. Next, as shown in step G, it is determined whether or not there is a start mark on the cursor. In this judgment, if there is no start mark on the cursor, the step mark is advanced and it is judged whether or not there is a space code on the cursor. If it is determined that there is no space code on the cursor on this step date, the cursor address Mc in the main memory 10 at this time is stored in the storage area M2 in the main memory 10, as shown in step 1. Next, the process advances to step J, increments the cursor address Mc to 11, and returns to step E. Further, if it is determined that there is a space code on the cursor on the step date, step 1 is jumped and the process proceeds to step J. The above steps E to J are repeated until the cursor address Mc in the main memory 10 becomes equal to the sweep pointer Ms in step E or until it is determined that there is a start mark on the cursor in step G. In addition, the contents of the storage area M2 are sequentially rewritten to the cursor address incremented by 11 until it is determined that there is a space code on the cursor on the step date, so the storage area finally has the address of the last character of the block data. is memorized. Therefore, if it is determined in step E that the cursor address Mc and the sweep pointer Ms are equal, that is, if the cursor moves sequentially to the right of the screen and searches to the top of the screen, or if there is a start mark on the cursor in step G. In other words, if the cursor has searched to the beginning of the next data block line, proceed to step K, decrement the cursor address Mc by 1, and move the cursor to the last position on the screen or the last position of the modified block. Return address Mc.

Next, as shown in step L, it is determined whether the cursor address Mc and the contents of the storage area M2 are equal. That is, in step L, it is determined whether there are characters until the last line or the end of the screen. If it is determined in this step L that the contents of the cursor address Mc and the storage area location are equal, the process advances to step M, and the sweep pointer M
It is determined whether the value obtained by subtracting s by 1 and the contents of the storage area M2 are equal. If the judgment result in step M is YES, that is, if there are characters to the end of the screen, the process proceeds to step N, and the cursor address corresponding to the first cursor position stored in storage area M, that is, the correction part is "MsSM,<
It is determined whether the condition of "Ms 180" is satisfied or not. This step N is to judge whether or not the cursor display indicating the correction position is on the first line of the screen, and the judgment result is N.
If O, proceed to process 0. Further, if it is determined in step M that there are characters until the end of the screen, the process also proceeds to process 0. This process 0 performs insert processing for one line above or below the corrected line, and the details will be described later. When this process ○ is completed or if NO is determined in step L, the process goes to step P, and if there is no character at the end of the correction block, the cursor address M
Rewrite c with the contents of storage area M. That is, the cursor address Mc is returned to the address of the nine character insertion position. Next, as shown in step Q, a space code is written in the storage area M3 in the main memory 0, and then, as shown in step R, the cursor address Mc is written in the cursor address register 4. Then, as shown in step S, the data on the cursor specified by this cursor address register 4 is retrieved from the refresh memory 12 and written into the storage area M4 of the main memory 0.
Next, as shown in step T, the space code stored in the annotation area M3 is retrieved and written into the refresh memory 12 specified by the cursor address.
Thereafter, the process proceeds to step U, and the data in the storage area M4 is transferred to the storage area M3. Then, as shown in step V, it is determined whether the value added to the storage area M2 is equal to the cursor address Mc, and if the determination result is NO, step W
The program advances to step R, increments the cursor address Mc, advances the cursor display by one digit, and returns to step R. Steps R to W above are performed until the judgment result in step V becomes YES, and one character's worth of space is inserted at the modified location, and the data of the modified block after the modified location is shifted one character to the right. will be moved to For example, as shown in the display example in Figure 3, if "PINT" is incorrectly displayed in the third line where "PRINT" should be displayed, you can move the cursor to "1" and The corrective action will be taken. In other words, in the initial state, the display is "PINT", but after one cycle of steps R to W, it becomes "P]NT" (where brackets are a space code). "P]IT" → "P]IN" → "P]INT"
and changes. Then, when the judgment result of step V becomes YES, that is, the last character of the data block has been moved one character to the right, or when the judgment result of step N becomes YES, that is, the characters reach the end of the screen. is present and the cursor is on the first line of the screen, proceed to step Then, the cursor address Mc is transferred to the cursor address register 14. As a result, the corrected part is displayed as "P]mT", and the space code part is displayed with a cursor. Therefore, in this state, the corrected data "R"
By entering , the display will become "PRINT",
Complete the correction process. Next, the one-line insert process in process 0 will be explained with reference to the flowchart shown in FIG. First, as shown in step A, "79" is subtracted from the cursor address Mc to set the cursor at the end of the line to the beginning of the line. Next, as shown in step B, "0" is written in the storage area M5 of the main memory 10, and then, as shown in step C, the cursor address Mc is transferred to the cursor address register 14. Then, as shown in step D, it is determined whether or not there is a start mark on the cursor, and if the result of the determination is YES, as shown in step E, the storage area M5 is
Proceed to. If the determination in step D is NO, step E is jumped and the process proceeds to step F. In this step F, it is determined whether the content of the storage area M5 is "4" or not. If the determination result is NO, the process proceeds to step G and it is determined whether the cursor address is "0" or not. If the determination result in step G is NO, "80" is subtracted from the cursor address Mc as shown in the step date, the start address of the line one line above the corrected line is specified, and the process returns to step C. Steps C to Day above are for determining whether there are four or more display lines each with a start mark above the correction line, and there is a margin of four or more lines above the correction line. If there is, the judgment result in step F will be YES,
If there is no margin of four or more lines above the corrected line, the determination result in step G becomes YES. However, if the determination result in step G is YES, proceed to step 1, roll down the entire screen by one line, erase the bottom line display,
Thereafter, as shown in step J, the screen above the corrected line is shifted up by one line and returned to its original state. Furthermore, if the determination result in step F is YES, proceed to step K.
"80" is subtracted from the sweep pointer Ms, and the subtraction result is set as the cursor address.

Next, the process advances to step L, where the cursor address Mc is set to "0".
”. This judgment result is YES
If so, the cursor address M is set as shown in step M.
Set c to "1840", that is, the first address of the bottom line, and proceed to step N. Also, the determination result of step L is N
If it is O, the cursor address Mc at this time is the first address of the bottom line, so proceed directly to step N.
Cursor address Mc to cursor address register E14
Transfer to. Then, in step 0, it is determined whether or not there is a space code on the cursor. This step 0 is for determining whether or not the bottom row is empty. If the bottom row is empty, the process proceeds to step 1 and roll-down processing is performed. If the determination result in step ◯ is NO and the bottom line of the screen is not empty, the process proceeds to step P, where the entire screen is rolled up by one line and the top line is erased. Next, proceed to step Q and edit the screen below the correction line by 1.
Shift down a line. This completes the insert processing for one line. In the above embodiment, the top line is deleted if there is a margin of 4 or more lines above the correction line, but the margin is not limited to the above embodiment and can be set arbitrarily. be. Further, in the above embodiments, a CRT display device is shown as the display device, but the present invention is not limited to this, and any display device capable of screen display may be used, such as a liquid crystal display device or a plasma display. Of course. As described above, according to the present invention, when editing a screen, the display state of the screen is checked to determine the vertical shift direction of the screen, so that the correction line is the top line or the bottom line of the screen. It is possible to reliably prevent a modified line from being deleted even if the modified line is located at

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the overall schematic configuration, FIG. 2 is a configuration diagram showing details of the display control section in FIG. 1, and FIG. 3 is a display example. , FIG. 4, and FIG. 5 are flowcharts showing the operation contents. 1... CPU (Central Processing Unit), 4, 5...
...1/○ boat, 7a...display control section, 7b.
. . . CRT display section, 10 . . . Main memory, 12 . . . Refresh memory. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A start mark that indicates the beginning of a line for each data block on the display screen, a means for indicating the character insertion position using a cursor mark during character insertion operations in screen editing, and a means for indicating the character insertion position using a cursor mark when a character is inserted at the end of the character insertion line. A means for detecting the number of start marks located above the insertion line, and when the number of start marks detected by this means is less than a set value or when the bottom line of the display screen is blank, all the characters below the character insertion line are detected. means for shifting the line downward by one line, and when the number of start marks detected by the start mark number detecting means is greater than or equal to the set value and the bottom line of the display screen is not blank, all lines above the character insertion line. A screen characterized in that it is equipped with means for shifting the cursor mark upward by one line, and means for shifting characters after the cursor mark position backward one character at a time and writing input data at the position indicated by the cursor mark. Editing method.