JPS6019596B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a memory array in a semiconductor memory.

Conventional memory consists of one bit with one transistor,
For example, MOS (Metal-Odde-Semi-
Ond ratio (tor) memory employed circuits as shown in FIGS. 1 and 2.

That is, in FIG. 1, when reading out a memory cell MCo, for example, a word line Wo and another data line Do are connected.
A pulse is simultaneously applied to the dummy word line DW, belonging to the memory cells MCo and DM, and the minute differential signal output appearing on the two data lines Do, Do is used as the read signal from the memory cells MCo and DM, to the set signal Set of the preamble PAo. By turning on the pre-amplifier P, it is operated and amplified, and the voltage appearing on either the data line Do or Do is detected to discriminate between information "1" and "0". The reason why differential signal output is generated here is as follows.
The voltage stored in the capacitor Co of the dummy cell DM is
Since the voltage is set to approximately the middle of the voltages corresponding to the information "1" and "0" stored in the memory cell Co, the voltage appearing on the data line after reading the dummy cell is the "1" and "0" of the memory cell Co. This is approximately the middle of the data line voltage when reading 0''. Therefore, the difference between this intermediate value and the "1" and "0" outputs becomes a differential signal output with different polarity.

Figure 2 is a schematic diagram of a circuit that takes into account the geometrical arrangement when a BI memory is configured by mounting a plurality of the circuits shown in Figure 1 (for example, 64 circuits in this example) in one chip. It is.

In the figure, the white circles are memory cells, and the black circles are circles and dummy cells. For example, in order to extract the signal appearing on the data line Do to the outside as described above, the transistor Qo is turned on by the address signal Ao, and the signal on the data line Do is input to the main amplifier MA and amplified. , data output Do
Take it out of the chip as ut. Now, the drawbacks of such a configuration can be summarized as follows. That is, in the evening, only one of the differential signals appearing on the data lines Do and Do is amplified by the main amplifier MA, which is inferior in terms of high speed. ■Since one signal is taken out, electrical imbalance between Do and Do tends to occur, causing malfunction.

■The data lines Do, Do whose electrical characteristics should be balanced are
Due to the lack of geometrical proximity within the chip, Do,D
Unbalanced noise is likely to couple to the preamplifier, causing malfunction when the preamplifier is turned on. Due to these drawbacks,
Conventionally, there were limits to the design of high-speed, highly stable BI memory. One object of the present invention is to provide a memory cell layout that allows for dense packing of cells.
One object of the present invention is to provide a semiconductor memory with a large noise margin. To this end, one embodiment of the present invention provides a dynamic random access memory IJ' that compares and reads adjacent pairs of data lines, in which the data lines are placed on the capacitor plate in the capacitor area. By extending or overlapping them, it is possible to densely pack the active regions constituting the cell.

This will be explained in detail in Examples below.

FIG. 3 shows an example of the circuit.

That is, the data line pair Do, where differential read signals appear,
Dol are arranged close to each other in parallel as shown in the figure, and the word lines Wo to W, DWo, DW. One each and D. ,D
A memory cell is connected to only one of the intersections of o. When reading a certain memory cell (for example, an MC spot), the dummy cell DMo connected to the data line Do to which that cell is not connected is read out at the same time, and the differential voltage appearing on the data lines Do and Do is sent to the preamplifier PA.
Make effective use of o. The differential signal amplified by the preamplifier P passes through transistors Qo and Qo by application of an address signal Ao, which is the output of the decoder, and is input to the differential amplifier MA, where it is differentially amplified again. As described above, in the present invention, the electrical balance between Do and Do is not disturbed in any way as compared to the case of FIG. Figure 4 shows D
A memory cell that maintains the electrical balance of o and Do (
8 bits) is a schematic diagram of a connection method. In the figure, a, b, and c are methods of connecting memory cells to Do and Do every every other, every second, and every fourth memory cell, respectively. FIGS. 5a and 6 are layouts for realizing FIGS. 4b and 4c using a silicon gate process. Figure 5b is A, A' in Figure 5a.
FIG.

In the figure, a storage capacitor forming electrode cp made of polysilicon
is for forming the storage capacitance Co in the memory cell as shown in FIG.

400 and 410 are drains and sources (or sources and drains) formed in the silicon substrate 600 to form the transistor Q; 420 corresponds to 410;
This is a drain (or source) for forming Co.

The storage capacitor forming electrode Cp and the word line W, W59, etc. are formed of polysilicon, and the data line D, etc. are formed of aluminum. Data line ○, etc. and word line W5
9 etc. are separated by an insulating film 200. 100 is a contact portion between the data lines Do, Do, etc. and the diffusion layer 400.

In N-channel MOS, the storage capacity Co is formed by cp
When a high voltage is applied to C, a capacitance C is formed between the channel and cp.

becomes. To briefly explain the operation using FIG. 5, when a pulse voltage is applied to the word line, for example, W6o, the transistor Q (corresponding to Q in MCo in FIG. 1) turns on, and C
The storage voltage of o is divided by the capacitance of data line Do and Co, and a voltage appears on Do. On the other hand, since the transistor Q does not exist on the data line Do paired with this, no output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. As is clear from FIG. 5, the distance between the diffusion layers of the contact portions Do and D can be increased due to the presence of the AI wiring in the middle. Therefore, there is an advantage that punch-through between Do and D can be avoided. Another advantage of the circuit shown in FIG. 3 is that the layout to the preamplifier P is easier than in the past. In other words, in the conventional figures 1 and 2,
PAo, which occupies a much larger area than the memory cell and has a complicated circuit configuration, must be laid out between Do and Do, which are laid out in a straight line with each other.
This was extremely difficult considering the pitch of the data lines. However, in FIG. 3, there is an area margin approximately twice as large as that of the conventional layout in the data line pitch direction, making the layout extremely easy. Also, the preamplifier PAo may be placed on the MA side as shown in Figure 3, or
Alternatively, it may be at the pond edge (W63 side) above Do, Do.

By arranging P on the W63 side, control circuits whose layout is relatively difficult (PAo, Qo, etc.) are not concentrated only at one end, as shown in FIG. Depending on the case, preamplifiers may be arranged alternately on the MA side and the W63 side on the data line. In this way, according to the present invention, the degree of freedom in layout can be greatly increased. In addition, although the word lines in FIGS. It can be laid out, and it is also the same machine in the case of an AI gate.

Also, in this example, one bit is configured with one transistor, but in order to extract signals differentially from the data pairs, a memory cell is connected only to one of the two intersections with the word line, and It is clear that all memories can be applied to 1 by applying the concept shown in FIGS. 3 and 4 using dummy cells.

In FIG. 3, CD and CD are common data lines for writing and outputting data. From the above, it is possible to realize memory with high speed and high stability operation.

[Brief Description of the Drawings] Figures 1 and 2 show a conventional memory configuration in which one bit is configured with one transistor, and Figure 3 shows an implementation of the present invention in which a read signal is output from only one side of a pair of data lines. For example, FIG. 4 shows a memory cell connection method, and FIGS. 5 and 6 show an example of a layout using a Si gate. Do, Do, D,: data line, Wo・”W62: word line, DWo, DW,: word line of dummy cell, MC., MC,: memory cell, DMo, DM,: dummy cell,
Co: storage capacity, Q: transistor in memory cell, W
D: Word driver, Q〇,Q. ~Q63: Data line selection transistor, Ao~3: Address signal, to P~
Pn3: Preamplifier, MA: Main amplifier, Set: Set signal, CP: Co forming electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A capacitor comprising an electrode formed on a surface region of a semiconductor substrate through an insulating film and integrally connected at least in the row direction and the surface of the semiconductor substrate below the electrode, and a transistor coupled to the capacitor. A semiconductor memory comprising a plurality of memory cells arranged in rows and columns, the data lines of the memory cells running in the column direction, and the data lines overlapping the electrodes via an insulator. A pair of data lines D_0,
A semiconductor memory characterized by being coupled to an amplifier PA_0.