JPS6011395B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a memory array in a semiconductor memory device.

Conventional memory consists of one bit with one transistor,
For example, M○S (Metal-○ illusion deichi Semic-
In the memory, circuits such as those shown in FIGS. 1 and 2 were used.

That is, in FIG. 1, for example, when reading a memory cell MCo, a pulse is simultaneously applied to a word line Wo and a dummy word line DW belonging to another data line Do, and read signals from memory cells MCo and DM. The minute differential signal output appearing on the two data lines Do and Do is connected to the set signal Set of the preamplifier PAo.
By turning on the preamplifier P, the preamplifier P is activated and amplified, and the voltage appearing on either the Do or Do data line is detected to discriminate between information "1" and "0". The reason why differential signal output is generated here is as follows. The voltage stored in the capacitor Co of the dummy cell DM is equal to the information “1” and “0” stored in the memory cell Co.
”, the voltage that appears on the data line after reading the dummy cell is approximately halfway between the data line voltage when reading “1” and “0” from the memory cell. The difference between the intermediate value and the "1" and "0" outputs becomes a differential signal output with different polarity.

Figure 2 shows a plurality of circuits shown in Figure 1 (for example, 6 here).
4) It is a diagram schematically showing a circuit in consideration of the geometric arrangement when a BI memory is configured by being mounted in a BI chip.

In the figure, white circles are memory cells, and bad circles are dummy cells.
For example, in order to take out the signal appearing on the data line Do as described above, the transistor Qo is turned on by the address signal Ao, and the signal on the data line Do is input to the main amplifier MA and amplified. It is taken out from the chip as the data output Do pile. Now, the drawbacks of such a configuration can be summarized as follows. In other words, ■Data lines Do, D
Main amplifier M outputs only one side of the differential signal appearing at
Since it is amplified by A, it is inferior in terms of high speed. ■Since one signal is taken out, electrical imbalance between Do and Do is likely to occur, causing malfunction.

■The data lines Do, Do whose electrical characteristics should be balanced are
D due to lack of geometrical proximity within the chip. ,Do
unbalanced noise is likely to couple with the preamplifier, causing malfunction when the preamplifier is turned on. Due to these drawbacks, there are limits to the design of high-speed, highly stable LSI memory. One object of the present invention is to provide a memory element layout method that allows high integration. To this end, one embodiment of the present invention makes the drain regions of the access transistors belonging to adjacent word lines a common diffusion region among the access transistors constituting the memory cells of the dynamic random access memory. It is something.

This will be explained in detail in Examples below. FIG. 3 shows an example of the circuit.

That is, the data line pair Do, where differential read signals appear,
Do are arranged close to each other in parallel as shown in the figure, and one each of word lines Wo to W, DWo, DW, and D. ,D
. A memory cell is connected to only one of the intersections. When reading a certain memory cell (for example, MC line), a dummy cell DM is connected to a data line Do to which that cell is not connected. are simultaneously read out, and the differential voltage appearing on the data lines ○o and Do is effectively used by the preamplifier PAo. Further, the differential signal amplified by the preamplifier P passes through the transistors Qo and Qo by applying the address signal Ao, which is the output of the decoder, to the differential amplifier M.
A and is amplified differentially again. As described above, in the present invention, the electrical balance between Do and Do is not disturbed in any way as compared to the case of FIG. Figure 4 shows Do,
FIG. 2 is a schematic diagram of a method of connecting memory cells (8 bits) while maintaining electrical balance of Do. In the figure, a, b, and c are Do
, Do are connected to every other memory cell, every second memory cell, and every fourth memory cell, respectively. 5A and 6 are layout examples for realizing FIGS. 4B and 4C using a silicon gate process. FIG. 5b is a cross-sectional view of section AA' in FIG. 5a.

In the figure, a storage capacitor forming electrode cp made of polysilicon
is for forming the storage capacitance Co in the memory cell as shown in FIG. 400, 41 are formed in the silicon substrate 600 and are the drain and source (or source and drain) for forming the transistor Q.
20 corresponds to 41 and is a drain (or source) for forming Co.

The storage capacitor forming electrode Cp and the word line W, W59, etc. are formed of polysilicon, and the data line D, etc. are formed of aluminum. Data line D, etc. and word line W5
9 and the like are separated from the insulating film 2001. 1001
It is also a contact portion between the data lines Do, Do, etc. and the diffusion layer 400.

In N-channel MOS, the storage capacity Co is formed by cp
When a high voltage is applied to , the capacitance between the channel formed directly below and CP becomes Co.

To briefly explain the operation using FIG. 5, when a pulse voltage is applied to the word line, for example, W6o, the transistor Q (
(corresponding to Q in MCo in Figure 1) is turned on, and the memory voltage of Co is divided by the capacitance of data line Do and Co.
A voltage will appear. On the other hand, since the transistor Q does not exist on the data line Do paired with this, no output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. As is clear from FIG. 5, the distance between the diffusion layers of the contact portions Do and D can be increased due to the presence of the AI wiring in the middle. Therefore, Do, D. It also has the advantage of avoiding punch-throughs in between. Another advantage of FIG. 3 is that the layout for the preamplifier P is easier than in the past. In other words, in the conventional Figures 1 and 2, PAo, which occupies a much larger area than the memory cell and has a more complex circuit configuration, must be laid out between Do and Do, which are laid out in a straight line with each other. First, considering the pitch of the data lines, this was extremely difficult, but in Figure 3, there is almost twice as much space in the layout as in the conventional layout in the direction of the data line pitch.
Layout becomes extremely easy. Also preamplifier PA
o may be placed on the MA side as shown in FIG. 3, or on the pond edge (W63 side) above Do, Do.

By arranging P on the W63 side, control circuits whose layout is relatively difficult (PAo, Qo, etc.) are not concentrated at one end as shown in FIG. 3. In some cases, preamplifiers may be alternately arranged on the MA side and W63 on the data line. As described above, according to the present invention, the degree of freedom in layout can be greatly increased. Furthermore, in FIGS. 5 and 6, the word line is made of poly-Si, but the word line is made of AI.
A similar layout is possible in the case of , and the same is true in the case of an AI gate.

Also, in this example, one bit is configured with one transistor, but in order to extract signals differentially from the data pair lines, a memory cell is connected only to one of the two intersections with the word line, and It is clear that all memories can be applied to 1 by applying the concept shown in FIGS. 3 and 4 using dummy cells.

In FIG. 3, CD and CD are common data lines for writing and outputting data. From the above, a memory with high speed and highly stable operation can be realized.

[Brief explanation of the drawing]

Figures 1 and 2 show a conventional memory configuration in which one bit is configured with one transistor, Figure 3 shows an embodiment of the present invention in which a read signal is output from only one side of a pair of data lines, and Figure 4 shows a memory configuration. 5 and 6 show an example of a layout using a Si gate as an example. Do, Do, D. ...Data line, Wo...
W Already... Word line, DWo, DW. ...Dummy cell word line, MCo, MC. ...memory cell,
DMo, DM, dummy cell, Co...
Storage capacity, transistor in Q memory cell, WD...word driver, Qo, Q~Q mother...transistor for data line selection, Ao~3...address signal, PAo~PA63... ...Preamp, MA...
Main amplifier, Set...Set signal, CP...
・Electrode for Co formation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A memory cell including a FET, in which a data line corresponding to one column and a data line corresponding to a column adjacent to the column are coupled as a set to an input terminal of a differential sense amplifier. 1. A semiconductor memory in which a plurality of semiconductor memories are arranged in rows and columns, and the drains or sources of FETs of memory cells belonging to the same data line and adjacent word lines are common.