JPS6019710B2 - Video signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for generating pulses with non-linear timing relationships and to a system for generating special effects such as wipes and dissolves using such pulse trains.

For example, a dissolve is an on-screen effect that combines two video input signals in such a way that the levels of the two input videos are changed differentially, and one of the two input videos is in the form of a black burst. When the other signal is used as an image signal, it is called a fade.

Also, the technique of combining two video signals in such a way that a part of the image related to one video signal is gradually switched to an image related to the other video signal on the television screen is called a wipe. An effect that is stopped in this intermediate state is called a key. The system for generating such special effects includes two circuit devices: a dissolve (fade) circuit and a wipe (key) circuit.

The dissolve circuit device has a variable gain amplifier that differentially mixes the level of the received video input, and the gain of this amplifier is controlled according to the DC level change signal. There is. The slope of the level change determines the mixing ratio of the two input videos, such that at the beginning of the slope only one video is output, and at the end of the slope only the other video is output. The wave circuit arrangement includes a wave switcher controlled by switching pulses having a frequency related to the horizontal and/or vertical scanning speed. The specification of Patent Application No. 52-59306 (see Samurai Kaishokyu-14462), which was filed at the same time as this application, discloses a technique for obtaining such switching pulses by using X and Y counters. ing. For example, an 8-bit × counter is subcarrier 3. A clock with a frequency that is 4'3 times the MHZ is counted, and the 8-bit Y counter is also half-etched.
Count rejected horizontal sync pulses. The wave speed is controlled by the output from the speed counter. In such a configuration, it is often desired to change the dissolve and wipe speeds nonlinearly.

It is therefore an object of the present invention to provide a non-linear array of pulse trains that can be used for non-linear changes in dissolve and wipe speeds.

Such pulse trains have a variety of applications in addition to their use in television special effects generators. Figure 1 shows
1 shows a circuit for generating a geometric pulse train, for example by using a 4-bit counter and a 4-bit shift register; Counter 12 receives equally spaced clock pulses at terminal 10 at a clock input (CK). The clock at terminal 10 is applied via inverter 14 to a count enable input terminal (ET). The carry output of the counter 12 is given from the terminal (Co) to the output terminal 16 and the clock input (CK) of the shift register 18, and is also passed through the inverter 20 to the load input (CK) of the counter 12.
LD) and one input of the NAND circuit 22. Data inputs A, B, C, and D of counter 12 receive outputs 4, 3, 2, and 1 of shift register 18, respectively, and these shift register outputs are input to AND gate 24. The AND gate output is given to the other input of the NAND gate 22, and this output is given to the input terminal (m) and clear terminal (CL) of the shift register 18. The counter 2 outputs a carry signal in response to the first pulse received, and this pulse passing through the inverter 20 places the counter 2 in a load state.

The carry output that has passed through the inverter 20 is also NAN
The data input is applied through the D gate 22, and the carry output is applied directly to the clock input, resulting in a 1 output from the shift register, which is applied to the ◯(8) input of the counter. Therefore, the count is preset to 8, and then counting the 8th pulse produces a carry output, which causes the 1 and 2 outputs from the shift register and the C(4) and D(8) of the counter. Load the input, which presets the counter to 12. Therefore, a carry occurs on the next fourth clock, which presets the counter to 14 so that a carry occurs when the next two pulses are received. This carry presets the counter to 15, so there will be a carry on the next pulse. This signal "1" sets the NAND gate output to 0, thereby clearing the shift register. Therefore, since no preset data input is given to the counter, it outputs a carry signal in the form of a pulse on the next first tick.
In FIG. 2, a shows the clock applied to the terminal 10, and b shows the geometric pulse train output from the output terminal 16. for example,
By cascading two 4-bit counters into an 8-bit counter and using an 8-bit shift register, an expanded geometric pulse train can be obtained. FIG. 3 shows 4-bit counters 100 and 1
This is a circuit for obtaining pulse trains of other nonlinear arrays such as arithmetic pulse trains using the 02.

Input terminal 106 receives equally spaced clock pulses. The first counter 100 receives this pulse (CK
) input and a (Co) output that outputs the carry signal. This (Co) output is applied to the output terminal 110 and the count enable input (ET) of the second counter 102, and is passed through the inverter 104 to the first counter 1.
00 load input (LO) and the second counter clock input (CK). The Q^, QB, Qc and Qo data outputs of the second counter 102 are provided to the A, 8, C and O data inputs of the first counter. The clear inputs of these counters are grounded via switch 108. Initially, it is assumed that there is no output from the second counter, and the first counter 100 outputs a carry in response to the received pulse of the first mother fin.

This produces an output pulse at output terminal 1101, which loads the first counter via inverter 104 and provides (16) clock pulses to second counter 102. This provides data to preset 1 from the output of the second counter to the data input of the first counter. Therefore, when the next first clock is received, a carry occurs. This carry is given as an output to the terminal 110, and the counter 1
Preset 00 to 2. Therefore, when it receives the 14th pulse next, it outputs a carry. In this way, the first counter is preset to 15, resulting in an arithmetic pulse train as shown in FIG. 4. In FIG. 4, a indicates the input clock pulse at terminal 106, and b indicates the output pulse train at terminal 110. As is clear from this exemplary configuration, by using a combination of two n-bit counters, the difference between adjacent pulse periods is constant (tolerance > 0).
A pulse train consisting of pulses can be generated. Such a non-linear array of pulse trains can be applied in digital circuitry to create dissolve control ramp waveforms and wipe control switching pulses.

Tokukan Sho 52-59305 (Tokukan Sho 5) filed on the same date.
No. 3-144621) discloses a digital circuit configuration for controlling the duration of dissolve.

FIG. 5 shows such a circuit configuration in which the nonlinear pulse train generating means of the present invention is incorporated. For example, a pulse fv synchronized with a frame pulse is applied to a terminal 2001, and this is output as 25 v by a PLL circuit comprising a phase comparator 202, a VC0204, and a feedback path 206. This 25 wipe v output is input to a programmable counter 208. This divides the input signal by the duration data n given to the terminal 2101. This output is converted by the nonlinear pulse generation circuit 212 into a pulse train with a nonlinear arrangement. As this circuit 212, the above-mentioned difference ratio pulse generation means and arithmetic pulse generation means can be used. Its output is provided as the clock count input of an 8-bit counter 214, and the counter output is provided to an 8-bit D/A converter 216. The converter output is produced via a programmable multiplier 218 at output terminal 22. Therefore, a dissolve control DC analog signal whose slope is nonlinearly changed according to the set duration is outputted to the output terminal. FIG. 6 shows a digital circuit scheme for obtaining a speed counter output for controlling wipe speed.

This kind of circuit system is described in the patent application filed on the same day in 1982-1985.
No. 306 (see Tokusekki No. 53-144622). Speed counter 304 receives clock pulses from clock pulse generator 300 via nonlinear pulse generator 302 and outputs wipe speed control data at output terminal 306. Pulses from oscillator 300 are sent to circuit 30
2 into a non-linear array of pulses, the wipe speed can be varied non-linearly with time. Key size data is provided to counter 304 from terminal 308 . As this circuit 302, the nonlinear pulse train generating circuit shown in FIGS. 1 and 3 described above can be used. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a geometric pulse train generation circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a diagram of the present invention. FIG. 4 is a waveform diagram for explaining the operation of the circuit in FIG. 3, and FIGS. 5 and 6 are diagrams showing the circuits in FIGS. FIG. 2 is a block diagram of a circuit incorporated in a control signal generation circuit and a wipe speed control signal generation circuit.

In the figure, 12, 100, 102 are 4-bit counters, 1
8 is a 4-bit shift register, and 212 and 302 are nonlinear pulse generation circuits.

Figure 1 Figure 2 figure Mountain vertical Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] 1. In a video signal processing method that performs a dissolve or wipe operation of a video signal, a clock signal generation circuit, a clock signal from this circuit is supplied, a circuit that arranges a pulse train of this clock signal in a non-linear array, and a circuit that generates a pulse train of this clock signal in a non-linear array, and a control signal generation circuit that is supplied to the circuit and controls the dissolve or wipe operation, and the speed of the dissolve or wipe operation is made non-linear by the control signal.