JPS6044865B2 - Signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to signal processing systems, and more particularly to systems for generating special effects for television images.

Such special effects generators are characterized by the combined processing of multiple video input signals to obtain a single video output signal.

Depending on the form of the input video signals provided and the form of their combined processing, output video signals with various special effects are provided. For example, a dissolve or fade effect can be created by combining two different video input signals with differentially varying levels. Also, by combining two video signals in such a way that a portion of the television image provided by one video signal is inserted or replaced by a portion of the television image provided by the other video signal. Wipe or key effects can be generated. Conventionally, when performing a dissolve operation, a dissolve period is determined and the input video signal is switched using a ramp waveform that changes linearly during that period.

However, in such a conventional device, a portion where the level change is small becomes a dead zone where movement cannot be confused when viewed with the naked eye, and the dissolve period is visually shortened. It is an object of the present invention to provide a dissolve waveform that solves the problem of nine colors as described above and allows visual changes to match actual operations.

FIG. 1 is a block diagram of a signal system of a special effect generation system incorporating the present invention. The signal system 10 has two input terminals 12,
14 and an output terminal 16. Input terminal 12, 1
4 are each provided with a video signal to be processed. Signal system 10 includes a wipe and key switcher circuit 18 and a dissolve switcher circuit 20. 1st
The second switch 18 receives the wipe and key switching pulses applied to the terminal 22 and the second switch 20
receives a lamp control signal applied to terminal 24. Switcher 18 has first and second terminals provided at terminals 12, 14.
, and fixed contact 1 of J switch 28
It has an output connected to. Fixed contact 1 of switch 26
is connected to the terminal 12, and the fixed contact 2 is grounded. Fixed contact 2 of switch 28 is connected to input terminal 14 .
The signals of the movable contacts of the switches 26, 28 are provided as inputs to a dissolver switch 20, the output of which is applied to the fixed contact 1 of the switch 30. The movable contact of the switch 28 is connected to the fixed contact 2 of the switch 30. A movable contact of switch 30 is connected to output terminal 16 . By setting switch 26 to position 2, switch 28 to position 1, and switch 30 to position 2, an output from switch 18 is produced at the output terminal.

This sets the wipe (key) mode. switch 26
By setting switch 28 to position 1, switch 28 to position 2, and switch 30 to position 1, an output from switch 20 is produced at output terminal 16. This sets dissolve (fade) mode. In addition, by selectively operating these switches, you can select the key. In (out), key. With. Fade. In (out) image formation can be performed.

Figure 2A is the key. This is an example of an in/out screen and a chart. First, from the state a with only the A image, it is dissolved to become the A + B image part as shown in b, and finally the A
The key state c of the image and B image is obtained. The key technique in Figure 2A is to proceed with image formation from left to right. On the other hand, the key is the technique of forming images from right to left. called out. To do this with the signal system 10 in FIG. 1, a video signal representing image A is input to the input terminal 12, and
4, a video signal representing a B image is input. Switcher 18 is operated to produce a video signal providing a screen of c. The first and second switches 26, 28 are
1 position and therefore dissolve. The switcher 20 is supplied with signals corresponding to screens a and c, respectively. This switcher 20 outputs the two-way signal so that the video signal giving the B screen is output to the output terminal 16 via the switch 30 in the 1 position! Dissolve. If dissolve. If the polarity of the control signal to the switcher 20 (given to the terminal 24) changes, a screen in which image portion A and image portion A+B are switched will be formed on screen b.
- Figure 2B shows the switch 26 of the signal system 10 in Figure 1,
key by operating 28 and 30. With. This shows how to create a fade (in, out) screen. First, a combination image 4 of images A and B gradually appears from screen a in a black state as shown in screen b, and finally a combination image 4 of images A and B appears as shown in screen c. Become. In this way, the combined image of image A and image B is faded in the order of A, b, and c. The key is to use techniques such as "in". With. Fade. This is called in, and conversely, the technique of changing from the key state of screen C to screen B and then black screen C is the key. With. Fade. Call it out. Such an effect on the television screen can be achieved by setting the first switch 26 to position 2 and the second switch 28 to position 1, dissolving. This is achieved by dissolving using the switcher 20. That is, dissolve. The switch includes black video via the first switch 26 and wipe and key video via the switch 28.
The output of switcher 18 is provided. FIG. 3 is an example of a specific circuit that achieves the function of the block of the signal system 10 shown in FIG.

Transistors Q1 and Q2 serve to provide a buffer function for the video signal input at terminal 12, and transistors Q3 and Q4 serve to provide a buffer function for the video signal input at terminal 14. Transistor Q89Q79Q
l69Ql79Ql8 and Ql9 are wipe and key. A switcher 18 is configured. Transistor Q99QlO9
Qll9Ql29Ql3 and Ql4) Desol Bu.
A switcher 20 is configured. Other transistors Q5, Q
8 and Ql5 work for voltage balance or impedance conversion. Figure 4 shows the wipe and key shown in Figure 1. Key and wipe at terminal 22 provided to switcher 18. A circuit for generating switching pulses is shown.

This wipe (key) generator 32 is connected to the X1 counter 34,
2 counter 36, Y1 counter 38, Y2 counter 40
and a speed counter 42. X1 and X2 counters 34 and 36 receive a clock signal Fx obtained by multiplying the subcarrier frequency (3.58 MHz) applied to terminal 44 by 4 and counting down to 113.

The load inputs of these counters 34, 36 receive a signal `` applied to terminal 46. This signal 5 consists of narrow pulses made from a half-etched horizontal sync signal. 40
receives the signal at input terminal 48 at their clock input,
It also receives the signal VBP at the input terminal 50 at the load input.
Signal FY is half. Etsuchi. The signal VBP is a rejected horizontal synchronization signal, and the signal VBP is a vertical blanking signal. It's a pulse. Speed counter 42 receives at its clock input a speed pulse SP which determines the wipe speed of terminal 52.
These counters 34, 36, 38, 40 and 42 are 8 bits in this embodiment. Consists of a counter.

Therefore, a carry signal is output at the count position of 256. These counters have data input terminals for receiving 8-bit data, and Y counters 38, 40 and speed counters have 8-bit data output terminals. These counters can be preset to any counting state by applying the data to be preset to the data input terminal and applying a load input terminal, such as a logic 0 load signal. As described later, the X1 counter 34 and Y1
The system of counters 38 can operate complementary to the system of X2 counters 36 and Y2 counters 40.

Therefore, to simplify the explanation, we will first discuss the Xl, Yl counter series, and then explain the Xl, Yl counter series, which has the same operating principle.
2, the relationship with the Y2 counter series will be described. NTS
According to the C standard, one frame of a video signal consists of 52 unit video lines, and one video line has one horizontal synchronization pulse.

Therefore, one field consists of 262.5 lines. Now, the speed counter 42, which will be described later, is in a cleared state, and the 8-bit . Assume that the data input is at 0. The vertical blacking pulse VBP applied to the terminal 50 actually has a waveform as shown in FIG. 5a, assuming that the time length of one video line is H. , the first light hour is logical 0 (mouth), the subsequent light hours are 253.5
H can be a logic one (high). The second waveform is Y
When applied to the load input of the 1 counter 38, the counting of the signal FY at the terminal 48 starts from the point at which it becomes logic 1. Therefore, if we consider the actual vertical blanking signal in Figure 5a as a load signal with a logic 0 period of 8.5H as shown in Figure 5b, the carry output of the Y1 counter will be the next vertical blanking pulse. occurs at the beginning of In this state, when 46r' is preset from the data input of the Y1 counter by the speed counter, a carry occurs at the last position of the blanking pulse, as shown in FIG. If you load , the camera will move from the end of the blanking pulse to the front.

Generally, if "n" (0≦n≦255) is set, the carry signal will be output ml before the end of the blanking pulse.
The clock signal is applied to the flip-flop 54 as a clock signal.

This D flip-flop 54 receives the BP signal at terminal 50 as a clear input. FIGS. 6A, b and c show the P signal, the carry signal and the D flip-flop 54 generated when the data 64n'' are preset, respectively.
shows the Q output of Waveform c provides the Y1 switching signal. When such a Y1 switching signal is applied as a wipe (key) switching pulse to the terminal 22 in FIGS. 1 and 3 via the control circuit 56, the soft edge circuit 58, and the output terminal 60, the signal on the actual television screen, e.g. As shown in FIG. 7, when the Y1 switching signal is in the 0 (one) logic state, the A screen is selected, and when the Y1 switching signal is in the high (1) logic state, the B screen is selected. If the input data value ゜゜n゛ is made to increase gradually in each vertical blanking period, the B screen will gradually expand as indicated by the arrow, and finally it will be completely just the B screen. On the other hand, if, conversely, the Y1 counter is preset so that "n" gradually decreases with each vertical blanking period, then
The A screen expands downward, and in the end, only the A screen remains. If the preset data from the speed counter 42 is fixed, a key status screen can be obtained. Next,
The operation of the 1 counter 34 will be explained. X1 counter 34 is adapted to receive an 8-bit data input from exclusive 0R gate 62, which will be described below. In the figure, gate 6
2 shows one of them, but is it actually eight exclusives corresponding to the number of data? A ρR gate is provided. One input of gate 62 is connected to a movable contact of switch 64. The first fixed contact is connected to the 8-bit output of a latch circuit 66, which will be described later, and the second fixed contact is connected to the 8-bit output of the Y1 counter 38. Connected to data output. now,
It is assumed that the input data from the speed counter 42 is "0" and the switch 64 is in position 1.

As described above, the subcarrier 3.58 MHz×413 signal is selected as the clock input of the X1 counter 34. This means that if the subcarrier 3.58MHz counts for 1H time period, it will be 227, and the number of pulses will be insufficient for the 8-bit counter to output a carrier, so 3.58MHz will be counted.
When ×413 is used as a clock, 303.
In order to count 25 pulses, the width of the load pulse of the X1 counter should be approximately 10 μs, which is exactly equivalent to the H blanking pulse. This is because it is possible. For the above reasons, the input terminal 46 is used as a load input for the X1 counter. Etsuchi. A narrow pulse '' (Figure 8a) made from the rejected H sync signal is applied. This pulse has a duration of one logic level of about 10 ps. This is the equivalent time to a 49.brass pulse in FX (Figure 8b).Therefore, the duration of the other logic level of the signal is 254.
corresponds to the duration of pulses. In this way, as previously described in connection with the Y1 counter, the X1 counter 3
It becomes possible to obtain pulses of various timings (FIG. 8c) according to the preset value given to the data input of 4. This timing signal is provided as a clock input to D flip-flop 68. This flip-flop has a clear input supplied with the signal ``at the terminal 46. Therefore, an X1 switching pulse as shown in FIG. 8d is generated at its output Q.
, soft edge circuit 58 and terminal 60 to terminal 22 of FIGS. 1 and 3. When given as a switching pulse, for example, if a switcher 18 is used that sends an A image between low levels and a B image between high levels of the X switching pulse, the actual television screen will be as shown in FIG. Yo. Regarding the continuous H blanking pulse, as ゜“n゛ gradually increases, B
The image gradually increases in size to the left until it is completely reduced to just the B image. Conversely, as ゜4n0 gradually decreases, image A expands to the right, and finally becomes completely... A
It becomes just an image. If the data input value to the X1 counter is fixed, a key state is set in which the A screen and B screen do not change. The above is a case where the switch 64 in FIG. 4 is in the 1 position.

If switch 64 is in position 2, the 8-bit data input of X1 counter 34 is provided by the 8-bit data output of Y1 counter 38. Now, assuming that the output of the speed counter 42 is ゛O゛, the 8-bit data of the output of the Y1 counter 38 is preset in the X1 counter 38 during each H time period. Since the Y1 counter counts the horizontal sync FY pulses at the terminal 48 after being preset at "0" until the next preset at "40", the output data of the Y1 counter for every H time period is from 46099 to 6419996629Z. 66n999. a25599
becomes. This output data presets the X1 counter with a horizontal synchronous speed load pulse, and from that value the counter is counted up using the FX clock pulse at terminal 44. Therefore, the output of the X1 counter is a pulse every time the Y1 counter counts up. Shift each one to the left. Therefore, since the output data of the Y1 counter is O at the top of the screen, the balance of the X1 counter is
During the H blanking period, when the Y1 counter output data is "゛1", the X1 counter's carry output will appear at the top right of the screen, and in this way, the Y1 counter output data will appear at the top right of the screen.
When the counter counts 254H, the key of the X1 counter will appear at the bottom left of the screen. These X1
When the D flip-flop 68 is set as described above with the counter carry and the "clear pulse" is set, the Next, if we consider the case where the speed counter 42 is counting up at a certain speed, the output of the Y1 counter is offset by the output data of the speed counter, and the 6'0'' output data of the Y1 counter is The position will have shifted.

Therefore, the speed counter is 44099966r99.44
n99. ．． 6425599 and Kauntap or 662
559Z. 66r199. ．． 66r996609, the TV 7 screen in FIG. 10 flows upwards, and as shown in FIG. A roughly rectangular cut-out window similar to a television screen is placed above the paper, and when the paper is moved upwards, a composite screen similar to the scene seen through the window is formed. The 8-bit speed counter 42 receives the wipe speed pulse (SP) at terminal 52 as a clock input and also receives the key. size. Receive data through data input.

When switch 72 is turned on and the load input of the counter is grounded, the counter will be connected to the key. size. Preset with data, device 32 changes from wipe generator mode to key generator mode. The data output of speed counter 48 is provided to exclusive 0R gate 74.

Although only one gate 74 is shown in the drawing (FIG. 4), there are actually as many gates as there are output data bits of the speed counter 42. This gate 74 is the control input terminal 7
4''. As is well known, by selectively changing the control logic input state applied to this control input terminal to high or low, the speed counter 42 can be made to function as an up counter and a down counter, respectively. For example, in wipe mode in a composite television screen consisting of A screen and B screen as shown in FIG. 12, by changing the control input of the exclusive ?R gate circuit, 78 can be selectively wiped.The exclusive ρR gate circuit 62 also has a similar control input terminal 62'.

This gate circuit 62 includes the exclusive 0R gate 74 described above.
controls the overall operation of wipe generator 32, whereas it merely determines the input data conditions of the X1 counter. The logic control signal at the terminal 62'' performs control according to the determination of the wipe pattern and the key pattern. The wipe (key) generator 32 includes a Y2 counter 40, an X1 counter 34, and a X2 counter 36 with similar configuration, exclusive 0R gate 6
Exclusive with the same configuration as 2. 0R gate 84, switch 6
4, a D flip-flop 80 having a similar configuration to the D flip-flop 54 receiving the carry output of the Y2 counter 40, and a D flip-flop 68 receiving the carry output of the X2 counter 36.

It has a D flip-flop 82 having a similar configuration. On the other hand, the 8-bit data output of the exclusive bacteria ρR gate 74 is Y1
The signal is applied directly to the counter, but is applied to the Y2 counter 40 via an inverter 84. This inverter has a Y1 counter 38 and a Y2 counter 4.
It is designed to work complementary to 0. That is, Y1
When a Y switching pulse is created using the Y2 and Y2 switching pulses, as shown in Fig. 13A and b, an image in which the upper and lower two B images are wiped toward the intermediate A image, or an image in which the upper and lower two A images are An image in which the B image sandwiched between the two images wipes in the direction of each A image is obtained.
Similarly, set switches 64 and 86 to position 1 to further exclude? ρ
When the logic control inputs of R gates 62 and 84 are conditioned to opposite logic states, X1 and
Synthesis of switching pulse The switching pulse wipes the two left and right B images in the direction of the intermediate A image, or wipes the B image sandwiched between the left and right two A images in the direction of both A images. Give an image like that.
Next, set switches 64 and 86 to position 2 and
, Yl and X2, Y2, it is possible to provide a wiped image of the A image and the B image as shown in FIG. 15A, b, c, and d6. Besides, exclusive 0R gate 64,7
4 and 84 to control switches 64 and 86, as well as switching pulses Xl, X2.
, Yl, and Y2, the 15th''
It allows for patterns that provide various wipe image effects as illustrated in the figure.

In FIG. 4, a latch circuit 6 receives the 8-bit output data of the speed counter 42 via an exclusive bit ρR gate 74.
6.

This latch also connects the clock input to receive the vertical blanking pulse at terminal 50 and the 8-bit output data to switch 6.
4 and 86 position contacts and respective gates 62 and 8
4 to the data inputs of the X1 counter 34 and the X2 counter 36. The X1 and X2 counters load input data with horizontal synchronous speed load pulses. If this latch circuit were not present,
Since the X1 and X2 counters will be loaded with the data output of the speed counter as is, the data of the speed counter must be updated at a location in the image other than vertical blanking, except when counting frame pulses or field pulses. become. For this purpose, as shown in Figure 16a, 2
The boundary lines between the two images A and B are not straight lines, but are at different levels. To prevent this on-screen effect,
Once the speed counter data is vertically synchronized speed pulse BP
Latch with and hold this for one feed. Therefore, since the held data is used as preset data for the X1 and X2 counters, the step-like effect shown in FIG. 16a disappears, and a straight boundary line as shown in FIG. 16b is obtained. In the figure, 90 indicates the boundary line of the first field, and 92 indicates the boundary line of the next field. The shorter the duration setting is, the more rough the wipe will be, and the distance between the boundary lines 90 and 92 will be larger; however, the speed of the wipe itself is quite fast and does not pose a visual problem.
As for the Y1 and Y2 counters, there is no need for latches as described above since these are loaded with the speed counter output data on the VBP signal at the vertically synchronized speed. Control circuit 56 receives the X1 switching pulse from flip-flop 68, the Y1 switching pulse from flip-flop 54, the X2 switching pulse from flip-flop 82, and the Y2 switching pulse from flip-flop 80.

This circuit 56 consists of a combination of various gates and outputs a composite switching pulse in response to the control logic signal Sc. Soft edge circuit 58 receives switching pulses from control circuit 56.

The composite switching pulse from the control circuit 56 is the 17th
As shown in Figure a, for example, the two images A in Figure 17b,
It has a sharp, hard edge that clearly switches B. On the other hand, if the switching pulse has a slope for only a certain period as shown in Fig. 17c, and the A and B image signals are mixed up by changing the analog distribution ratio during this period, the result will be as shown in Fig. 17d. The edges of the image appear softer, which is visually pleasing. In order to multiply the A image signal and the B image signal in an analog manner in order to obtain such a boundary screen A+B, the configuration becomes complicated and the cost becomes high. Therefore, in order to provide a similar effect, a soft edge circuit 58 is provided, and the switching signal is digitally processed. That is, as shown in FIG. 18, at the A+B boundary of the television screen (FIG. 18a), the switching pulse in FIG.・The ratio is changed.
The duty ratio is small at the boundary A+B near image A, and as it approaches image B, the duty ratio is continuously changed so that it becomes large. Therefore, due to the visual integral effect of such a switching pulse screen,
It becomes possible to obtain a screen having a soft switching section similar to the analog distribution method described above. Since a soft edge effect can be achieved through digital processing of the switching signal, the linearity of the boundary A+B is improved. Not only the above-described soft edging in the line direction, but also the edging in the vertical direction can be performed in the same manner as described above. FIG. 19a shows a soft edge of the boundary part A+B between the upper and lower images A and B, and the part A+B includes ml lines. On the line closer to the upper image A, switching is performed using a pulse with a small duty ratio, as shown in FIG. 19b, and on the n-th and final line, switching is performed using a pulse with a maximum duty ratio. In this way, the A+B boundary portion, which is a soft edge, is provided by temporally changing the distribution of the signals of A<5B on each line. A part of a specific example of such a soft edge circuit 58 is the second
It is shown in Figure 0.

This circuit consists of two 4-bit counters 100, 102
and an inverter 104. As such, the Texas Instruments SM74l6l integrated circuit can be used as the counter. The clock input of first counter 100 receives a clock signal FC applied to input terminal 106. If the switch 108 is off and the clear input is not applied, the counter 100 counts the 0th to 1st clock pulses and outputs a zero output. This signal is inverted by an inverter 104 and applied to a second counter 102', and is also applied to a first counter 100'.
Also given to the load input. When the load input becomes low level, the first counter A, B, C, D
The inputs are QA, QB, Qc and Q of the second counter. Preset by output. Upon input of the first carry pulse, the second counter outputs a value of 0, and the first counter is preset by this value of 0. The next output will be preset by the value of “゜1゛,”
In this way, the first counter is preset to 4'15'3. Therefore, the output 110 contains a pulse train signal FO whose period between pulses is narrowed by one clock FC.
UT is obtained. By performing appropriate gating using this pulse signal FOUT, it is possible to create the soft edge switching pulse described in connection with FIG. 18. As described above for each of the elements in FIG. 4, these elements are all digital elements.

Therefore, horizontal and vertical synchronization signals are extracted from the composite video signal, and these synchronization signals are used to perform FY,'' and V as described above.
It is also desirable to digitize the circuit for creating BP. Normally, extracting the vertical synchronization signal from the composite video signal separately from the horizontal synchronization signal is performed by analog processing using an integrating circuit. In the method described below, 3.5
8! l! By counting the 4 Hz subcarrier, only the vertical synchronization component is distinguished and digitally extracted. As shown in the composite sync signal waveform of the video signal in FIG. 21, the horizontal sync pulse width is about 4 μsec, while the vertical sync pulse width is about 30 μsec. 22nd
The circuit shown in the figure focuses on such a difference in pulse width and extracts a pulse representing vertical synchronization. In FIG. 22, this vertical synchronization separation circuit is an 8-bit counter with two 4-bit counters 112 and 114 connected in a look-ahead manner.
It consists of a counter. Counters 112 and 114 may also be Texas Instruments SN74l6l integrated circuits. The clock inputs of the first and second counters receive a 3.58 MHz subcarrier at terminal 116, and the clear inputs of the first and second counters and the count enable inputs P and T of the first counter 112 are provided at terminal 118. and receives a composite synchronization signal which is inverted by an inverter 120. The carry output terminal of the first counter 112 is connected to count enable input terminals P and T of the second counter 114. The Q7 output terminal of the second counter, the 7-bit output of the 8-bit counter, is connected to output terminal 122. With the above configuration, when counting the 3.58 MHz clock, approximately b pulses are counted during the horizontal synchronization pulse period, while b pulses are counted during the vertical synchronization pulse period. Each time length counts approximately one (1) or more pulses.

Therefore, in order to distinguish both sync pulses, i.e. to separate the vertical sync pulse, the cut value 15 is 1 in binary.
111, the count value 100 is the binary number 1100010, so it is sufficient to take out the output of the 7th bit of the counter. In FIG. 23, b indicates a waveform extracted from the composite sync waveform of a at the 7-bit output terminal of the counter according to the vertical sync waveform. This output pulse can be suitably shaped and used as the VBP signal applied to terminal 50 in FIG. Other clock frequencies may be selected depending on the required jitter accuracy. 1 and 3, the ramp signal at terminal 24 supplied to dissolver switch 20 is generated by ramp signal generating circuit 130 shown in block diagram form in FIG.

Dissolve switch 20 has terminal 1 input to it.
2 and 14 video signals A and B are differentially combined.
This means that the output level of both combined video signals is always constant. A state in which the mixing levels of the A and B video signals are fixed at 50% of each other during dissolve is called a mix effect. Fade is a type of dissolve, where one of the video signals to be combined is in the form of a black burst, and the other image video signal is gradually emphasized. An effect that is emphasized and eventually becomes a blank screen is called a fade-out. Further, the dissolve time period is particularly called a "duration".
Such a dissolve effect is controlled by a signal applied to terminal 24. Ramp signal generation circuit 130 receives the frame pulse at input terminal 132.

Phase comparator 134, voltage controlled oscillator 136, and feedback path 138 form a PLL circuit. If the frequency of the frame pulse is Fv, the output frequency of the PLL circuit is fixed at, for example, 256 fV. This signal is input to a programmable counter 140 having a frequency division ratio of 11n, and is divided by the desired duration value n. It will be surrounded.
This frequency-divided signal is given to the first signal processing circuit 142. This signal processing circuit 142 is connected to the starting control input terminal 1.
44 and a stop control input terminal 146. The signal processing circuit has output lines 150 and 152 connected to the up and down inputs of counter 148, respectively. One output of counter 148 is provided to first signal processing circuit 142 via line 154. A DIA converter 156 receiving the counter output converts the counter output digital signal to an analog ramp signal, which is then provided to an output terminal 162 via a second signal processing circuit 158 and an amplifier 160. At this output terminal, a lamp signal is generated which is applied to the lamp control signal input terminal 24 of FIGS. 1 and 3. Such a ramp signal generation circuit 130
An arbitrary duration length from 0 to, for example, 255 frames can be set, and therefore, a duration from 0 to, for example, 858 frames can be set at a time twice as many as the frame.

A conventional circuit that provides various slopes up to a constant amplitude value inputs a constant frequency clock such as a frame pulse to an n-bit counter, converts the output into D18, and changes the gain of the analog output according to the duration. The signal was amplified using a saturable amplifier. In order to obtain an analog output that approximates a straight line, it is necessary to use a multi-bit counter and a DIA converter, and in order to obtain various slopes of the lamp output, it is necessary to control the amplification degree of the analog amplifier. . The steep slope output does not lose linearity, and the slope reduction is limited by the number of bits. The circuit of FIG. 24 effectively eliminates these drawbacks.

A signal synchronized with the vertical synchronization signal of the video signal, that is, a frame pulse signal Fv, is generated by a PLL circuit consisting of a phase comparator 134C0136 and a feedback path, for example.
It is converted to a frequency of 6 fv. This 256f frequency is divided by a desired duration value n in a programmable ● counter 140. This is counted by an 8-bit counter 148. The time TD required for the 8-bit counter 148 to count 256 pulses is as follows.

Therefore, the time TD is proportional to the set duration value n. The output of the counter 148 is converted into an analog value by a DIA converter 156, and a saturable amplifier 1 with a constant amplification rate is used.
The output ramp waveform amplified in step 60 can preferably form a ramp waveform with a slope corresponding to an arbitrary duration value. Also, if you want a long duration for dissolve or fade control, use the counter and DIA
This can be done by increasing the number of bits in the counter, but increasing the number of bits increases the cost, and on the other hand, if the duration is made longer, the change in screen movement becomes gradual, resulting in a mix state in the middle.

A first signal processing circuit 142 is provided to eliminate such drawbacks. This circuit 142 has a duration n
When 1≦n≦255, normal operation is performed, and n! 1b
When n=256, the ramp operates to have the same inclination as n=255, temporarily stops operating at the half position of 128, and resumes operation in response to a restart command. FIG. 25 shows a diagram of the output ramp waveform produced by such an operation. The voltage level is V on the vertical axis. , time is shown in frames on the horizontal axis. A solid line 164 is an output ramp waveform with a linear slope up to a predetermined n value by increasing the number of bits of the counter and DIA converter. From this n value, the output voltage becomes saturated, which is indicated by 166. 1st
By using the signal processing circuit 142, the output ramp waveform rises from the starting position 168 with the same slope as n=255. This is indicated at 170. At the time of n=128, the slope becomes 0 and the output voltage becomes constant. This is indicated at 172. At position 174, the lamp rises again in response to a starting command and reaches a predetermined saturation voltage position 166.

With this method, the number of pulses to be counted is 25
5, but the duration that can be controlled is unlimited. Of course, the various illustrative values in the embodiment described above may be changed, and the clock pulse frequency may also be selected to be other than the 30 Hz frame frequency. FIG. 26 is an example of a specific circuit of the first signal processing circuit 142 shown in FIG. 24.

A start command is applied to a terminal 144, and a stop command is applied to a terminal 146.A frame pulse is applied to a terminal 180, and a speed pulse from the programmable counter 140 is applied to a terminal 182.A beam set signal is applied to a terminal 184. The circuit 142 includes a D flip-flop 186,1
88, 190, 192, 194 - and two A
Includes ND gates 196 and 198. The output of AND gate 196 is connected to counter 148 via lead 150.
is connected to the up count input of AND gate 198.
The output of is connected via lead 152 to the downcount input of counter 196. 8-bit Counter 14
The 8 128 count output is connected via lead 154 to the clock input of flip-flop 194.

Therefore, if flip-flop 194 has a clock input, the signal at D input terminal 200 will appear at the Q output, thereby clearing two flip-flops 186 and 188. Counter 194 is SN7274, counter 186
, 188 are SN72l75, and the counters 190 and 192 are similarly constructed of SN72l75 type integrated circuits.
Counter 148 is comprised of an octal reversible counter made by cascading two SN74l parts 1C, and the output of this counter is connected to octal DIA converter 156. The analog output of the converter 156 is sent to the second signal processing circuit 1
Amplifier 160 and output terminal 1 after being processed by 58
62. Desolve Switch 20 in Figure 1
The level change of the two input video signals A and B is the 27th
When controlled by the dissolve switch 20 in the form of a gain control circuit as shown in FIG. Each signal must be completely switched during the time period T. However, T
In the section , signals A and B are mixed at a rate depending on the voltage of the ramp slope, and gradually switch to A-B or B-+A. At this time, the set time T feels faster than the time actually seen on the screen. The reason for this is that the lower end x (between the voltage level V1) and the upper end y (between the voltage level V2) of the lamp are dead zones where no movement is perceived when viewed with the naked eye. Therefore, it is a time when the dissolve effect can be seen on the screen. Second signal processing circuit 158
The purpose of this is to make the set T equal to the sensing time on the screen, thereby improving the operability of the dissolve. For this purpose, as shown by the solid line in Figure 28, the total amplitude of the lamp is increased from V to V- (V1 + V2), at which point the lamp is started by raising the level by V1, and at the moment the lamp is started. Now, lift only V2 and match the set time T and the perceived time D! It was designed so that A specific circuit configuration of this processing circuit 158 is shown in FIG.

The DIA converter output is provided to terminal 202.

The amplifier 160 is supplied with a ramp waveform from the DIA converter through a terminal 202, and is also supplied with the ramp waveform from the switch circuit 2.
A level shift voltage is supplied from 18. This switch circuit 218 consists of a first electronic switch S1 and a second electronic switch S2, and the first and second electronic switches S1 and S2 are connected to the first output Y of the data selector 226.
and a second output Y1. The data selector 226 consists of four single-throw, double-pole electronic switches, and each output Y when the key-out signal from the terminal 216 is at a high level. , Yl, Y2, and Y3 are one input B of each. , Bi, B2, and B3, and when the key out signal is at a low level, they are connected to the other inputs AO, Al, A2, and 8, respectively. The first input pair BO, AO of the first electronic switch of the data selector 226 is connected to a first D-type flip-flop 2.
28 and the O of the second D-type flip-flop 230.
The outputs of the second D-type flip-flop are connected to the second input pair Bl, Al of the second electronic switch.
and the O output of the first D-type flip-flop 228 are connected, respectively, to the third input pair B2, of the third electronic switch.
The carry and holo outputs of the counter 148 are connected to A2 via terminals 208 and 210, respectively, and the fourth input pair B3 and A3 of the fourth electronic switch are connected to the start and end points of the dissolve. A pulse signal indicating point T2 is provided via terminals 204 and 206, respectively.

Now, when a dissolve operation is performed using a ramp waveform as shown in FIG. 28, the key out signal is set to high level, and the output Y of each electronic switch of the data selector.

, Yl, Y2, Y3 are input B. , Bl, B2, 8. When a pulse signal is applied to the terminal 204 at the start point t1 of the dissolve period, this pulse signal is applied to the clock terminal of the first D-type flip-flop 228 through the fourth electronic switch Y3. As a result, the Q output of the first flip-flop 228 becomes high level, and this Q output becomes the high level of the first electronic switch low YO.
through the switch circuit 218, which closes the first electronic switch S1. As a result, the power source 224 is supplied to the amplifier 160, and the starting point t is shown in FIG.
At 1, the level increases rapidly. Thereafter, during the dissolve period, a ramp waveform is supplied to the terminal 202 from the AID converter. Then, when the counter 148 finishes counting at the final moving point, the carrier output is transferred to the terminal 2.
08 to the third electronic switch of the data selector. The carrier output is the second flip-flop 23
When applied to the 0 clock terminal, the D terminal of this flip-flop 230 is at a high level, so the Q output becomes high. As a result, this Q output is supplied to the second switch circuit S2 of the switch circuit 218 through the second electronic switch Y1, closing this switch circuit S2. As a result, the power source 220 is supplied to the amplifier 160, and the level of the ramp waveform increases rapidly again at the final point T2, as shown in FIG. The above is the operation to obtain the ramp waveform shown in FIG. 28, but in order to obtain a ramp waveform that is contrary to this, the key out signal at the terminal 216 is set to low level and the data selector 226 is switched to the stop command signal. This is made possible by controlling the first and second flip-flop circuits 228 and 230 using a holographic signal.

In order to check the state before and after the dissolve operation, a reset signal is sent from the terminal 212 to the first and second flip-flop circuits 228 and 230, and a preview signal is sent from the terminal 214 to the first and second flip-flop circuits 228 and 230. A signal is given.

That is, when the reset signal is applied to the clear terminals of the first and second flip-flop circuits 228 and 230, each Q output becomes a low level, and the switch circuit 218 becomes an initial state. On the other hand, when the preview signal is applied to the priority terminals of the first and second flip-flop circuits 228 and 230, each Q output becomes high level, and the switch circuit 218 enters the final state.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of the signal system of a television special effects generator incorporating the present invention, and FIGS. 2A and 2B illustrate the effects on a television screen produced by operation of the circuit of FIG. 3 is a circuit diagram showing details of a circuit embodying the circuit of FIG. 1, and FIG. 4 is a block diagram of a wipe (key) generator for use with the circuits of FIGS. 1 and 3. , FIGS. 5 and 6 are waveform diagrams for explaining the operation of a part of the circuit of FIG. 4, and FIG. 7 is a waveform diagram for explaining the operation of the elements described in connection with FIG. 5. , FIG. 8 is a waveform diagram for explaining the operation of the elements in other parts of the circuit in FIG. 4, and FIG. Diagrams for explanation, No. 10, 11, 12, 13, 14, 15 and 15''
This figure is a diagram showing a television screen created by changing the operating state of the circuit in FIG. 4, and FIG. Figures 17, 18 and 19 are diagrams showing a television screen and its related waveforms for explaining the operation of certain elements of the circuit in Figure 4,
, 18 and 19, and FIGS. 21, 22 and 23 are for explaining the circuit for obtaining the signal given in FIG. 4 and its operation. The circuit diagram and waveform diagram of Figure 24 are the same as Figures 1 and 3.
25 is a waveform diagram for explaining the operation of certain elements in Figure 24, and Figure 26 is a concrete diagram of the elements explained in connection with Figure 25. 27 and 28 are waveform diagrams for explaining the operation of other elements in FIG. 24, and FIG.
29 is a diagram showing a specific circuit of the element described in connection with FIGS. 4 and 28; FIG. In the figure, 158 is a second signal processing circuit, and 218 is an electronic switch.

Claims (1)

[Claims] 1. Supplying an input signal to a gain control circuit, and changing the input signal from a first level to a second level different from the first level in a predetermined period.
The level of the input signal is controlled by the control signal up to a level of , and a rapid level change portion is formed in the level-controlled input signal at the start point and/or end point of the predetermined period. signal processing circuit.