JPS6020932B2 - timer circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to timer circuits.

The timer circuit of the present invention outputs a pulse signal indicating that a predetermined time has passed after the arrival of an input signal, and the predetermined time can be selectively specified from the outside. This is to prevent dangerous malfunctions even if there is a malfunction.

The present invention will be explained below with reference to the drawings.

FIG. 1 shows an embodiment of the timer circuit of the present invention. In the figure, S/RA to S/RE are shift registers that operate at the rising edge of the pulse applied to the shift pulse terminal, and GI to G3 are shift registers that operate at the rising edge of the pulse applied to the shift pulse terminal. Nand gate with such characteristics,
G4-G6 are AND gates, NAND gates GI-G3
One input terminal is commonly connected to the input of the timer circuit, and the other input terminal is a dedicated terminal for time setting T, ~T3.
individually connected to.

The input of S/RA is the output of NAND gate GI, and the S/RB
The input of is connected to the output of S/RA, and the AND gate G4
One input of is connected to the output of S/RB, and the other input is connected to the output of NAND gate G2. The input of S/RC is the output of AND gate G4, and the input of S/RD is S/
Connected to the output of RC.

One input of AND gate G5 is connected to the output of S/RD, the other input to the output of NAND gate G3, and the output of AND gate G5 is connected to the input of S/RE. The output of S/RD is input to one input of AND gate G6, and the output of S/RE is input to the other input of inverter I.
Given via NV. Next, Nand Gate GI~G
A specific example circuit of No. 3 is shown in FIG.

In the figure, one input terminal of this NAND gate connected to the input IN is connected to the base of the transistor QI via the input resistor RA, and the collector is connected to the voltage source EC via the resistor RI. connected to the base of

The collector of transistor Q2 is directly connected to the base of transistor Q3 and is connected via an input resistor RB to the other input terminal of this gate which is connected to dedicated terminals T, .about.T3. The collector of transistor Q3 is resistor R
2 to the voltage source C and to the output terminal of this gate. The emitters of these transistors QI to Q3 are also grounded. The operation of the timer circuit having such a configuration will be explained next.

FIG. 3 is a waveform diagram at various points for explaining the operation of the timer circuit of FIG. 1. Now, consider the case where only the dedicated terminal T, is set to a high level, or logic "1", and L and T3 are given a low level, or logic "0".

Then, the outputs of NAND gates G2 and G3 become "1" regardless of the logic "1" or "0" of the input signal applied to the input river.
” becomes.

To elaborate on this, these NAND gates are Ti
When "0" is applied to the terminal, transistor Q2 is opened or shorted by the signal applied to the input IN terminal, that is, logic "1" or "0", but in either case, transistor Q3 is turned off. Therefore, the gate output is ``1''
become.

Furthermore, the NAND gate is characterized in that even when no signal is applied to the Ti terminal due to a failure such as poor contact, the gate output is "1".

However, since the output of the NAND gate GI is "1" given to the Ti terminal of the NAND gate in Fig. 2, the gate output becomes the inverted logic of the input IN terminal and is given to the input of the shift register S/RA. . In this case, S/RA to S/RE are directly connected and vertically connected, so the output waveform of S/RA is shifted in order. Therefore, the time until the arrival of the input signal generates the pulse obtained from the AND gate G6 at the output terminal OUT is the second
This is the TWI time shown in the "output" waveform in the figure. Next, when only the dedicated terminal T2 is "1" and the terminals T and t are "0", the outputs of the NAND gates GI and G3 are always "1" as described above, and the outputs of S/RA and S/RB are "1". As shown by the broken lines in FIG. 2, the values never become "0".

The input signal is inverted and given from the output of AND gate G4.

The operations of S/RC to S/RE are the same as above, and the output waveforms of these shift registers are as shown by the broken line in FIG. 2, and the time until the output pulse of AND gate G6 is generated is shown by the broken line. The time is TW2 as shown in . When the terminals T and T2 are "0" and only T3 is "1", the time until the output pulse of the gate G6 is generated is an additional time.

Thus, according to the logic of the dedicated terminals T, .about.T3, the output pulse of this timer circuit is selected which represents the elapsed time since the arrival of the input.

In this way, the elapsed time after the arrival of the input signal is determined by the dedicated terminal T,
-T3 is set by selecting one of them.

The feature of the timer circuit of the present invention is that, as can be seen from the embodiment in FIG. Instead of being led to the input of the NAND gate in the same order or in parallel as seen in , the logic "1" and "0" of the input IN are once exchanged with an open and short circuit signal, and this signal and the signal of the Ti terminal are connected. are connected in parallel and the input of the Ti terminal is "1", the logic of the input m is inverted and becomes the output of the NAND gate, and T
When the input to the i terminal is "0", the output of the NAND gate is "1" regardless of the logic of the input m. Therefore, unless a signal of "1" is input to the Ti terminal via the dedicated terminal, the output of this NAND gate will not become "0".

In addition, even though the input of a “1” signal to the Ti terminal may become “0” due to poor contact, etc., the “0” signal input to the Ti terminal
” signal will never become “1” even if it is accidentally input.
From now on, for example, the dedicated terminals T,, T2, T3 are (0, 1
, 0), the input to the base of transistor Q3 may become (0, 0, 0) due to a failure, but it will never become (0, 0, 1). In other words, when a failure occurs, the timer time may become infinite, but it will never become shorter. Further, even if an open failure or a short failure occurs in the transistor Q3 constituting the final stage of the NAND gate, the timer time will not become shorter.

In other words, in such an open fault or short fault, the NAND gate cannot read the change in the input signal, and in the case of a short fault, the output of the NAND gate is always "0", so the AND gate does not convey the change in the input state. , the timer time never becomes shorter. Therefore, even if the time is set shorter than the set time and the output representing the elapsed time is not sent out, it is safe because dangerous malfunctions can be avoided.

For example, in a device that sets elapsed time by using a decoder circuit that uses two variables as input variables and sends out four outputs, a malfunction in the decoder circuit causes multiple outputs to output the same logic signal as the selected one. Comparing this with the fact that there was an inherent possibility that both would occur at the same time, it can be said that this is a timer circuit that takes so-called safety design into consideration.

In the above description, three time settings can be selected, but the time can be set arbitrarily by increasing or decreasing the number of circuit elements as necessary. Brief Explanation of the Drawings FIG. 1 shows an embodiment of the timer circuit of the present invention, FIG. 2 shows an embodiment of the NAND gate of the timer circuit of FIG. 1, and FIG. 3 shows an embodiment of the timer circuit of FIG. 1. FIG. 2 is a time chart for explaining the operation of FIG.

GI~G3...NAND gate, G4~G6...AND gate, S/RA~S/RE...shift register, m
V...Inverter, T, ~L...Dedicated terminal for time specification.
Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 An input is connected to a plurality of dedicated terminals for time setting, an input signal terminal, and the dedicated terminal, and a short circuit or open signal obtained in response to the input of the input signal terminal and a signal to the dedicated terminal are connected. A first group of gate circuits outputs a logic signal in combination with an input; a second group of gate circuits has the output of the first group of gate circuits as an input; a plurality of shift registers connected in series via gate circuits belonging to the second group, a signal obtained by inverting the output of the last register of the shift registers, and an output of the register immediately before the last register; and a logic circuit that outputs a logic function signal.