JPS6021515B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television receiver in which information such as the time and the channel number being received is displayed on a portion of the image reproduction surface superimposed on the television image being received.

In recent years, as IC technology has progressed, the functionality of television receivers has increased, and receivers having the above-mentioned functions have come to be seen on the market.

In such a television receiver, when displaying information such as the time and channel number on the image reproduction screen, the display is generally as follows.

tl} The time and channel number are automatically displayed on the image playback screen only when performing channel selection operations such as channel switching.

■ It is equipped with switches for controlling the display, and when necessary, the time and channel number can be displayed on the image playback screen by operating these switches.

All of these methods are intended to reduce the complexity of displaying the time and channel number superimposed on the television image at all times, but they have the following drawbacks.

First, in the case of [1], since the display is only performed during the channel selection operation, if you want to check the time or channel number while receiving the signal, you will have to repeat the unnecessary selection process. The operation must be repeated.

Also, in case of '2), you cannot know the time or channel number without operating a switch each time, which is the same as in case of '1}. A switch must also be operated at the same time, and if you forget to turn off the switch and leave the display on, it will get in the way of viewing the television image.

This will be explained using drawings.

FIG. 1 shows an example of a television receiver having a function corresponding to the case (2) above.

1 is a clock circuit, which is usually composed of a digital circuit, and its output time information is expressed in the form of a 4-bit binary IG Hayabusa code for each hour, minute, second, etc. It is customary.

2 displays the time and channel number numerically on the image reproduction screen in accordance with time information from the clock circuit 1 and a signal representing the channel number being received obtained from a tuner connected to the terminal 12; This is a display signal generation circuit that generates a display signal for the display, and its output is obtained in the form of a pulse signal.

3 is an AND gate which gates the display signal from the display signal generation circuit 2 in accordance with the Q output of the RS flip-flop 8.

4 is a diode for passing only "1" of the display signal which is a pulse signal when the display signal from the AND gate 3 is superimposed on the video signal from the terminal 6, and the superimposition ratio at that time is The values of the resistors 51, 52, and 53 can be determined arbitrarily, and the superimposed video signal is sent to the output terminal 7.
can be obtained.

8 is R for generating a gate signal for gate 3 as described above.
In the S flip-flop, when the display start switch 9 is pressed, a current flows from the power supply 11 to the resistor 54, a signal is applied to the set input S to set it, the Q output becomes "1", and when the display stop switch 10 is pressed A current flows through the resistor 55, a signal is applied to the reset input R, and the Q output is reset to ``0''.

The operation of this circuit will be briefly explained below.

When the display start switch 9 is closed while the television receiver is in operation, the flip-flop 8 is set and the Q output is “
1", the AND gate 3 opens, and the display signal from the display signal generation circuit 2 is transferred from the diode 4 to the resistors 51 to 53.
It comes to be superimposed on the video signal from terminal 6 via.

Therefore, a display signal is supplied from the output terminal 7 to the cathode ray tube of the television receiver together with the video signal, and the time and channel number are displayed on a portion of the image reproduction surface. next,
When the display stop switch 10 is pressed, the flip-flop 8 is reset and the Q output becomes "0". Therefore, AND
Since the gate 3 is closed, the display signal is blocked by the AND gate 3 and is no longer supplied to the cathode ray tube of the television receiver, and the display of the time and channel number disappears from the image reproduction screen. Therefore, in a television receiver having such a configuration, each time you want to know the time or channel number, press the switch 9 to display it on the image playback screen, and each time you want to erase the display, press the switch 9.
Switch 10 must be pressed.

An object of the present invention is to eliminate the drawbacks of the prior art described above, to provide a television that can display the time and channel number on the image playback surface without interfering with the television image, and that does not require the operation of switches or the like. To provide the receiver.

In order to achieve this object, the present invention is characterized in that the time and channel number are automatically displayed repeatedly at predetermined time intervals on the image reproduction screen.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

In the embodiment shown in FIG. 2, the same parts as in FIG. 1 are given the same numbers, and detailed explanation thereof will be omitted.

This embodiment differs from the case shown in FIG.
An intermittent display control circuit 13 is provided in place of the flip-flop 8 for generating a gate signal for the gate 3.
The difference is that a gate signal is supplied to the AND gate 3 in accordance with time information from the clock circuit 1.

In the configuration of this intermittent display control circuit 13, 131 and 1
Reference numerals 32 denote OR gates each having four inputs, to which time information expressed in a binary IG Hayabusa code from the clock circuit 1 is supplied, and to the input of the OR gate 131, a signal representing the minute of the time is supplied. The first signal is the OR gate. The signal of the 10th place is connected to the input of 132.

133 is a two-input NOR gate, OR gate 131,
Only when all of the outputs of 132 become "0", "1" is generated as an output, and the AND gate 3 is opened.

Now, in the embodiment of the present invention configured as described above,
At 0 minutes of every hour, among the time information from clock circuit 1,
The 4-bit signal representing the 1 minute digit signal and the 4-bit signal representing the 1 minute digit signal are all "0".

That is, at 0 minutes of every hour, the inputs of OR gates 131 and 132 are both (0000). Therefore, the outputs of OR gates 131 and 132 also become "0", so the NOR
Since the output of gate 133 becomes “1”, AND gate 3
opens, and as already explained, the display signal from the display signal generation circuit 2 is superimposed on the video signal from the terminal 6 and supplied to the cathode ray tube of the receiver, and superimposed on the television image on the image reproduction surface. The time and channel number being received are displayed. Eventually, as time passes and it reaches 1 minute,
Since the first-order signal added from clock circuit 1 to the input of OR gate 131 is (0001), this OR
The output of the gate 131 is changed to “1”, and the output of the NOR gate 13
The output of 3 becomes "0".

Then, the AND gate 3 closes and the display signal being supplied to the cathode ray tube is blocked, so that the time and channel number disappear from the image reproduction screen, leaving only the television image.

In this example, OR gates 131 and 132 are used to display the display only when the hour reaches 0 minutes, that is, every hour. It is unnecessary to explain that by appropriately performing the supply method, it is possible to set an arbitrary time and display at arbitrary intervals.

Furthermore, if an intermittent display control circuit 13 is provided in addition to the flip-flop 8 in FIG.
It is also possible to add a function that allows arbitrary display from 101.

As explained above, in the embodiment of the present invention shown in FIG. 2, the time and the reception channel number at that time are automatically displayed on the image playback screen every time the hour reaches 0 minutes. , there is no need to go through the trouble of selecting a channel or operating a switch separately when you want to know the time or channel as in the conventional technology, and the time and channel number are always displayed on the image screen unnecessarily. It is possible to obtain an effect such that the image surface is not made complicated due to the above.

Generally, when using a television receiver, the channel is often changed when changing the television broadcast program, so the time and channel number are displayed at 0 minutes of every hour or every third generation. Therefore, according to the present invention, the time and channel number are automatically and always displayed when needed. , a great practical effect can be obtained. Note that in the above explanation, detailed explanations of the clock circuit 1 and the display signal generation circuit 2 have been omitted, but any known configuration may be used for these, and any configuration may be used. Those skilled in the art can easily understand that the effects of the present invention can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional television receiver that displays the time and channel number on the image playback screen by operating a switch, and FIG. 2 is a block diagram showing an example of a television receiver according to an embodiment of the present invention. 1 is a block diagram of a John receiver; FIG. 1...Clock circuit, 2...Display signal generation circuit, 3...AND gate, 4...Diode for superimposing display signal and video signal, 13 ...
...Intermittent display control circuit. 2 illustrations

Claims (1)

[Claims] 1. In a television image device having the function of displaying the time and the channel number being received by superimposing it on a portion of the television image, a clock circuit for generating time information, and the time information and the channel number being received by the clock circuit are provided. a display signal generation circuit that generates a display signal for displaying on the image reproduction screen; a gate circuit that is connected to the display signal generation circuit and controls the continuation of this display signal; and a gate circuit that is connected to the display signal generation circuit and controls the continuation of this display signal, and and an intermittent display control circuit that controls the gate circuit in order to display both the time and the receiving channel number on the image reproduction screen for a fixed period of time at each predetermined time interval according to the time information. Characteristic television receiver.