JPS6022531B2 - Schmitt circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schmitt circuit with a highly accurate threshold value.

Figure 1 shows a conventional Schmitt circuit with highly accurate ON and OFF levels.

In the figure, 101 and 102 are comparators, 105 and 106 are AND circuits, and the logic circuit 105 and ID6 constitute an RS flip-flop. In the circuit of FIG. 1, the reference voltages are Vref, . Let Vre et al., and Vre also >Vref2.

When the input signal Vre is also lower, the output of the comparator 101 is at H level and the output of comparator 102 is at L level, so the output of AND circuit 105 is at L level. When the input signal rises from this state and takes an intermediate value between Vref and Vref2, the outputs of comparators 1 and 01 and comparator 102 both go to H level, so in order to maintain the previous state, the logical product is The output of circuit 105 is at L level. When the input signal further increases and Vre reaches a pressure higher than that, the output of comparator 101 becomes L level, the output of comparator 102 becomes H level, and the output of logic bond circuit 105 becomes H level. From this state, the input signal is lowered to Vref,
When the value is between Vref2 and Vref2, the outputs of comparators 101 and 102 are both at H level, and the output of AND circuit 105, which maintains the previous state, is at H level. When the input signal is further lowered to a value below Vref2, the output of comparator 101 becomes H level and the output of comparator 102 becomes L level, so the output of AND circuit 105 becomes L level. If the relationship between the input voltage and the output voltage is illustrated based on the above operation, the operating characteristics shown in FIG. 2 can be obtained. As explained above, in the conventional circuit, the AND circuits 105, 10
6 RS flip-flops are required, and the circuit configuration is complicated. The present invention realizes a highly accurate Schmitt circuit with a simple circuit configuration.

The present invention will be explained below with reference to FIG. 103 in the figure
, 104 is a comparator, and 108 is an OR circuit. 107
indicates a comparator operation control circuit; when the output of the OR circuit 108 is at H level, the comparator 104 operates; when the output of the OR circuit 108 is at L level, the comparator 104 stops operating; The output becomes L level.

While the input signal is lower than Vre, etc., the outputs of the comparators 103 and 104 are both at L level, so the OR circuit 1
The output of 08 is at L level. Comparator operation control circuit 10
7 is a comparator 10 when the output of the OR circuit 108 is at L level.
In order to stop the operation of the comparator 104, the operation of the comparator 104 is stopped. When the input signal is increased to a value between Vref and Vtef2, the output of comparator 103 is at L level, and since comparator 104 remains inactive, its output is at L level. It remains as it is. Therefore, the output of OR circuit 108 is at L level. When the input signal is further increased to a value higher than Vref, the comparator 103
The output of the OR circuit 108 becomes H level, and the output of the OR circuit 108 becomes H level.
level.

When the output of the OR circuit 108 becomes H level, the comparator operation control circuit 107 operates the comparator 104, so the output of the comparator 104 also becomes H level. When the input signal is lowered from this state and takes a value between VreL and Vref2, the output of the comparator 104 is at H level, so the output of the OR circuit 108 is at H level. When the input signal further decreases to a value below Vref2, the comparator 1
Since the outputs of 03 and 104 are both at L level, the output of OR circuit 108 is at L level. FIGS. 4 and 5 each show a specific embodiment of the present invention.

In the embodiment shown in FIG. 4, 11 is a PNP transistor;
12 and 13 are differentially connected NPN transistors, 19
31 is a resistor, and 51 is a diode, which constitute a comparator 104. 15 is a PNP transistor; 16 and 17 are NPN transistors connected in a closed-loop manner; 20 is an NPN transistor that functions as a constant current source; 33 is a resistor; and 52 is a diode, which constitute a comparator 103.

PNP transistors 14 and 18 have their bases connected to the collectors of transistors 12 and 16, respectively, and constitute an OR circuit 108.

Reference numeral 21 denotes an NPN transistor whose base is connected to the collectors of the transistors 4 and 18 via a resistor 32, and constitutes the comparator operation control circuit 107.

34, 35, and 36 are resistors connected in series, and supply the potential Vref between the resistors 34 and 35 to the base of the transistor 17, and supply the potential Vref2 between the resistors 35 and 36 to the base of the transistor 13.

201 and 202 are DC power supplies.

In the embodiment shown in FIG. 5, 53 is a diode between the base and emitter of the transistor 21, and the transistor 2
1. Constructs a comparator operation control circuit 107 together with the resistor 32.

301 is a constant current source connected to transistors 16 and 17.

It will be readily understood that the embodiments shown in FIGS. 4 and 5 operate in the same way as the embodiment shown in FIG. 3. As explained above, the Schmitt circuit according to the present invention uses an OR circuit and a comparator operation control circuit in place of the RS flip-flop of the conventional circuit. The comparison operation control circuit can also be constructed with a small number of parts, resulting in a simpler circuit configuration than conventional circuits. Incidentally, FIG. 12 of Hakamakai Publication No. 48-10296 shows a sawtooth wave generating circuit related to the present invention, but if this circuit is rewritten as a Schmitt circuit, it will become as shown in FIG. 6.

In the circuit of FIG. 6, if the base potential Vref, of the transistor 13 when the transistor 7 is in the FF state is larger than the base potential Vref21 of the transistor 5, Vref, , Vref2 is set to two threshold values. The Schmitt circuit operates as follows.

However, in the circuit shown in FIG. 6, one of the two reference voltages (VreL) is controlled by the output signal, and at this time, Vre must not be affected.

For this reason, the reference voltage stage must be prepared independently.
Like the reference voltage stage of the embodiment shown in FIGS. 4 and 5,
Two reference voltages cannot be obtained by dividing the power supply voltage by three resistors.

Therefore, the following disadvantages arise. I Vr
When ef, and Vref2 are made close to each other to reduce the hysteresis, if an independent reference voltage is used, the hysteresis (Vref, - Vref2) will be reduced due to variations in the resistance ratio.
However, there will be large variations, and in some cases, the relationship of Vref,>Vref2 may not be maintained, and the Schmitt circuit operation may not be performed.

2. When integrating a circuit with a relatively high power supply voltage, the resistance between the power supply and GND should be reduced as much as possible.

The reason for this is that in integrated circuits where it is difficult to use large resistors, the circuit configuration in which a resistor is connected between the power supply and ground is
This is because it increases current consumption.

The circuits shown in FIGS. 4 and 5 have one resistor row from the power source to the ground, and the circuit shown in FIG. 6 has two rows. From this, the circuits shown in FIGS. 4 and 5 are superior to the circuit shown in FIG. 6. The circuit according to the present invention can be used in a wide range of applications such as high-precision filter circuits, timer circuits, triangular wave generation circuits, chain-tooth wave generation circuits, astable multinoise brakes with accurate pulse width, monostable multipipelators, etc. It can be applied to consumer and industrial electronic circuits.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing a conventional Schmitt circuit, Fig. 2 is a characteristic diagram explaining the operation of the Schmitt circuit, Fig. 3 is a circuit diagram showing a Schmitt circuit according to the present invention, and Fig. 4 is a circuit diagram showing a Schmitt circuit according to the present invention. 5 is a circuit diagram showing an embodiment of the present invention, and FIG. 6 is a circuit diagram of an embodiment of the present invention.
Publication No. 110296! 2 is a circuit diagram of FIG. 2 rewritten as a Schmitt circuit. In the figure, 101 and 102 are comparators, 105 and 106 are AND circuits, 103 is a first comparator, 104 is a second comparator, 107 is a comparator operation control circuit, and 108 is an OR circuit. Figure 2 Figure 3 Figure 6 Figure 4 Figure 5

Claims (1)

[Claims] 1. A first comparator that has a differential input stage and compares the first reference voltage and the input signal, and has a differential input stage;
a second comparator that compares a second reference voltage and the input signal; a logical sum circuit that obtains a logical sum of the output of the first comparator and the output of the second comparator; A Schmitt circuit that controls the bias current of the input stage of the second comparator based on the output of the circuit to operate or stop the second comparator, and uses the signal obtained at the output of the OR circuit as an output signal.