JPS6022629B2 - thermal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal recording device, and particularly relates to controlling the recording power pulse width to record at a predetermined density directly in a thermal recording bag that records at irregular time intervals and at high speed. .

Recording density in thermal recording varies based on various factors. In a thermal recording device using a thermal head having a plurality of heat generating elements, which is the object of the present invention, the following two factors can be broadly classified. That is, one is a change in recording density mainly due to factors of the individual heat generating elements, and the other is a change in recording density due to factors that can be considered collectively for a plurality of heat generating elements. The former is the object of the present invention, and the latter is, for example,
48 (Utility Model Publication No. 57-20354) ``Thermal printing density control device.'' It is known that in the thermal head used in the embodiments described later, each heat generating element radiates heat with a time constant of about 3 to 4 msec when the recording power pulse is interrupted. When a heat generating element is thermally driven with a recording power pulse having a time width of 1.8 hsec, recording is made at the planned recording density, the heat generating element returns to the base temperature level after about 1 hsec, and until then the temperature remains is in a feverish state. The recording density in thermal recording is determined by the thermal energy applied from the heating element to the coloring agent or transfer agent. This thermal energy is determined by the recording power pulse and the heat accumulation state.
That is, when thermally driven in a high heat accumulation state, a dark record is obtained.
Conventionally, in a thermal head in which multiple heat generating elements are arranged, changes in recording density due to individual factors of the heat generating elements can be controlled by controlling the pulse of recording power using a resistor and a capacitor in the drive circuit of each heat generating element. We are taking a method to do so.

In this case, as the number of heating elements increases, the number of adjustments increases, and the size of the drive circuit also has a limit due to the inclusion of an atrog circuit. On the other hand, even if control using resistors and capacitors is replaced with a logic circuit, an arithmetic circuit (AUL) is required for each heating element, and a thermal head with a large number of heating elements requires a huge number of gates. Or, it is necessary to have control conditions for each heating element individually.

Therefore, if the structure of the head changes or the coloring agent or transfer agent is different, it is necessary to change all the conditions for each heating element. For this reason, in a thermal recording device that uses a thermal head with a large number of heat-generating elements, it is necessary to wait for the heat-generating elements to drop to the base temperature level before starting the next recording, or to take measures to quickly lower the temperature to the base temperature level. , and record the planned concentration. However, the recording cycle is 1.9hsec or 2.9hsec.
When high-speed recording on the order of about 100 seconds is required, the above-mentioned method cannot be used, and the next recording must be performed while the heat is stored. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a heat-sensitive recording device that can start recording at a predetermined density in a heat-storage state and can be applied even when the time intervals scheduled for recording are not constant. That is, the present invention stores in advance the relationship between the recording interval time that provides a scheduled density and the time width of the recording power pulse, and also stores the history of each heat generating element in the record information unique to each heat generating element. The time width of the recording power pulse given to the heat generating element is controlled in synchronization with a recording control clock having a clock interval corresponding to a predetermined density error. . Examples will be described below. FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, 32 heating elements 1, 12, .
. . , 11, . . . , 132 record a line with 32 black and white pixels, and each heating element 1, to 132 returns to the base temperature level by leaving a recording interval of 1 hsec or more. , 1.5hs at basal temperature level
The scheduled temperature is recorded by thermally driving with a recording power pulse having a time width of ec. Therefore, the maximum recording cycle is about 1.8 hsec, and the recording interval of the heating elements 1, - 132 that are not thermally driven for 7 lines or more is always 1 hsec (7xl. sec) or more.

The recording information DM, D2o, ...D,o, ..., D32o of "1" and "0" for one line to be recorded from now on is transferred from the memory 2 to the AND gates 31, 32, ..., 31, ..., 3.
32 to the gate terminals of the heating elements 1, . . . , 2, one end of each heating element 1, . Said AND gate 3, ~
Trigger signals Pt, Pt2'... are connected to the other two terminals of the three spots.
'Po,...,Pt32 are given. These time relationships are shown in FIG. In FIG. 2, the recording control clock h is generated at a time interval of 125 fsec, and t in the recording start reference time signal T is the recording start reference time of the line lo to be recorded from now on, and T, to T7.
is the recording start reference time of the past seven lines 1 to 17.

The power supply voltage HV is based on the recording start reference time signal T,
1.8 hs of 1.2 clock period of recording control clock h
It is held at a high potential during the ec period, and is grounded or at a low potential during the other periods. Also, the current number of recorded information D, o to O8 is
It is written into the memory 2 immediately before the recording green start reference time signal To, and is continuously read out until the period corresponding to h,2 of the recording control clock h, and Dio in FIG. This is a representative view of the read period corresponding to the heat generating element li. Here, Du(i=1 to 32,
j=0 to 7) indicates recorded information. i is a subscript corresponding to the heat generating element li and corresponds to each heat generating element. i is a subscript corresponding to the recording start reference time signal TJ and indicates recording information printed by the signal of Tj. For example, when the heat generating element 132 prints black at the recording start reference time T, D3a=1, and when white is printed, D3a=0. This is a representative example of one of the trigger signals Pt, ~Pt32 in FIG.
is a representative representation of one of the recording power pulses P, .about.P. Recording power pulses P, to P32 are generated by heating element 1. ~
Whether it is given to 132 or not depends on the recording information D, o to D32.
The recording power pulses P, .about.P32 rise at the end of the clock period to which the corresponding trigger signals Pt, .about.Pt32 are applied, and the recording power pulses P, .about.P32 rise at the end of the clock cycle to which the corresponding trigger signals Pt, .about.Pt32 are applied, and at the fall of the power supply voltage HV. fall uniformly. As will be clear from the following explanation, the trigger signals Pt, .about.Pt32 are generated in one of the cycles h, .about.h, 2 of the recording control clock h, so the pulse width of the key recording power pulses P, .about.P32 is 12.
The recording density, which can be controlled at intervals of 5 ms and corresponds to a recording power pulse having a time width of 125 rsec, determines the density error. Again in FIG. 1, 4 is the recording interval TW, ~TW7 (second
This is a recording interval measurement memory that measures and updates the recording interval (see figure) and stores it in an updated manner, and is repeatedly read out in parallel in synchronization with the recording control clock h after the current recording start reference time To. ~tw7 indicates the read recording interval measurement time signal and is applied to the comparator 5.

A circuit for measuring and recording TW.~TW7 can be easily implemented using a counter, memory (RAM, etc.), and an adder. FIG. 3 shows its block diagram. That is, every time the recording start reference time 9 occurs, the recording interval TWj-, is retrieved from the memory, the value of the counter is added, and the result is stored again in the memory at the address where the recording interval TWj is stored. In addition, if the recording interval time exceeds 1 hsec,
It is stored as hsec. The other input of the comparator 5 in FIG. 1 is the recording interval scheduled time signal w of the memory 6.
The memory 6 stores the recording power pulse width using a recording control clock h.
Addresses are made to correspond to clock cycle numbers 1 to 12, and scheduled recording interval times are stored in advance as shown in Table 1. That is, the address is a counter signal counted by the clock h and set by the recording start reference time signal T. As the calculation of this counter progresses, the thyristor trigger signal is delayed. Therefore, when the address value is small, it is necessary to trigger the heating element with a long recording interval time, and when the address value is large, the recording interval time must be shortened and the heating element is triggered. This relationship is stored in memory 6. Table 1 In Table 1, for example, the storage content of the fifth address is 2.5, which means that the recording interval time w is 2.5.
In the case of 5hsec (=w5), this means that the recording power pulse width that provides the expected density is 1.00 seconds.

Note that even when the heat generating elements 1 to 132 are driven continuously without recording interval time, 0. Although a recording power pulse with a pulse width of Sec is required, and therefore information on addresses 10 to 12 is unnecessary, they are provided to maintain uniformity of control. Recording interval time w, ~w of this memory 6
9 is after the recording start reference time To as shown in FIG.
The data are sequentially read out in synchronization with the recording control clock h. 1st
Comparator 5 in the figure has recording interval measurement time W, ~tw7
and recording interval scheduled time w. , w2, . 3. enemy hSeC, t scold = 5. enemy hSeC
, tW3=9.8hSeC, tW4-tW7=12. If hSeC or higher, the comparison results C, to C7 will be as shown in Table 2. Table 2 On the other hand, when the recording power pulses P, .
c or more, in this case t cry ~ 1 in tw7
hsec or more, the heat generating elements 1 and 132 that were not thermally driven in the past 3 lines 1 and 13 are targeted, and the recorded information of the past 3 lines 1 and 13 is all "0".
This applies if the

Similarly, the recorded information of the past two lines 1, 12 of the heating element 1, to 1 spot that should be moved by the clock cycle h2 is “0”.
”, and the heat generating elements 1 to 132 to be thermally driven by the cook cycles h3 and h4 are
This is a case where the recorded information of is "0", and after the clock cycle, all heat generating elements 1, . . . 1 are targeted. Therefore, the comparison results C and ~C7 shown in Table 2 indicate the correspondence between the recorded information of past recording lines 1 and 17 and the thermal drive start clocks h, ~h, and 2. . That is, Hisame-ketsu Cj (i=1 to 7) indicates the range of permitted recorded information history. On the other hand, Cj and recorded information history Dij (i=
As can be seen from the above explanation, the relationships 1 to 7) are such that the condition at the past line li is "1" in the truth table of Table 3, and the condition in Table 3 also extends to all lines 1 to 7. When the relationships shown in Table 3 are satisfied, the trigger signal Pti can be generated by the corresponding clock h.

Writing this as a logical formula, Ei ni(C7UDi7)n(C
6UD16)n...[(C,UDi,)...The first equation is obtained.

Here, "U" represents a logical sum, and "[" represents a logical product. The comparison results C, ~C7 are given to the parallel-serial register 7, and the second
As shown in the figure, C7,
The comparison results are read out in the order C6, . The OR gate 9 receives the recording control clock h as the other input, and therefore the flip-flops 8, .about.832 are once set at the beginning of each clock cycle h, .about.h, 2. This is the comparison result serial signal CS,
~CS. This is provided to set the flip-flops 8, . Incidentally, flip-flops 8 and 832 are set-priority flip-flops. On the other hand, the past 7 lines 1, ~ 1
7 recorded information Du~D, 7, D2, ~D27,..., D,
．． ~Di7,..., D3a~D327 are updated and stored in the memory 1 in FIG. 1, and Di, ~D in FIG.
It is read out repeatedly as represented by i7, and in each clock period h, to h, 2, it is read out serially starting from the past line.

Past 7 lines,~17 record information ○,. ~D, 7,…
, Di, .about., 7, . . . , D32, .about.D spot 7 are applied to reset terminals of flip-flops 8, .about.832. Therefore, at the end of each period, eg, h, of the recording control clock, the output of the flip-flop, eg, 8i, is the recorded information of the past line, eg, D, . , D, and 3 are all 0, and by synchronizing this output with the recording control clock h in the AND gates 11 and 11, the trigger signal Pt, ~P
It will be female. Therefore, the comparison result C in Table 2 above
,,C2,...,C7 respectively as past record line 1,,
12, . . . 17, past record information D, . ~
D, 7,..., ○1・~Di7,..., D spot, ~D
“0” between 827 and comparison result C,,C2,...,C7
Trigger signals Pt, .about.Pt32 are generated at the end of clock cycles h, .about.h, 2 when the information matches, and recording power pulses P, .about.P32 are raised. That is, as a method of sequentially executing the theory of the first equation at the clock hk (h=1 to 12), a flip-flop 8i is used, and a serial signal CSk of C, ~C, is input to the S input (set), By performing the above operation with D,j (i=7 to 1) at the R input (reset), E of the first equation can be obtained as an output. The output of this flip-flop 8 and the clock h
By synchronizing with the AND gate 11i, a trigger signal Pti which is a thyristor trigger clock including a signal for controlling the recording power pulse width is obtained. That is, every recording control clock h that controls the recording power pulse width, it is checked whether the recorded information history Dij (j=1 to 7) is a pattern permitted by the comparison result Ci (i=1 to 7), If the condition is satisfied, the rise of the recording power pulse is allowed at the recording control clock. Note that the trigger signals Pt, ~Pt32 are generated once and then regenerated in the subsequent clock cycle, but the rise of the recording power pulses P, ~P32 corresponds to the trigger signal Pu generated first from the rise of the power supply voltage HV. ~P
Since it depends on t32, there is no influence on the recording power pulse width.
Although this embodiment is an example in which the heat generating elements 1 to 132 are arranged in a line, it is also possible to use a serial printer etc. in which the heat generating elements are arranged in a matrix, by simply making the line feed correspond to the recording head feed. The same applies. In addition, in a high-density facsimile-sensitive V thermal recording device, for example, 32
It is customary to provide several tens of selectors to control each heat generating element as one selector unit. In such a case, the capacities of the memories 2 and 10 are increased, and the output is controlled so that each clock peripheral sum, ~h, 2 goes around for each selector, and the OR gate 9 and the AND gate 11
By using the other input as the selector clock,
It can be made to correspond. Furthermore, in some types of thermal recording devices, even if the recording interval time is the same, the required recording power pulse may differ somewhat depending on which line in the past was recorded. In such a case, memory 6
It is necessary to store the recording interval time for each line, and to compare the recording interval measurement time tw, to tw7 with the scheduled recording interval time w for each line. Also, the power supply voltage H
When a commercial voltage is used as V, it is necessary to make the clock intervals of the recording control clock h unequal so as to give approximately equal recording errors. Furthermore, changes in ambient concentration can also be accommodated by controlling the clock interval.
Furthermore, although the starting point of the recording power pulse was controlled in the above embodiment, the ending point can also be controlled. In this case, the recording interval time is shortened and the recording is read out from the memory 6 in synchronization with the recording control clock. . Furthermore, 1. Ato se
Considering the addition of c, the recording start reference time signal T
Therefore, the time interval is tw, 11.5hse
ckoT, 1To, tw2 11.5hsec=T2-To
,...tW? +1.8hsec=T7-T. Therefore,
Only the recording start reference time signal T may be used as input information to the recording interval measurement memory 4. In this case, the output of the recording interval measurement memory 4 is T, -To, T2 -T.
o, ..., T7 - To output the time interval itself, and in order to correspond to it, the stored contents of the memory 6 are uniformly set to 1.8
A simple method is to store a value larger by hsec. As is clear from the above description, the present invention uses the recording control clock period as a unit of control of the recording power pulse width, and uses the recording interval time common to each line and recording information unique to each heat generating element to record data. Since the thermal state is predicted, there is an advantage that high-speed recording of the planned concentration is possible with a relatively simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart thereof, and FIG. 3 is a block diagram for supplementary explanation of the measurement memory 4 in FIG. 1. 1...Heating element, 2...Memory, 3.
...And gate, 4...Measurement memory,
5...Comparator, 6...Memory, 7...
Parallel series register, 8...Flip-flop,
9...or gate, 10 memory, 11...and gate. Figure 3 Figure 1 Figure 2

Claims (1)

[Claims] 1. In a thermal recording device having multiple heat generating elements,
A record history memory that updates and stores the recorded information history up to the past recording time of a predetermined number of each heat generating element and that is repeatedly read out in synchronization with the recording control clock, and a recording interval measurement memory that updates and stores the measured recording interval time up to the recording time and is repeatedly read out in synchronization with the recording control clock; The recording interval memory is read in a predetermined order in synchronization with the recording control clock, and the magnitude relationship between the recording interval time of measurement and the recording interval time of the schedule is compared at each recording reference time in synchronization with the recording control clock. a means of comparison to
Inspecting for each recording control clock whether or not the recording information history is in a pattern acceptable to the comparison result of the comparing means, and if the pattern is satisfied, allowing the recording power pulse to rise at the recording control clock. 1. A heat-sensitive recording device comprising means for controlling a recording power pulse width of a heating element.