JPS6258914B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a thermal recording device, and particularly to controlling the recording power pulse width for recording at a predetermined density in a thermal recording device that records at irregular time intervals and at high speed. BACKGROUND OF THE INVENTION Recording density in thermal recording varies based on various factors. In a thermal recording device using a thermal head having a plurality of heating elements, which is the object of the present invention, the following two factors can be broadly classified. That is, one is a change in recording density mainly due to factors of the individual heat generating elements, and the other is a change in recording density due to factors that can be considered collectively for a plurality of heat generating elements. The former is the object of the present invention. It is known that in the thermal head used in the embodiments described later, each heat generating element radiates heat with a time constant of about 3 to 4 msec when the recording power pulse is interrupted. When a heat generating element is thermally driven with a recording power pulse having a time width of 1.8 msec, recording is made at the planned recording density, and the heat generating element returns to the base temperature level after about 10 msec, and remains in a heat storage state until then. It is in. Recording density in thermal recording is determined by thermal energy applied from a heat generating element to a coloring agent or a transfer agent. This thermal energy is determined by the recording power pulse and the heat storage state. That is, when thermally driven in a high heat storage state, dark recording results. Conventionally, in a thermal head that has multiple heat generating elements, control over changes in recording density caused by individual factors of the heat generating elements involves controlling the pulse width of the recording power pulse using a low resistor and a capacitor in the drive circuit of each heat generating element. We are taking measures to control it. Problems to be Solved by the Invention However, with this, as the number of heating elements increases, the number of adjustments increases, and the miniaturization of the drive circuit requires an analog circuit, so there are limits to IC implementation. On the other hand, even if control using resistors and capacitors is replaced with logic circuits, an arithmetic unit (ALU) is required for each heating element, and a thermal head with a large number of heating elements requires a huge number of gates. Or, it is necessary to have control conditions for each heating element individually. Therefore, if the structure of the head changes, or if the coloring agent or transfer agent is different, it is necessary to change all the conditions for each heating element, which is a drawback. For this reason, in a thermal recording device that uses a thermal head with a large number of heat-generating elements, it is necessary to wait for the heat-generating elements to drop to the base temperature level before starting the next recording, or to take measures to quickly lower the temperature to the base temperature level. Therefore, I have been recording the planned concentration. However, when high-speed recording with a recording period of about 2.0 msec or less is required, the above-mentioned method cannot be used, and the next recording has to be performed in a state of heat accumulation. Also, for example, in the G3 facsimile machine, the image signal is subjected to band compression, so the amount of data for one line varies depending on the recording pattern.
Furthermore, since the data speed of the transmission line is constant, the time for completing one line of data varies depending on the pattern to be recorded, and the recording cycle of each line of the recording device is not constant, so it is necessary to accommodate this. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a heat-sensitive recording device that can start recording at a predetermined density in a heat-storage state and can be applied even when the scheduled recording period for recording is not constant. Means for Solving the Problems The present invention provides a recording data time signal indicating that all recording data corresponding to each of the heat generating elements has been completed in a thermal recording device that has a plurality of heat generating elements and records at irregular intervals. a circuit for measuring the cycle of the data; a data memory for storing previously recorded data corresponding to each heating element; and a recording interval time memory for storing recording interval time corresponding to each heating element; If the old recorded data is black, the contents of the corresponding part of the recording interval time memory are rewritten to the above period and become the recording interval time, and if the old recorded data is white, the contents of the corresponding part of the recording interval time memory are rewritten to the above period. A circuit that rewrites the above-mentioned content and the above-mentioned cycle to a value that adds the above-mentioned period to the above-mentioned recording interval time, and a recording start reference time signal generated after the completion of rewriting the above-mentioned recording interval time memory, subtracts a count from a predetermined value. A counter that outputs a count value sequentially until it reaches zero, and when the counter starts subtracting, each of the above recording interval times is input in sequence, and a constant recording density is achieved according to the value. A circuit that outputs a recording power pulse width of a predetermined value as shown in FIG. A matching circuit is provided for each heating element, and extracts only the corresponding matching output from the matching outputs to start thermally driving the heating element, and generates the signal after a predetermined time from the recording start reference time signal. The present invention is a thermal recording device characterized by having a circuit that stops thermal driving in response to a recording end signal. Embodiment The present invention relates to a thermal recording device that simultaneously records dot lines on a recording paper running in a fixed direction by applying predetermined pulses to a plurality of heat generating elements arranged in a line. The outline will be explained with reference to FIGS. 6 and 7. FIG. 6 shows a recording example, where 1 ₁ to _{1 32} are heating elements, 51 is a recording paper, A is a running direction of the recording paper 51,
₁₉ to ₁₀ are dot lines simultaneously recorded by the heating elements ₁₁ to ₁₃₂ , respectively, circles _a1 , _a2 , etc. indicate black dots recorded on the recording paper 51,
The heating elements 1 ₁ to 1 ₃₂ are dot lines 1 ₉ , 1 ₈ ,
...1 Record one dot line at the same time in the order of ₁ ,
This shows that dot line ₁₀ is currently being recorded. FIG. 7 shows the driving pulses 1 1 and 1 ₂ for driving the heating elements 1 ₁ and 1 ₂ in FIG. 6, where an amplitude of ₁ records black and an amplitude of 0 records white (no driving). The recording start point is determined based on the interval and the progress of occurrence of black or white recording data, and the width of the pulse that drives the heat generating element is controlled within the range shown by the dotted line to record at a predetermined density. This will be explained in detail below using examples. FIG. 1 is a circuit diagram of a heat-sensitive recording device showing an embodiment of the present invention, and FIG. 2 is a time chart. In Figure 1, 32 heating elements 1 ₁ , 1 ₂
..., 1 _i , ... 1 ₃₂ record one line with 32 black and white pixels, and each heating element 1 ₁ to 1 ₃₂ consists of a heating resistor 1a and a switching transistor 1b, and each heating element 1 ₁ ~1 One end of ₃₂ is grounded,
A constant power supply voltage HV is applied to the other end. or,
Each heating element 1 ₁ to 1 ₃₂ returns to the base temperature level by leaving a recording interval of about 10 msec or more, and at the base temperature level, it is thermally driven by a recording power pulse having a time width of 1.8 msec. Therefore, the scheduled temperature is recorded. Therefore, the maximum recording cycle is about 1.8 msec. The recording interval measurement memory 2 stores recording interval times TM ₁ to TM corresponding to each heat generating element 1 ₁ to 1 ₃₂ as described later.
TM ₃₂ is quantized and measured using a recording control clock h (see FIG. 2) having a period of 150 μsec. 67 if recording interval time TM ₁ to TM ₃₂ is 10 msec or more
(=10.05 msec), and therefore the recording interval times TM ₁ to _{TM 32} take one value from 0 to 67.
The recording interval times TM ₁ to _{TM 32} are serially and repeatedly read out by the address counter 3 and applied to the conversion ROM 4 . In this embodiment, the address counter 3 is driven by a clock h/32 whose frequency is 32 times that of the recording control clock h. The conversion ROM 4 records in advance the relationship between the recording interval time and the recording power pulse width that give the planned density, and specifies the quantized recording interval times TM ₁ to TM ₃₂ as addresses as shown below. By doing so, recording power pulse widths PW ₁ to PW ₃₂ quantized at 150 μsec are output to the matching circuit 6. Here, the power pulse width is the time width of the power pulse that drives the heat generating element during recording.

[Table] Specifically, the conversion ROM 4 is configured as shown in FIG. That is, TM6 to TM0 are
The output of the recording interval measurement memory 2 specified by the address counter 3 is encoded in binary numbers.
The signal line for the most significant bit is TM6, and the signal line for the least significant bit is TM0. The output of the conversion ROM 4 is similar, with the most significant bit being PW3 and the least significant bit being PW0. Therefore, the values shown in the previous table are equivalent to the signals shown in the following table. This can be easily achieved by writing the value indicated by PW to the address corresponding to the TM in a commercially available ROM.

[Table] As explained above, the conversion ROM 4 serially and repeatedly outputs recording power pulse widths PW of PW ₁ to PW ₃₂ corresponding to recording interval times TM ₁ to TM ₃₂ . The recording power pulse width counter 5 is set to a count value of 12 by the recording start reference time signal TR inputted to the input S, and the recording power pulse width counter 5 is set to a count value of 12 by the recording start reference time signal TR inputted to the input _S.
In synchronization with the recording control clock h given to the count value 0, the count value 12~0
is output to the matching circuit 6. The coincidence circuit 6 compares the recording power pulse widths PW ₁ to _{PW 32} with the count value for each count value, and when they match, the coincidence output Pt ₁ , ..., Pt _i , ... , outputs Pt ₃₂ . The decoder 9 operates according to the truth table shown in the following table.

[Table] Gate groups 7 ₁ to 7 ₃₂ are outputs from the decoder 9 that decodes the output of the address counter 3, respectively.
Based on KP ₁ ~ KP ₃₂ , the above matching output Pt ₁ ~ Pt ₃₂
Predetermined coincidence outputs Pt' ₁ to Pt' ₃₂ are extracted from the gate groups 8 1 to 8 32 and distributed to corresponding gates of the gate groups 8 ₁ to _{8 32} . The matching outputs Pt' ₁ to Pt' ₃₂ of the gate groups 7 ₁ to 7 ₃₂ are as follows:
Takes a “1” output at any count value from 12 to 0 of the recording power pulse width counter 5,
At other values, "0" is output. The gate groups 8 ₁ to 8 ₃₂ have the above-mentioned coincidence outputs Pt' ₁ to 8 32 .
Pt' ₃₂ and recorded data D ₁ , . _. . , D i _, . That is, there is an output when the recorded data is black. The flip-flops ₁₁₁ to ₁₁₃₂ are set by the outputs of the gate groups ₈₁ to ₈₃₂ , and reset all at once by the recording end signal TS (see FIG. 2), and the heat generating elements 11 to 132 are set by the outputs of the gate groups ₈₁ to ₈₃₂ . The outputs of 11 ₁ to 11 ₃₂ are thermally driven only during the "1" period. 2 and 8 show time charts of the thermosensitive recording device shown in FIG. 1, and the operation of the circuit shown in FIG. 1 will be explained using FIGS. 2 and 8. In FIGS. 2 and 8, h is a recording control clock with a period of 150 .mu.sec, and the other pulses are synchronized with this clock. TD is a recording data time signal given externally, and is a recording data time signal.
D ₁ to D ₃₂ indicate the given time points, and the recording period td, which is the interval between them, is not constant. TR is a recording start reference time signal given from the outside, and is a very short fixed time after the recording data time signal TD is given (in this example, 1 hour later).
It is given to For example, when the recording data time signal TDa is applied, the data memory 10 takes in the applied recording data D ₁ to D ₃₂ . The recording interval measurement memory 2 finishes measuring the recording interval times TM ₁ to _{TM 32} between the recording data time signal TDa and the recording start reference time signal TRa, as will be described later. The above-mentioned recording interval times TM ₁ to TM ₃₂ are repeated for 12 clock periods at a rate of once per clock period in synchronization with the recording control clock h after the recording start reference time signal TRa is given as shown in FIG. Read out. Read recording interval time TM ₁ to TM ₃₂
is the recording power pulse width PW ₁ ~
It is converted to PW ₃₂ and repeatedly output in synchronization with the recording control clock h. On the other hand, the recording power pulse width counter 5 starts counting after receiving the recording start reference time signal TRa as shown in FIG. 8, and subtracts "1" from 12 in synchronization with the recording control clock h. That is, count values 12 to 0 are output in series. The coincidence circuit 6 calculates the count value and the recording power pulse width PW ₁ to _{PW 32} for each count value.
If they match, "1" is output. For example, in FIG. 8, heating elements 1 ₁ to _{1 3} and 1
Only the recording interval time TM ₁ to TM ₃ and TMi of _i are
Greater than 7.80msec and less than 9.90msec, i.e. TM
When the value of is between 52 and 66, the recording power pulse width counter 5 outputs "1" Pt ₁ , Pt ₂ , Pt ₃ and Pt _i in a period of count value CW of 11. Pt ₁ ~ Pt ₃₂
By synchronizing the decoded value of the address counter 3 indicating the position of the index i at the recording interval time TM _i , that is, the output KP _i of the decoder 9, with the gate 7 _i , the signal Pt′ _i of only the corresponding part is generated. obtain. In the example of FIG. 8, the gate 7 _i synchronizes with Pt ₁ , Pt ₂ , Pt ₃ and Pt _i inputted during the period when the count value is 11 and KP _i from the decoder 9. ′ Only _i is output. By matching this Pt' _i with the corresponding output D _i of the data memory 10 and the gate 8 _i , when recording D _i =1, that is, black, Pt' _i becomes the S input (set terminal) of the flip-flop 11 _i . is input. The flip-flop _11i starts thermally driving the heating element _11i at the end of the count value CW of 11, as shown by FFi in FIG. 2, and generates a recording end signal that is generated 1.8 msec after the recording start reference time signal TRa Ends at TS. Note that thermal driving of all other heat generating elements also ends at the time of this TS. FIG. 3 is a circuit diagram of the recording interval time measurement memory 2 shown in FIG. 21 is the recording interval time
Recording interval time memory for recording TM ₁ to TM ₃₂ , 2
2 is a set-priority flip-flop which is set by the recording data time signal TD and subsequently reset by the recording control clock h; 23 and 25 to 27 are respective gates; 24 is a data memory for storing old recorded data whose recording has just finished; 28 is an addition circuit that outputs the maximum value 67 when the addition result is greater than 67, and 29 is a recording data time signal TD.
is cleared to zero value, the recording control clock h is counted at 150μsec intervals, and the count value is 67 (=
A counter that stops counting when it reaches 10.05msec),
A latch circuit 30 receives the output of the counter 29 and latches it using the recording data time signal TD. Note that 3 is the address counter 3 shown in FIG. The operation of the circuit shown in FIG. 3 will be explained below. The gate 23 is opened by the set-priority flip-flop 22 for only one cycle of the recording control clock h, and during that time the recording interval time memory 21 and the data memory 24 are controlled by the address counter 3, and the recording interval time TM ₁ to TM ₃₂ and the previously recorded data D' ₁ to D' ₃₂ are read out and sent to the gate 25.
~Given to 27. Gates 25 to 27 allow the recording interval time TM ₁ to TM ₃₂ to pass when the old recorded data D' ₁ to D' ₃₂ are output as "0", and the old recorded data
D′ ₁ to D′ ₃₂ Outputs a 0 value in case of “1” output. On the other hand, the counter 29 is set to 0 by the recording time signal TDb immediately before the current recording data time signal TDa.
When cleared to a value, it begins counting the incoming record control clocks. Note that counting ends when 67 is counted. When the current recording data time signal TDa is input, the latch circuit 30 latches the output of the counter 29 at that time for one recording control clock. The respective outputs passing through the gates 25 to 27 and the output of the latch circuit 30 are added together by an adder circuit 28 and applied to a recording interval time memory 21. In this way, the recording interval time memory 2
What is stored in 1 is the recording interval time TM ₁ above.
~TM ₃₂ . FIG. 9 is a time chart showing the operation of FIG. 3, and the recording data Di is A,
In this example, B, C, . . . are input. counter 29
The vertical axis of the output shows the measured time, which actually has a step-like shape synchronized with the clock h, but is shown as a straight line for convenience. For example, the time between the recorded data time signal TD ₁ and TD ₂ measured by the counter 29
td ₂ is latched to the latch circuit 30 by TD ₂ ,
The latch circuit 30 outputs td ₂ ' (=td ₂ ) for 1 h. As explained above, td ₂ ′ is the recording interval time.
Used for rewriting TMi. The same applies to td ₃ ′, …, td ₄ ′. That is, the old recorded data Di′ is
Then, B is 1 (black), so TMi=td ₂ ′, and when Di′ is C, C is 0 (white), so the old TMi value td 2 ′ is added to td ₃ ′, and TMi=td ₂ ′. td ₂ ′+td ₃ ′, and similarly when Di′=D, TMi=td ₂ ′+td ₃ ′+
When td ₄ ′, Di′=E, TMi=td ₅ ′, when Di′=F
TMi=td ₅ ', and rewriting is performed sequentially. In addition
The above rewriting operation for TMi is executed when the value of the address counter 3 is i, as shown in the lower enlarged view of FIG. As explained above, the recording interval time memory 21
The content of is, if the previous recorded data D′ _i that has just finished recording is white during the period from the recorded data time signal TD to the recording start reference time signal TR (in this embodiment, one cycle of the recording control clock). is rewritten as the old TM _i +t′d, and in the case of black, it is rewritten as t′d. Here, t'd is the value of the output of the latch circuit 30. This shows that when a black signal is input after a white signal, the time for driving the heat generating element is longer than when a black signal continues. That is, the drive time of the heat generating element is controlled by taking into consideration the state of heat accumulation in the heat generating element in advance and also taking into consideration the fluctuation of the recording period td. In this way, the new recording interval time is stored in the recording interval time memory 21 at the time of the recording start reference time signal TR. FIG. 4 is a circuit diagram showing a second embodiment of the present invention, in which the conversion ROM 4 and the matching circuit 6 are replaced by a conversion ROM 4 and a matching circuit 6.
The difference is that a ROM 31 and a comparator 32 are employed, and the other configurations are the same. The conversion ROM 31 is
As shown in the following table, the recording power pulse width PW quantized at 150 μsec is used as an address, and the recording interval time value TW also quantized at 150 μsec is stored.

[Table] In this embodiment, the recording power pulse width counter 5
In each period of 3 to 12 of each count value CW, the comparator 32 detects recording interval time values TM ₁ to TM ₃₂ that are larger than the output of the conversion ROM 31, and thermally drives the corresponding heat generating elements 1 ₁ to 1 ₃₂ . This is what starts the process. Effects of the Invention As is clear from the above explanation, in the present invention, the recording power pulse width, which is scheduled to be, for example, 1.8 msec, is divided into equal parts, and recording is started at one of them according to the recording interval time. Because
Even in a recording apparatus in which the reception interval of recording data is not constant, there is an excellent advantage that fine density control can be performed. In the above embodiment, the time point at which recording starts is controlled, but almost the same effect can be obtained by controlling the time point at which recording ends. Furthermore, when a commercial power supply is used as the power supply voltage HV, it is necessary to use a recording control clock with appropriately non-uniform intervals. Furthermore, if the interval between the recording control clocks can be finely adjusted, it is possible to cope with power supply voltage effects, changes in ambient temperature, etc.
In addition, in FIG. 1, if the data memory 10 is configured to be read out in synchronization with the recording interval time measurement memory 2, the gate groups 7 ₁ to 7 ₃₂ and 8 ₁ to 8 ₃₂ can be combined into a group of three-input gates. It can also be substituted with .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart showing the signals in FIG. 1, FIG. 3 is a block diagram of the recording interval time measurement memory in FIG. 1, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. is the conversion ROM in Figure 1
4 is a supplementary explanatory diagram, FIG. 6 is a recording example for explaining the outline of the present invention, FIG. 7 is a driving pulse for driving the heat generating element in FIG. 6, and FIG. 8 is a time diagram showing the signal in FIG. 1. 9 is a time chart showing the signals of FIG. 3. 1 ₁ to 1 ₃₂ ... each heating element, 2 ... recording interval measurement memory, 3 ... address counter, 4 ... conversion
ROM, 5... Power pulse width counter, 6... Coincidence circuit, 7 ₁ to 7 ₃₂ ... Gate group, 8 ₁ to 8 ₃₂ ...
...Gate group, 9 ₁ to 9 ₃₂ ...Decoder, 10...
Data memory, 11...Flip-flop.

Claims (1)

[Claims] 1. In a thermal recording device that has a plurality of heat generating elements and records at irregular intervals, the period of a recorded data time signal indicating that all recorded data corresponding to each of the above heat generating elements has been completed is measured. a data memory that stores previously recorded data corresponding to each heat generating element; a recording interval time memory that stores a recording interval time corresponding to each heat generating element; and the previously recorded data. If it is black, the content of the corresponding part of the recording interval time memory is rewritten to the above period and becomes the recording interval time, and if it is white, the content of the corresponding part of the recording interval time memory is rewritten to the above period. A circuit that rewrites the recording interval time to a value obtained by adding the above period, and a recording start reference time signal generated after rewriting the recording interval time memory, starts subtracting counting from a predetermined value and zeroing it. A counter that sequentially outputs count values until the counter starts counting, and a predetermined recording density that is determined in advance by inputting each of the recording interval times in sequence at the start of the subtraction count of the counter, and according to the values. a circuit that outputs a recording power pulse width of a value equal to the value of the pulse width; a circuit provided for each heating element, which extracts only the corresponding matching output from the matching outputs to start thermally driving the heating element, and a recording end signal generated after a predetermined time from the recording start reference time signal; A thermal recording device characterized by having a circuit for stopping thermal drive.