JPS6023507B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including an insulated gate field effect transistor and a capacitor serving as an information storage section.

[Background of the Invention] As is well known, semiconductor memory devices equipped with an insulated gate field effect transistor and a capacitor serving as an information storage section are widely used for various purposes, but due to the remarkable increase in integration density in recent years, Accordingly, there is a strong demand for a reduction in the required area.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that requires a much smaller area and has a much higher integration density than conventional semiconductor memory devices.

[Summary of the invention]

In order to achieve the above object, the present invention provides a semiconductor memory device in which a plurality of capacitors utilizing grooves formed inward from a semiconductor substrate and a plurality of insulated gate field effect transistors are arranged in a matrix. There are things that form.

[Embodiments of the invention]

A conceptual diagram of the present invention is shown in FIGS. 1a and 1b.

The case of drain capacity is shown in a, and the case of inversion capacity is shown in b.
The gist of the present invention is to dig a pore 16 in the semiconductor substrate 4 and use the surface of the inner wall of the pore as a capacitor, thereby significantly expanding the area of the inner wall of the pore relative to the area of the opening on the substrate surface. It is characterized by being able to. In this way, the storage capacity can be expanded without increasing the planar area, and the disadvantages of multi-stage connections, which are the disadvantages of the conventional method, can be dramatically reduced. According to the conventional example, a capacity of 100mm□ is about 1
pF, but the pore in Figure 1 has an opening of □2 meters x 100 mm.
Since it is possible to easily form a depth of 50 Am, the area of the capacitor remains the same and the area of the critical plate surface can be reduced to 1/50.

In this example, the integration degree of at least 5M sound is realized with the same board area as the conventional one. Moreover, if the scale is the same, the area can be reduced to 1/50, and the effect of implementing the present invention is immeasurable. Next, the method for forming pores will be described.

An etching method using an aqueous solution of KOH is known from the related art, and the etching rate of the {111} plane of silicon is particularly slow. It is also possible to increase the speed. In other words, orientation-dependent etching (orientation
The {111} plane, which has the slowest etching rate, can be formed with high precision by using the etching method (indentetching). This explanation is shown in FIG. Because the purpose of the present invention is to form pores deep in the vertical direction, the surface of the substrate is in the {111} plane or its vicinity (hereinafter, when the {111} plane is referred to as the {111} plane, unless otherwise specified, the vicinity thereof is also included. is {11
0} within 20o from the surface. 20 for {110} plane
There must be no other low index planes within o). Second
As shown in the figure, etching mask hole side lines 17 are formed on the {110} plane.

As an etching mask, any material can be used as long as it is sufficiently slower than the etching rate of silicon;
2 is used. An etching mask hole with a width Lo is formed in this Si02 film, and then etched with an aqueous KOH solution. The etching rate and KOH concentration of the {110} plane are shown in FIG. 3. The dependence of the etching rate on KOH concentration is modest, but when the smoothness of the etched surface is taken into account,
A concentration of 0% or more is appropriate. For example, liquid temperature 80qCKO
If a solution with a H concentration of 40% is used, the etching rate is 1.25.
It becomes 1/min. When etching is performed for 60 minutes using this solution, the depth D of the etching hole becomes 75 mm. As shown in FIG. 2, the inner wall surface 18 of the etching hole is composed of a {111} plane, and the etching mask hole side line 7 is the intersection line of the {1 11} plane and the {110} plane [112].
Assuming 8 degrees from the direction, the larger a is, the more minute {111} planes will be on the inner wall surface. Although the diagram depicts an uneven surface with many steps, this is an atomically enlarged view; the actual inner wall surface is a mirror surface, and the schematic uneven surface shown in the diagram cannot be seen. Furthermore, the final width LF of the etching hole is generally expanded compared to the width Lo of the etching mask hole, and the amount of expansion strongly depends on a'.

Let the amount of enlargement be m and define it by the following equation. m=thousand
This m is the distance from the side line of the etching mask to the inner wall surface of the etching hole.

The relationship between this m and the value 8 normalized by the etching hole depth ○ is shown in FIG. 8 and m/D show a nearly linear relationship, and m is expected to be extremely small at 8:0.

In other words, it is shown that if the etching hole side line is exactly in the [112] direction, an etching hole with almost the same width as the etching mask hole width can be formed. In reality 8=0
It is not possible to use this condition. For example 0=lo
In the case of , if a hole with a depth of 75 m is formed as described above, m = 2.6 m. That is, even if the width of the cutting mass hole is 1 m, it expands by 2.6 mm at both ends, and the final width of the cutting hole becomes 6.6 Am. Although the etching method for forming pongee holes in carrying out the present invention has been described above, the present invention does not limit the etching method and does not limit the type of etching method.

The present invention will be explained below using detailed examples.

In addition, in the description of the present invention, the above-mentioned pongee hole forming etching is
DE (Orientation Dependent)
E is abbreviated as hing), and the detailed conditions are not specified each time. Further, since the structure of the present invention can use a drain capacitor (FIG. 1a) or an inversion capacitor (FIG. 1b), an example of the drain capacitor will be described first. FIG. 5 shows an embodiment of the present invention.

First, as shown in a, an etching hole 19 is formed in an insulating film (Si02 is often used) that serves as an etching mask on the substrate 4.
is formed by a photoetching method. Then O
A pongee hole 16 is formed by DE, and as shown in b, a substrate of the first conductivity type and a second conductivity type opposite to that of the first conductivity type substrate are removed by a known thermal diffusion or ion implantation method, except for the source region and the insulating film in the pore area. A region 5 is formed. As shown in c, the insulating film 6 is then exposed using a thermal oxidation method or the like, and an electrode connection hole 20 is formed using a phototing method or the like, and then a gate electrode 8 and a source electrode 7 are formed as shown in d. By doing so, the structure of the present invention shown in FIG. 1a can be realized. Another embodiment of the invention is shown in FIG.

The process up to step a is the same as the method shown in FIG. After that b
As shown in Figure C, a self-aligned electrode 21 is formed on a predetermined insulating film 6, and using this as a mask, a second conductivity type region 5 is formed by known ion implantation or thermal diffusion method as shown in Figure C.
The self-aligned electrode 21 may be made of a material that can withstand ion implantation or thermal diffusion.
High melting point metals such as are often used. Furthermore, on top of that, CVD (Chemical Vapor Depos)
tion) method and PSG (Phospho-silica) which is doped with phosphorus and boron.
Class) and Boro-SilicateGl
A second layer insulating film 22 typified by (ass) is deposited to connect the source region, the source electrode 7 connected to the self-aligned electrode 21, and the gate electrode 8. In this embodiment, the source region, the drain region, and the gate are formed in self-alignment, so that the device can be miniaturized. FIG. 7 shows another embodiment of the present invention.

As shown in a, an insulating film 6 is formed, and self-aligned electrodes 21 are formed in predetermined portions. Since this electrode is used as a mask for ODE etching, it must be compatible with the KOH aqueous solution, but the above-mentioned polycrystalline silicon, Mo, W, etc. are easily soluble. Therefore, it is necessary to further deposit an insulating film on the electrode 21 as well. Next, as shown in b, by ODE, Tsumugi hole 16
Then, using the electrode 21 as a mask, the insulating film 6 of the source part is formed.
remove. Thereafter, as shown in c, a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method,
A second layer insulating film 22 is deposited. Furthermore, as shown in d, an electrode connection hole 20 is formed by a photo-etching method, and a source electrode 7 and a gate electrode 8 are formed. In this embodiment, since the four gates, the hole, the drain, and the source gate are self-aligned, the device can be further miniaturized than the embodiments shown in FIGS. 5 and 6. At this time, the self-type electrode 21 is formed so as to surround the pongee hole 16, as shown in the plan view e.
The three embodiments of the present invention have been described above, and in the case of FIGS. 5 and 6, the drain gates are arranged in one direction.

As shown in FIG. 8, a second conductivity type region 5 which becomes a gate electrode and a source can be formed to surround the pongee hole 16. Furthermore, although all of the above three embodiments of the present invention have been explained using one element, the data line 13, which is the connection of the source region arranged in a matrix, and the word line 13, which is the connection of the gate, cross each other. . At this time, in the above three embodiments, the gate electrode 8 and the source electrode 7 cannot be separated within the same plane. To solve this problem, the surfaces of the substrates 4 may be brought together without connecting the source electrode 7 from the two-conductivity type region 5 of the source. However, in this case, there is a region 5 directly under the self-aligned electrode 21 which becomes the gate.
Therefore, in the case of FIGS. 6 and 7, it is necessary to form the source connection region 5 in advance in addition to forming the castle 5. For this purpose, a part of the insulating film mask 6 is removed and a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method, as shown in FIG. 9a, or the entire surface of the substrate is formed as shown in FIG. A method can be used in which after forming the region 5, the region 5 that will become the source region is left and the rest are removed.

FIG. 10 shows an embodiment of the present invention arranged in a matrix.

A is a case in which the source and gate are arranged in one direction, and b is a case in which the source is formed to surround the gate. Using the method described above, the second conductivity type region 5 serving as the source is used as a data line, and the self-aligned electrode 21 serving as the gate is used as a word line. At this time, it is necessary to electrically isolate the sources arranged in parallel, and a separation band 23 is formed between them. This separation band can be formed by increasing the thickness of the insulating film above it to 5000A or more, by adding impurities to this part to have the same conductivity type as the substrate, or by connecting the third electrode to the electrode 21 through the insulating film 6.
Several methods are known, such as forming a channel under the substrate and applying a voltage to prevent the formation of a channel on the substrate and the conductive state, but the present invention is not limited to these methods. .
FIG. 11 shows another embodiment of the present invention.

This uses the inversion capacitance b in Figures 1, 2, and 5, and forms a second conductivity type castle 5 that becomes a source as shown in a in Figure 11, and then as shown in b in Figure 11. Pores 16 are formed in predetermined portions by ODE. Further, after forming an insulating film 6 as shown in c, an electrode connection hole 20 is formed on the source, and as shown in d, a source electrode 7 and a gate electrode 8 are formed.
, a capacitive electrode 9 is formed, and the inner wall of the pongee hole is used as a capacitor. Another embodiment of the invention is shown in FIG.

In this method, the gate and source are formed by self-alignment. After forming the pongee hole 16 by ODE as shown in a, an insulating film 6 covering the entire surface is formed, and a self-aligned electrode 21 is formed in a predetermined position as shown in b. After forming the second conductivity type region 5 in the position, the second conductivity type region 5 is formed by using this as a mask by known ion implantation or thermal diffusion method. After that, the second
A layer insulating film 22 is formed, and the space electrode 7, gate electrode 8, and capacitor electrode 9 are connected through electrode connection holes as shown in d. By doing so, the source, gate, and capacitor electrode can be formed by self-alignment, which is effective for miniaturization. Another embodiment of the invention is shown in FIG.

In this method, the gate, source, capacitor electrode, and pore are formed by self-alignment.As shown in a, the self-aligned electrode 21 is formed by the method described above, and then this is used as a mask during ODE etching. As insulating film 6
After using this as a mask and performing ODE etching as shown in b to form a pongee hole 16, the inner wall of the pore is covered with an insulating film 6. Thereafter, as shown in c, the second self-aligned electrode 24 is attached, leaving a predetermined portion. Thereafter, a second conductivity type region 5 that will become a source is formed by known ion implantation and diffusion. Further, this region 5 may be formed before the second self-aligned electrode 24 is formed. After that, as shown in d, the second layer insulating film 22
After forming an electrode connection hole 20, the source electrode 7, gate electrode 8, and capacitor electrode are connected. This allows the electrodes to be formed in self-alignment with each other, which is advantageous for further miniaturization. Figure 14 shows a source with a different arrangement from Figure 13.
Another embodiment of the present invention is shown in which the gate capacitor electrode is formed by self-alignment. In addition to arranging the capacitor electrodes, sources, and gates in one direction as shown in FIGS. 15, 16, 17, and 18, they can also be arranged surrounding each other as shown in FIG. can.

Further, when a large number of elements are arranged in a matrix and a common source is to be used, the common source shown in FIG. 13 may be formed in advance as described above. The elements having this capacitive electrode can be arranged in a matrix as shown in FIG.

This is a configuration in which a capacitor electrode is added when using the drain junction capacitor shown in FIG. 10, and the gate electrode and capacitor electrode may be arranged alternately as shown in the figure. In this way, the matrix can be constructed without forming electrode connection holes, so that it can be miniaturized. In the description of the present invention, for convenience, the insulating film 6 is formed on the substrate surface and on the self-aligned electrode in the same manner, but a different insulating film may be used on each substrate.

Further, in the present invention, a {110}-plane silicon substrate is used,
Since vertical pongee holes cannot be formed on the surface of other low index planes (for example, {111} and {100}), the present invention has little effect in implementing the present invention. I like it.

[Effects of the Invention] As is clear from the above description, according to the present invention, the required area of a semiconductor memory device can be significantly reduced, and it is extremely effective in improving the integration density.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing the concept of the present invention, Fig. 2, Fig. 3,
Figure 4 is a diagram explaining the method of forming pores, Figures 5 to 15
The figures up to the figures are diagrams showing embodiments of the present invention. Guncho diagram chrysanthemum Z diagram already 3 times good 4 figure 5 figure 5 chrysanthemum 7 figure 8 figure good? Picture group ’

Claims (1)

[Claims] 1 A plurality of capacitors and a plurality of insulated gate field effect transistors serving as information storage sections are arranged in a matrix, and the capacitors are arranged on the surface of a pore formed from the main surface of the semiconductor substrate toward the inside of the substrate. 1. A semiconductor memory device comprising at least an insulating film and a capacitor electrode formed in layers.