JPS6023506B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and specifically relates to an insulated gate field effect transistor and a semiconductor memory device that is an information storage section.

[Background of the invention]

As is well known, insulated gate field effect transistors and
Semiconductor storage devices with a capacity serving as an information storage section are widely used for various purposes, but with the remarkable increase in integration density in recent years, there is a strong demand for a reduction in the required area.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that has a significantly smaller desired area of 4.0 mm and has a much higher integration density than the conventional one.

[Summary of the invention]

In order to achieve the above object, the present invention utilizes pongee pores formed inward from the main surface of a semiconductor substrate as a capacitor, and provides gate insulation of the insulated gate field effect transistor on the surface of the pores. It is formed by laminating an insulating film different from a film and an electrode.

[Embodiments of the invention] A conceptual diagram of the present invention is shown in FIGS. 1a and 1b.

The case of drain capacitance is shown in a, and the case of inversion capacitance is shown in b. The gist of the present invention is to drill a pongee hole 16 in the semiconductor substrate 4,
The purpose is to use the surface of the inner wall of this pongee hole as a capacitor.
It is characterized by being able to significantly enlarge the pore inner wall area relative to the area of the closed portion on the substrate surface. In this way, the storage capacity can be expanded without increasing the planar area, and the disadvantages of multi-stage connection, which were the disadvantages of the conventional method, can be dramatically reduced. According to the related example, a capacitance of 100 French m□ is about 1 pF, but the pongee hole in Figure 1 has an opening of 2〃m x 100 mm.
Since a depth of 50 rm can be easily formed with a depth of 50 rm, the area of the substrate surface can be reduced to 1/50 while the area of the capacitor remains the same.

In this example, an integration degree of at least 5 tones is achieved with the same board area as in the prior art. Furthermore, if the scale is the same, the area can be reduced to 1/50 by 4 mm vertically, and the effect of implementing the present invention is immeasurable. Next, the method for forming pores will be described.

An etching method using an aqueous solution of KOH is known from a related subject, but this etching rate is particularly slow for the {111} plane of silicon, and if appropriate conditions are selected, it is possible to etch 1/2 of the surface other than the {1 1 1} plane. 400 speeds are also possible. That is, orientation-dependent etching
The {111} plane, which has the slowest etching rate, can be formed with high precision using pendentetching. This explanation is shown in FIG. Since the purpose of the present invention is to form pores deep in the vertical direction, the surface of the substrate is in the {110} plane or its vicinity (hereinafter referred to as the {110} plane, unless otherwise specified, includes the vicinity thereof. teeth{
110} within 20o from the plane. In the case of a {110} plane, there must be no other low index plane within 20 degrees.
As shown in FIG. 2, etching hole side lines 17 are formed on the {110} plane.

As an etching mask, any material can be used as long as it is sufficiently slower than the etching rate of silicon;
2 is used. An etching mask hole with a width is formed in this Si02 film, and then etched with an aqueous KOH solution. FIG. 3 shows the measured values of the etching rate and KOH concentration of the {110} plane. The dependence of the etching rate on KOH concentration is small, but considering the smoothness of the etched surface, 2
A concentration of 0% or more is suitable. For example, liquid temperature 80℃KO
If a solution with an H concentration of 40% is used, the etching rate will be 1.25 m/min. When etching is performed for 60 minutes using this solution, the depth D of the etching hole becomes 75 m. As shown in FIG. 2, the inner wall surface 18 of the etching hole is {
111} plane, and the etching mask hole side line 17 is the intersection line of the {1 1 1} plane and the {1 10} plane.
2], the larger the number 8, the more the micro 4 {111} planes on the inner wall surface. Although the diagram depicts an uneven surface with many steps, this is an atomically enlarged view; the actual inner wall surface is a mirror surface, and the schematic uneven surface shown in the diagram cannot be seen. Furthermore, the final width LF of the etching hole generally expands compared to the width of the etching mask hole, and the amount of expansion strongly depends on 81.

Let the amount of enlargement be m and define it by the following equation. m ni 3; 3
[1} This m is the distance from the side line of the etching mask to the inner wall surface of the etching hole.

The relationship between this m and the value 0 normalized by the etching hole depth ○ is shown in FIG. 8 and m/D show a nearly linear relationship, and when 8=0, m is expected to be extremely small by 4.

In other words, the etching mass hole side line is exactly [112]
This shows that an etching hole with almost the same width as the etching mask hole width can be formed if the direction is oriented. In reality, the condition 8=0 cannot be used. For example 8
In the case of =lo, if an etching hole with a depth of 75 m is formed as described above, m = 2.6 m. In other words, even if the width Lo of the etching mask hole is 1Am, there are 2
．． The etching hole width is enlarged by 6 m increments, and the final etching hole width is 6.6 rm. Although the etching method for forming pongee holes in carrying out the present invention has been described above, the present invention does not limit the etching method and does not limit the type of etching method.

The present invention will be explained below using detailed examples.

In addition, in the description of the present invention, the above-mentioned pongee hole forming etching is
DE(OrientationDependentEt
The detailed etching conditions will not be specified each time. In addition, the structure of the present invention is a drain capacitor (Fig. 1a) or an inversion capacitor (Fig. 1b).
An example of the drain capacitance will be described first. FIG. 5 shows an embodiment of the present invention.

First, as shown in a, an etching hole 19 is formed in an insulating film (Si02 is often used) to serve as an etching mask on the substrate 4 by photo-etching. After that, pores 16 are formed by ODE, and as shown in b,
By removing the source region and the insulating film in the pores, a second conductivity type substrate opposite to the first conductivity type substrate is removed by a known thermal diffusion or ion implantation method.
A conductive type region 5 is formed. As shown in c, an insulating film 6 is then deposited by thermal oxidation or the like, electrode connection holes 20 are formed by photoetching or the like, and then gate electrodes 8 and source electrodes 7 are formed as shown in d. By doing so, the structure of the present invention shown in FIG. 1a can be realized. Another embodiment of the invention is shown in FIG.

The process up to step a is the same as the method shown in FIG. After that b
As shown in FIG. 3, a self-aligned electrode 21 is formed on a predetermined insulating film 6, and using this as a mask, a second conductivity type region 5 is formed by known ion implantation or thermal diffusion method as shown in FIG. The self-aligned electrode 21 may be made of a material that can withstand ion implantation or thermal diffusion.
High melting point metals such as O and W are often used. Furthermore, on top of that, CVD (Chemical Vapor Depo)
Si02 film by the SiO2 film and Phospho-silca film with phosphorus and boron added to it.
Glass) and spots G (Glass on the broadside ro-silica)
) is deposited to connect the source region, the sous electrode 7 connected to the self-aligned electrode 21, and the gate electrode 8. In this embodiment, the source region, the drain region, and the gate are formed in self-alignment, so that miniaturization of the device can be achieved. FIG. 7 shows another embodiment of the present invention. As shown in a, an insulating film 6 is formed, and self-aligned electrodes 21 are formed in predetermined portions. Since this electrode is used as a mask for ODE etching, it needs to be dissolvable in the KOH aqueous solution, but the aforementioned polycrystalline silicon, Mo, W, etc. are easily soluble. Therefore, it is also necessary to deposit the insulating film 6 on the electrode 21 as well. Next, as shown in b, a hole 16 is formed by ODE, and then the insulating film 6 in the source portion is removed using the electrode 21 as a mask. Thereafter, as shown in c, a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method.
is formed, and a second layer insulating film 22 is deposited. Furthermore, as shown in d, an electrode connection hole 20 is formed by photo-etching, and a source electrode 7 and a gate electrode 8 are formed. In this embodiment, since the four elements, the hole, the drain, the source, and the gate, are self-aligned, the device can be further miniaturized than the embodiments shown in FIGS. 5 and 6. At this time, the self-type electrode 21 is
As shown in the figure, it is formed so as to surround the pongee hole 16. The three embodiments of the present invention have been described above, and in the case of FIGS. 5 and 6, an example was used in which the drain and the gate are lined up in one direction.

As shown in FIG. 8, a second conductivity type region 5 that becomes a gate electrode and a source can be formed to surround the pongee hole 16. Furthermore, all of the above three embodiments of the present invention have been explained using one element, but when this element is arranged in a matrix, the data line, which is the connection of the source region, and the word lines 1 and 3, which are the connections of the gate, are connected to each other. intersect.

At this time, in the above three embodiments, the gate electrode 8 and the source electrode 7 cannot be separated within the same plane. To solve this problem, it is sufficient to align the surface of the substrate 4 without connecting the source electrode 7 from the second conductivity type region 5 of the source. However, in this case, the region 5 cannot be formed directly under the self-aligned electrode 21 which becomes the gate.
In the case shown in the figure, it is necessary to form the source connection region 5 in advance in addition to forming the region 5. For this, as shown in FIG. 9a, a part of the insulating film mask 6 is removed and a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method, but as shown in A method can be used in which after forming the region 5, the region 5 that will become the source region is left and the rest are removed.

FIG. 10 shows an embodiment of the present invention arranged in a matrix.

A is a case in which the source and gate are arranged in one direction, and b is a case in which the source is formed to surround the gate. Using the method described above, the second conductivity type region 5 serving as the source is used as a data line, and the self-aligned electrode 21 serving as the gate is used as a word line. At this time, it is necessary to electrically isolate the sources arranged in parallel, and a separation band 23 is formed between them. This separation band can be formed by increasing the thickness of the insulating film above it to 5000A or more, by adding impurities to this part to have the same conductivity type as the substrate, or by connecting the third electrode to the electrode 21 through the insulating film 6.
Several methods are known, such as forming a channel under the substrate and applying a voltage to prevent a channel from forming on the substrate and becoming conductive, but the present invention is not limited to these methods. . FIG. 11 shows another embodiment of the present invention. This uses the inverting capacitance b in Figures 1, 2, and 5, and is the 11th
As shown in a in the figure, a region 5 of the second conductivity type serving as a source is formed, and then, as shown in b, a pongee hole 16 is formed in a predetermined portion by ODE. Further, after forming an insulating film 6 as shown in c, an electrode connection hole 20 is formed on the source, and a source electrode 7, a gate electrode 8, and a capacitor electrode 9 are formed as shown in d, and the inner wall of the pongee hole is part is used as the capacity.
In addition to the present invention, an embodiment is shown in FIG.

In this method, the gate and source are formed by self-alignment, and after forming pores 16 by ODE as shown in a, an insulating film 6 covering the entire surface is formed, and a self-aligned electrode 21 is formed in a predetermined position as shown in b. After forming the second conductivity type region 5 in the position, the second conductivity type region 5 is formed by using this as a mask by known ion implantation or thermal diffusion method. Thereafter, a second layer insulating film 22 is formed as shown in c, and a source electrode 7 is formed as shown in d.
, the gate electrode 8 and the capacitor electrode 9 are connected through the electrode connection hole. By doing so, the source, gate, and capacitor electrode can be formed by self-alignment, which is effective for miniaturization. Another embodiment of the invention is shown in FIG.

In this method, the gate, source, capacitor electrode, and pongee hole are formed by self-alignment.As shown in a, after forming the self-aligned electrode 21 by the above method, this is used as a mask during ODE etching. As shown in b, an insulating film 6 is deposited on the surface and this is used as a mask for ODE.
After forming the pongee hole 16 by etching, the inner wall of the pongee hole is covered with an insulating film 6. Thereafter, as shown in c, the second self-aligned electrode 24 is attached, leaving a predetermined portion. Thereafter, a second conductivity type region 5 that will become a source is formed by known ion implantation or diffusion. Further, this region 5 may be formed before the second self-aligned electrode 24 is formed. Thereafter, as shown in d, a second layer insulating film 22 is formed and an electrode connection hole 20 is formed, after which the source electrode 7, gate electrode 8, and capacitor electrode 9 are connected. This allows the electrodes to be formed in self-alignment with each other, which is advantageous for further miniaturization. FIG. 14 shows another embodiment of the present invention in which source and gate capacitor electrodes are formed by self-alignment in a different arrangement from that in FIG. 13.

In addition to the method of arranging the capacitor electrode, source, and gate in one direction as shown in FIGS. 15, 16, 17, and 18, it is also possible to arrange the capacitor electrode, source, and gate in one direction as shown in FIG. Can be arrayed.

Further, when a large number of elements are arranged in a matrix and a common source is to be used, the common source shown in FIG. 13 may be formed in advance as described above. The elements having this capacitive electrode can be arranged in a matrix as shown in FIG. This is a configuration in which a capacitor electrode is added when using the drain junction capacitor shown in FIG. 10, and the gate electrode and capacitor electrode may be arranged alternately as shown in the figure.
In this way, the matrix can be constructed without forming electrode connection holes, so miniaturization can be achieved. In the description of the present invention, for convenience, the insulating film 6 was formed on the substrate surface and on the self-aligned electrode in the same way, but a different insulating film may be used on each substrate.

Further, in the present invention, a {110}-plane silicon substrate is used,
For other low-index planes, such as {111} and {100}, it is impossible to form pegholes that are substantially perpendicular to the surface, so the present invention has little effect. preferable.

[Effects of the Invention] As is clear from the above description, according to the present invention, the required area of a semiconductor memory device can be significantly reduced, and it is extremely useful for improving the integration density.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing the concept of the present invention, Fig. 2, Fig. 3,
Figure 4 is a diagram explaining the method of forming pores, Figures 5 to 15
The figures up to the figures are diagrams showing embodiments of the present invention. Tsutomu' figure 2 figure 3 figure younger brother 4 figure S prisoner figure 5 figure more 7 figure more 8 figure more? Zuta/. Figure number ′′ figure/2 figure '3 figure Aoi/4 fourth brother/S figure

Claims (1)

[Claims] 1. In a semiconductor memory device including a capacitor serving as an information storage section and an insulated gate field effect transistor, the capacitor is laminated on the surface of a pore formed from the main surface of the semiconductor substrate toward the inside of the substrate. What is claimed is: 1. A semiconductor memory device comprising at least an insulating film and a capacitor electrode formed by the pore, the insulating film formed on the surface of the pore being different from the gate insulating film of the field effect transistor.