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JPS6024592B2 - Manufacturing method of wide-gap emitter transistor - Google Patents
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JPS6024592B2 - Manufacturing method of wide-gap emitter transistor - Google Patents

Manufacturing method of wide-gap emitter transistor

Info

Publication number
JPS6024592B2
JPS6024592B2 JP50010494A JP1049475A JPS6024592B2 JP S6024592 B2 JPS6024592 B2 JP S6024592B2 JP 50010494 A JP50010494 A JP 50010494A JP 1049475 A JP1049475 A JP 1049475A JP S6024592 B2 JPS6024592 B2 JP S6024592B2
Authority
JP
Japan
Prior art keywords
layer
base layer
semiconductor
base
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50010494A
Other languages
Japanese (ja)
Other versions
JPS5185677A (en
Inventor
俊久 塚田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50010494A priority Critical patent/JPS6024592B2/en
Publication of JPS5185677A publication Critical patent/JPS5185677A/ja
Publication of JPS6024592B2 publication Critical patent/JPS6024592B2/en
Expired legal-status Critical Current

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Landscapes

  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 本発明はGa船・Ga,.Nxふ系ワイドギャップェミ
ッタトランジスタの構造とその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Ga ship, Ga... This article relates to the structure of an Nx wide gap emitter transistor and its manufacturing method.

ゲルマニウム、シリコンなかんずくシリコンはトランジ
スタを作るのに最も一般的な材料である。
Germanium, especially silicon, is the most common material for making transistors.

これに対し硯化ガリウム(GaAs)はシリコン、ゲル
マニウムに比較して禁制帯エネルギーが大きいので真性
半導体になる温度が高い。したがってGaAsトランジ
スタは高温で使用できることおよび高出力が得られると
期待される。またGa.笛の電子の移動度が大きいので
、高速性、高周波特性が良好であることが期待できる。
こうした特徴が期待されるにも拘らず、Ga公でつくっ
たトランジスタが実用になっていない原因は、シリコン
においては容易に実現できるベース、ェミツタの形成が
うまくいかないためである。またへテロ接合を用いたワ
イドギャップェミッタによりトランジスタの注入効率を
あげるという考えは、既にトランジスタが発明されてま
もなく指摘された事柄であるが、現在にいたるもまだ完
全に実施されたことがない。
On the other hand, gallium silicide (GaAs) has a higher forbidden band energy than silicon or germanium, so the temperature at which it becomes an intrinsic semiconductor is high. Therefore, it is expected that GaAs transistors can be used at high temperatures and provide high output. Also Ga. Since the mobility of electrons in the whistle is high, it can be expected to have good high speed and high frequency characteristics.
Despite these promising features, transistors made from Ga have not been put into practical use because it is difficult to form bases and emitters, which can be easily achieved with silicon. Furthermore, the idea of increasing the injection efficiency of transistors by using wide-gap emitters using heterojunctions was already pointed out soon after the transistor was invented, but it has not yet been fully implemented. .

これはへテロ接合の良好なものが得られなかったためで
ある。本発明の目的は以上述べた従来素子の難点をもた
ないトランジスタ、すなわちェミッタ注入効率が高く、
高速性に優れ、高出力が得られ、かつ高温まで使用可能
なGaAsヘテロ接合トランジスタを提供することにあ
る。
This is because a good heterojunction could not be obtained. The object of the present invention is to provide a transistor which does not have the drawbacks of the conventional elements mentioned above, that is, has high emitter injection efficiency.
The object of the present invention is to provide a GaAs heterojunction transistor that has excellent high speed performance, can obtain high output, and can be used up to high temperatures.

以下、本発明を実施例により詳しく説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.

第1図aは本発明の一実施例の断面を示したものである
。同図bは本トランジスタの表面を示したものである。
この構造のトランジスタをつくるにはまずn形Ga偽基
板1上にn形Ga餌2、p形Ca偽3、n形Gao.8
AI O.2As4を液相ェピタキシャル法により連続
的に成長させる。これらの層の厚さは最初のn型GaA
sが3山、ベースとなるp型Ga偽層が0.2ム、最後
のェミッタ層が2山である。最初のn形約aAs層2は
ベース層の厚さの再現性を良くするために成長させる。
直接ベース層であるp型GaAs層3を基板上に成長さ
せると厚さの制御が難しくなるからである。ェミッタ層
は一般にn形Ga,へNx船を成長させるが、xはここ
で0.2を採用した。この値はもう少し小さくても十分
の効果が期待される。ついで第1図aに示したようにp
層5を亜鉛の選択拡散により形成する。拡散は十分ベー
ス層となるp型GaAs層3に達するだけの深さに行な
う。図に示すようにベースを少し通り越す程度の拡散を
実際には行なった。拡散終了後ェミツタ、ベースへのコ
ンタクト6,7を第1図に示したようにとり、コレクタ
へのコンタクト8はn形Ga兆基板からとってトランジ
スタを形成した。第1図bはこのトランジスタの平面図
で、第1図aと同一部位は同一符号で示している。
FIG. 1a shows a cross section of an embodiment of the present invention. Figure b shows the surface of this transistor.
To make a transistor with this structure, first, on an n-type Ga pseudo substrate 1, an n-type Ga substrate 2, a p-type Ca pseudo 3, an n-type Gao substrate. 8
A.I.O. 2As4 is grown continuously by liquid phase epitaxial method. The thickness of these layers is the same as that of the initial n-type GaA
s has three peaks, the base p-type Ga pseudo layer has a thickness of 0.2 μm, and the final emitter layer has two peaks. A first n-type approximately aAs layer 2 is grown to improve the reproducibility of the base layer thickness.
This is because if the p-type GaAs layer 3 serving as the base layer is grown directly on the substrate, it becomes difficult to control the thickness. The emitter layer is generally made of n-type Ga, with Nx layers grown, but x was set at 0.2 here. A sufficient effect is expected even if this value is a little smaller. Then, as shown in Figure 1a, p
Layer 5 is formed by selective diffusion of zinc. Diffusion is carried out to a depth sufficient to reach the p-type GaAs layer 3 serving as the base layer. As shown in the figure, we actually performed diffusion to the extent that it slightly passed the base. After completion of the diffusion, contacts 6 and 7 to the emitter and base were made as shown in FIG. 1, and a contact 8 to the collector was made from the n-type Ga substrate to form a transistor. FIG. 1b is a plan view of this transistor, and the same parts as in FIG. 1a are designated by the same reference numerals.

なお10はェミッタ電極用パッドを示している。このト
ランジスタにおいてェミツタ接地電流増幅率3を測定し
たところB=500という高い値が得られた。
Note that 10 indicates a pad for an emitter electrode. When the ground emitter current amplification factor 3 of this transistor was measured, a high value of B=500 was obtained.

また高速性にも懐れた特徴が得られた。この例の如く、
ベース3を形成する半導体より禁制帯エネルギーの大き
い半導体4を用いてェミッタが形成されているため、ベ
ース領域からェミッタへの正孔の注入がなく、その結果
ヱミツ夕接合を通過する電流の中で電子電流の占める割
合が改善される。
It also has the characteristics of high speed. As in this example,
Since the emitter is formed using the semiconductor 4 which has a higher forbidden band energy than the semiconductor forming the base 3, there is no injection of holes from the base region to the emitter, and as a result, in the current passing through the emitter junction. The proportion occupied by electron current is improved.

即ち、ェミッタ効率を増大することができる。更に本発
明においてはベース領域とべ‐ス・コンタクト領域が同
一のェピタキシャル層内に設けられているため、ベース
に接続される実効的な直列抵抗が低くなり、トランジス
タの高周波特性に好ましいものである。
That is, emitter efficiency can be increased. Furthermore, in the present invention, since the base region and the base contact region are provided in the same epitaxial layer, the effective series resistance connected to the base is low, which is favorable for the high frequency characteristics of the transistor. .

以上述べたように本発明によるトランジスタは電流増幅
率が高く、高速性に優れ、高出力、高温動作可能といっ
た特徴を兼ねそなえたものでその実用的価値は非常に大
きいものがある。
As described above, the transistor according to the present invention has the characteristics of high current amplification, excellent high speed, high output, and high temperature operation, and has great practical value.

なお実施例においてはnpnトランジスタを対象とした
が、pnpトランジスタももちろん可能である。
Note that although the embodiment deals with npn transistors, it is of course possible to use pnp transistors as well.

また実施例のGaAsはGa,NA1xAsにて置き換
えることが可能であり、さらにGa,★AIxAs系半
導体を基本とする化合物半導体たとえばGa,すりxA
s,‐yPy(0<y<1)等で置き換えることも可能
である。
In addition, GaAs in the examples can be replaced with Ga, NA1xAs, and compound semiconductors based on Ga, *AIxAs semiconductors, such as Ga, AlxA
It is also possible to replace it with s, -yPy (0<y<1), etc.

さらに本発明の方法はGa粕ICの製造方法にも適用で
き、また発光ダイオードとの組合せにより新しい機能を
持たせることもできる点で極めて実用性の高いものであ
る。
Furthermore, the method of the present invention is extremely practical in that it can be applied to a method for manufacturing Ga-lees ICs, and new functions can be provided by combining it with light-emitting diodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示したものである。 図において1はn形Ga船基板、2はn形GaAs成長
層、3はp形GaAs、4はn形Gao.8AIO.2
As、5はp形Gao.&り0.2Asである。 6,7,8はそれぞれェミッタ、ベース、コレクタ電極
である。 10‘まェミッタ電極用パッドである。
FIG. 1 shows an embodiment of the present invention. In the figure, 1 is an n-type Ga carrier substrate, 2 is an n-type GaAs growth layer, 3 is a p-type GaAs layer, and 4 is an n-type GaO layer. 8AIO. 2
As, 5 is p-type Gao. &ri is 0.2As. 6, 7, and 8 are emitter, base, and collector electrodes, respectively. 10' is a pad for emitter electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 所定の半導体基板上にGa_1_−_xAl_xA
s(0≦x≦1)系化合物半導体ないし該半導体を基本
とする化合物半導体をもつてコレクタ層、ベース層、お
よび該ベース層と反対導電型を有し、且、該ベース層を
構成する半導体より禁制帯エネルギーの大きい半導体で
構成され、且、前記ベース層とヘテロ接合を構成するエ
ミツタ層を少なくとも含む複数層を積層成長させる工程
、該成長層の表面の所定領域より少なくとも該ベース層
に達する深さに該ベース層と同一導電型の不純物を選択
拡散せしめベースコンタクト用領域を形成する工程を有
することを特徴とするワイドギヤツプエミツタトランジ
スタの製造方法。
1 Ga_1_-_xAl_xA on a predetermined semiconductor substrate
A semiconductor comprising an s (0≦x≦1)-based compound semiconductor or a compound semiconductor based on the semiconductor, having a collector layer, a base layer, and a conductivity type opposite to the base layer, and constituting the base layer. A step of laminating and growing a plurality of layers made of a semiconductor having a higher forbidden band energy and including at least an emitter layer forming a heterojunction with the base layer, reaching at least the base layer from a predetermined region on the surface of the grown layer. 1. A method for manufacturing a wide gap emitter transistor, comprising the step of selectively diffusing impurities of the same conductivity type as the base layer to a depth to form a base contact region.
JP50010494A 1975-01-27 1975-01-27 Manufacturing method of wide-gap emitter transistor Expired JPS6024592B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50010494A JPS6024592B2 (en) 1975-01-27 1975-01-27 Manufacturing method of wide-gap emitter transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50010494A JPS6024592B2 (en) 1975-01-27 1975-01-27 Manufacturing method of wide-gap emitter transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP59072772A Division JPS6035570A (en) 1984-04-13 1984-04-13 Wide gap emitter transistor

Publications (2)

Publication Number Publication Date
JPS5185677A JPS5185677A (en) 1976-07-27
JPS6024592B2 true JPS6024592B2 (en) 1985-06-13

Family

ID=11751729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50010494A Expired JPS6024592B2 (en) 1975-01-27 1975-01-27 Manufacturing method of wide-gap emitter transistor

Country Status (1)

Country Link
JP (1) JPS6024592B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106724B1 (en) * 1982-09-17 1989-06-07 ETAT FRANCAIS représenté par le Ministre des PTT (Centre National d'Etudes des Télécommunications) Ballistic heterojunction bipolar transistor
JPS6010774A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Semiconductor device
JPS6050957A (en) * 1983-08-31 1985-03-22 Fujitsu Ltd Hetero junction bipolar semiconductor device
JPS60253267A (en) * 1984-05-29 1985-12-13 Toshiba Corp Hetero-junction bipolar transistor and manufacture thereof
JPS61182257A (en) * 1985-02-08 1986-08-14 Nec Corp Hetero-junction bipolar transistor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559830B2 (en) * 1973-01-24 1980-03-12

Also Published As

Publication number Publication date
JPS5185677A (en) 1976-07-27

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