JPS6024622B2 - Facsimile line control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile line control device in which the number of counters for providing write addresses and read addresses for a pair of memories included in a plurality of line corresponding units is reduced.

Plans are underway to reduce fees for recent facsimile lines by using, for example, the configuration shown in FIG. 1 in which long-distance offices are connected using high-speed facsimile dedicated lines.

In Fig. 1, 1 is a facsimile machine, 3 and 13 are toll office exchange machines, and 4 to 4n are transmitting side line correspondence units, and each line is checked to see if there is information to be supplied to each line. If there is any information, it will be output when an instruction is received from the buffer memory 6, which will be described later. Reference numeral 5 denotes a common encoder, which encodes and compresses the image signal supplied from the selected line corresponding section 4i.

A buffer memory (BM) 6 checks whether there is an image signal to be transmitted to each line corresponding section 4i via a line (not shown) connected to each of the line corresponding sections 4, to 4n, and
Each line of the image signal of the line corresponding section where the image signal exists is sequentially scanned, and the image signal of each line corresponding section is introduced into the encoder 5. In addition, this buffer memory (BM
) 6 is a function that stores the image information encoded by the encoder 5 in each line corresponding section, and when several lines have been accumulated, adds identification information of the line corresponding section and sends the image information to the receiving side. has. Based on the received identification information, the receiving side buffer memory 16 specifies, through a decoder, the line corresponding section to be received among the line corresponding sections 14, to 14n, for example, the line corresponding section 14, and also specifies the line corresponding section to be received subsequently. It has a function of introducing image information into the decoder 15.

Based on this identification information, the decoder 15 connects the line corresponding parts 14, . . .
Set one of the pair of lines connected to 14n to high level,
A signal obtained by decoding image information is supplied to the other side. Also, at this time, it has a function of sending out a clock in synchronization with the decoded signal. In the system having the above functions, the sending side, that is, the sending side facsimile (FAX-S) 1 passes through the telephone line changeover switch 2, enters the toll office exchange 3, and exchange is performed, and supports multiple facsimile lines. After one of the sections 4, to 4n is selected and code-compressed by the encoder 5, it is stored in a buffer memory (BM) 6, and transmitted to the buffer memory (BM) 16 on the receiving side via a high-speed transmission line 10.
After being decoded by the decoder 15 in the opposite direction to the sending side, it is transmitted to the receiving side's toll office exchange 13 through one of the predetermined line correspondence sections 141 to 14n and transmitted to the other party's facsimile (FAX-
R) 1 as an image signal. Note that this facsimile (FAX-R) 1 corresponds to one of the line corresponding parts 14, to 14n, and there are other parts n, although not shown.
- There is one facsimile machine. FIG. 2 shows the configuration of a known example of the line corresponding parts 4, to 4n on the transmitting side in this case.

Since these have the same configuration, they will be explained without subscripts. A pair of memories (MO
) 21 and (MI) 23 are provided, and by switching the input side switch SI and the output side switch S2, the image signal binarized by the demodulator is supplied to one memory stream via the switch SI, and the image signal is supplied to the memory stream on the other side. The contents of are sent to the encoder 5 via a three-state gate 25 which is line-specifically controlled via a switch S2. On the other hand, the counters 22 and 24 that give write addresses to the memories (MO) 21 and (MI) 23 switch the sampling clocks using the switches S3 and S4, and when the image signal is supplied to one memory via the image signal switch SI, the counters 22 and 24 respond accordingly. A write address is given by the counter corresponding to the other memory, and a clock is given to the counter corresponding to the other memory via an AND circuit 26 controlled by line designation from the encoder 5, and a read address is given to the counter corresponding to the memory. Switch S in the diagram
At positions I-S4, a clock crosses switch S3 and is sent to counter 22, giving a write address to memory (MO) 21 and a direct signal being stored via switch SI. On the other hand, a clock is sent from the encoder 5 to the counter 24 through the AND circuit 26 and the switch S4, and the clock is sent to the memory (MI) 2.
3 is given a read address and its contents are read out,
Encoder 5 via switch S2 and 3-state gate 25
sent to. In this case, the 3-state gate 25 and the AND
Line designation control is performed on the circuit 26 by the encoder 5. Although the switches SI to S4 are shown here in the form of ordinary switches, it goes without saying that these can be constructed using logic gates.

These structures are mounted on printed circuit boards as integrated circuits, but their miniaturization and simplification have become problems. In particular, the counters 22 and 24 are made up of a large number of gate circuits and account for a large proportion of the space factor, so if they can be reduced, they can be applied to multiple line support sections, so the benefits gained from miniaturization and cost reduction are It's big. SUMMARY OF THE INVENTION An object of the present invention is to provide a facsimile line control device that reduces the number of counters that provide write addresses and read addresses for a pair of memories included in a plurality of line correspondence units. In order to achieve the above object, the facsimile line control device of the present invention comprises a plurality of line corresponding parts and a common code part, and by providing a pair of memories in the line corresponding parts and switching, one memory can be used to receive data from a facsimile terminal. In the facsimile line control device, in which the contents of the other memory are read out in the common code section while the image signals of the other memory are being stored, one of the memories is switched to correspond to the image signal from the facsimile terminal in each line corresponding section. The present invention is characterized in that a common counter is provided for giving a write address to the memo file, and a common counter is provided for giving a read address to the other switched memo file to the common code section.

The principle and embodiments of the present invention will be explained in detail below.

FIG. 3 is a schematic explanatory diagram of an embodiment of the present invention. The structures in FIG. 2 are given the same numbers. A pair of memories (MO) 21 and (M
I) By providing 23 and switching switches SI and S2,
As shown in FIG. 2, the image signal is stored in one memo stream via the switch SI, and the contents of the other memo 1 are sent to the encoder 5 via the switch S2 and the 3-state gate 25 which is controlled by line designation. That's right. The difference in this figure is that the counters that give write addresses to the memories (MO) 21 and (MI) 23 are shared, and a common counter 31 is used, and in order to give read addresses, each line corresponding section 4 has a counter. This is because one common counter 35 is provided in the common encoder 5 without providing a common counter 35. Since reading speed can be increased, the line support section 4
While data is being written into one memory, it is easy to read data from the other memory across a plurality of line correspondence units 4 and complete the reading. By using the above configuration, it is sufficient to reduce the number of counters provided in the line correspondence section 4 by half and add one counter to the common encoder 5. In the figure, when the received image signal is supplied to the memory (MO) 21 via the switch SI, a write address is given by the counter 31 via the switch SII, and the memory (MI) 23
Since the counter 5 of the common encoder 5 is capable of high-speed reading as described above, while the write address is given from the counter 31 to one memory (MO) 21 and the received image signal is stored, The contents of the other memory (MI) 23 are read out from the counter 35 and the address is given to the common code unit 5 through the switch S2 and the 3-state gate 25.
sent to.

This procedure is performed by the line handling section 4. For example, if n=10, it is possible to read out all the memory contents from the address ADO shown by the solid line in the figure to the address AD9 shown by the dotted line controlled by the switches S12 and S14. These reading line designations are performed by line designation control from the common encoder 5. In this way, the write address of a pair of memories in the line corresponding section is given by a common counter provided for each line corresponding section, and the read address for all line corresponding sections is given by a common counter provided in the common encoder. You can make it in time. FIG. 4 shows a specific circuit example of an embodiment of the present invention based on the above-described principle. Components that are the same as those in FIG. 3 are given the same numbers.
In the figure, the image signal binarized by the demodulator is switched and input to memories (MO) 21 and (MI) 23 through AND circuits A1 and A3 corresponding to switch SI in FIG.

Also, in the memories (MO) 21 and (MI) 23, a clock synchronized with the sampling clock is connected to an AND circuit A2.
, A4 to the write (WE) terminal, and the sampling signal is input to the write (WE) terminal through A4. AND circuit A corresponding to switches SI1 and S13 in FIG.
5. Write address via A6 and OR1, OR2 to memory (MO) 21, (MI) 23 address (AD)
Give it to the terminal. Also, the counter 3 of the common encoder 5, which will be described later.
The read address supplied from V 5 is passed through a 3-state gate 48 controlled by a line designation signal to AND circuits A7 and A corresponding to switches SI1 and S13 in FIG.
The read address is given to the address (AD) terminals of the memories (MO) 21 and (MI) 23 via 8 and OR1 and OR2.

These pairs of AND circuits AI, A3, A2, A4, A5
, A6, A7, and A8 are simultaneously switched by adding the output and inverted output of a flip-flop (FF) 40 that inverts on/off states based on the output of the counter 31, respectively. The outputs of the memories (MO) 21 and (MI) 23 are connected to AND circuits A9, AIO and O corresponding to the switch S2 in FIG.
The signal is sent to the common encoder 5 via the R circuit OR3 and the three-state gate 25 controlled by the line designation signal. AND
Circuit A9, AI Kawama FF4 as well as the above-mentioned AND circuits
A zero output and an inverted output are added to perform switching control. With the above configuration of the line correspondence section 4, as described in the general explanation of FIG. During this time, other memories are given read addresses from the counter 35 of the common encoder 5, and the memory contents are read out and sent to the common encoder 5. Since high-speed reading is possible, reading is completed within this period across a plurality of line corresponding parts by the line designation signal. The configuration of the common encoder 5 is such that the output of the 3-state gate 25 is connected to the AND circuit 11 as shown on the right side of the figure.
is incremented by a clock and inputted to a change check circuit 41, and a run length counter 42 connected thereto calculates the white or black run length (number of continuous bits) of the received image signal.
When detecting a change point, the encoding information and the number of bits are obtained from the encoding conversion table stored in a fixed memory (ROM) 43 based on the image signal information and run length value, and are then input to the shift register 44 and set counter, respectively. Set it to 45.

Also, the start signal from the change point detection circuit 41 is counted together with the clock through the AND circuit A12 into the counter 35 to detect the end of encoding of one line, and the EOL signal is transferred from the line end signal (EOL) generation circuit 46 to the shift register. 44 and added to the encoded information. In the present invention, attention is paid to the counter 35 for detecting the end of the line, and the output of this counter 35 is input to the 3
Send via state gate 48 and AND circuit A7,A
Memory (MO) 21, (M
I) It is designed to be shared as the read address of 23. As mentioned above, this read address is switched and supplied to the 3-state gates 48 of the plurality of line corresponding parts 4, to 4n by the line designation signal, and moreover, reading and writing are performed at a higher speed of 2M or more than in the past. Therefore, during one writing operation in one memory of the line corresponding section, reading of the other memory of the line corresponding section can be completed, for example, with a hardness of two. As described above, according to the present invention, a common counter is provided in each line corresponding section to provide a write address to one of the memories switched in response to the image signal received from the facsimile terminal, and
A common cursor is provided for giving a read address to the other switched memory in the common code section and sequentially reading out the memories of the plurality of line corresponding sections at high speed.

As a result, the number of counters in the line corresponding section is halved, and the counters in the common code section can share the EOL detection counter as described above, which greatly simplifies the configuration and helps reduce the size and cost of integrated circuits. big.

[Brief explanation of the drawing]

Fig. 1 is a general explanatory diagram of a facsimile system to which the present invention is applied, Fig. 2 is an explanatory diagram of a conventional example, Fig. 3 is a schematic explanatory diagram of an embodiment of the present invention, and Fig. 4 is an explanatory diagram of an embodiment of the present invention. It is an explanatory diagram of a specific circuit example, and in the figure, 4, 4, 4M are line corresponding parts, 5 is a common code part, 21, 23 are memories, 25, 48 are 3-state gates, 31, 35 are counters, 40 is a flip-flop, 41 is a change point detection circuit, 42 is a run length counter, 43 is a fixed memory (ROM), 44 is a shift register, 45 is a set counter, 46 is an EOL generation circuit, A1 and A12 are AND circuits, ORI to OR3 indicates an OR circuit. Figure 1 Figure 2 Figure 3 Figure Dimensions

Claims (1)

[Claims] 1 Consists of a plurality of line corresponding parts and a common code part, and by providing a pair of memories in the line corresponding parts and switching, one memory stores image signals from a facsimile terminal while the other memory stores them. In the facsimile line control device for reading the contents of the common code section, a common counter is provided in each line corresponding section for giving a write address to one of the memories switched in response to the image signal from the facsimile terminal, and A facsimile line control device, characterized in that the code section is provided with a common counter that gives a read address to the other memory.