JPS6024967B2 - auto clear circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an auto-clear circuit in a (synchronous) logic system.

As an auto clear circuit, one that utilizes the rise of the power supply voltage is known.

For example, an OR time constant circuit is used to form an auto-clear signal at a logic level of "0" or "1" at a predetermined time when the power supply voltage rises, or a level shift circuit is used to form an auto-clear signal at the rise of the power supply voltage. These methods utilize the time difference between . These auto clear circuits are directly affected by the rise of the power supply voltage.
In the former case, under a power supply that rises slowly, and in the latter case under a power supply that rises quickly, a malfunction may occur in which a clear signal cannot be formed.

Further, a similar problem may occur even when the power is temporarily turned off. Furthermore, when the logic system is configured as a monolithic semiconductor integrated circuit, the former auto-clear circuit requires an OR time constant circuit to be configured with external components, and the latter auto-clear circuit is designed for clocks with low power supply voltage. In logic systems and the like, there is a problem in that it cannot be used because the level shift amount cannot be large.

This invention was made in order to provide an auto-clear circuit that operates reliably regardless of wire voltage.

This invention focuses on the fact that in a synchronous logic system, it is sufficient to determine when an auto-clear is being output based on the presence or absence of a clock pulse. The purpose is to detect whether or not the current state is present, and to form an auto-clear signal based on this.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes a timing pulse generation circuit including an oscillation circuit and a frequency dividing circuit (none of which is shown) that receives the output of the oscillation circuit.

An inverter circuit (m,
, IN2), a resistor (R.) and a capacitor (C,
) is input to an integrating circuit consisting of

This inverter circuit (IN,, IN2) and the integrating circuit (
R,,C,) constitute a delay circuit, the output of which is applied to one input of an exclusive OR circuit (EX), and the pulse output a is directly applied to the other input. This exclusive OR circuit (EX), together with the delay circuit described above, is for detecting the output of the pulse signal, and the output is sent to the P-channel MISFET (IN2) of the inverter circuit (IN2).
Insulated gate field effect transistor...Q,
), a resistor (R2), and a capacitor (C2
) is input to a smoothing circuit composed of

A clear signal (ACL) is obtained by inputting this smoothed output to a waveform shaping circuit composed of inverter circuits (IN4, IN5).

Note that this circuit uses complementary M to reduce power consumption of the circuit.
It is composed of ISFET.

The operation of this circuit will be explained next with reference to the operational waveform diagram shown in FIG.

When the power is turned on, the power supply voltage ycc is supplied to the frequency divider circuit 1, but its output remains at the logical value "0" or "1" for some time after the power is turned on, depending on the rise characteristics of the power supply voltage Vcc and the startup characteristics of the oscillation circuit. It will output one value of .

Now, as shown in the figure, it is assumed that the voltage is stabilized at "1" (power supply voltage level). Until the oscillation circuit starts operating after the power is turned on, the timing pulse generation circuit 1 outputs the above-mentioned bell. Next, when the oscillation circuit operates, the circuit 1 outputs a corresponding pulse signal.

This is connected to the inverter circuit (IN,...2) and the integral circuit (
R. , C,) becomes the delayed signal b. The output of the exclusive OR circuit (EX) which inputs the pulse signal a and the delayed signal b becomes "0" when both inputs are "0" or "1". , as shown in the same figure, only at the rising or falling edge of the pulse “
A signal c of 1'' is formed.

This allows pulse signal detection. In the rectifier circuit, the inverter circuit (IN3) is an exclusive OR circuit (
The output of Ex) is “1”, that is, the power supply voltage (Vcc
), it outputs "0", that is, substantially the circuit ground voltage (Vss).

P-channel MISFET Q. is the inverter circuit (N
3) is in a conductive state for a period when the output is "0". As a result, in the oscillation circuit, the output of the exclusive OR circuit (Ex) is “
The conductive state occurs only when the power supply voltage y
When cc is relatively high, a diode-connected enhancement type n-channel M is used as a rectifier circuit as shown in Figure 5.
ISFETQ can be used.

In this case, since the inverter (IN3) is not used, the number of circuit elements is reduced.

In the circuit shown in Figure 5, when the potential at point c reaches the "1" level, the electrode connected to point c of MISFET (Q4) acts as a drain, and the electrode connected to point d acts as a source. . As a result, the MISFET (Q) becomes conductive only when the potential at point c becomes "1". However, in the rectifier circuit shown in Fig. 5, the electrode connected to point d of MISFET (Q) when conductive as described above acts as a source, so the "1" level potential at point c is applied to MISFET (Q).
The voltage decreases by the gate-source threshold voltage of ET(Q) and appears at point d.

In other words, the level decreases. In the rectifier circuit shown in Figure 1,
Since the electrode connected to the point c of the MISFET (Q,) during conduction acts as a source, and the electrode connected to the point d acts as a drain, there is no level drop at the point d.

The rectifier circuit shown in FIG. 1 is suitable for a circuit with a low power supply voltage, such as a battery-powered electronic watch. A signal d can be obtained by smoothing the output of the rectifier circuit with a smoothing circuit.

In this case, the period t of the detection signal c and the OR time constant (C
By appropriately setting the relationship 2R2), the signal d
The rising speed of is controlled. A clear signal (ACL) can be formed by waveform rectifying this smoothed output d using the logic threshold voltage (Vt) of the inverter circuit (m4, IN5).

In other words, this clear signal (ACL) is
Until the smoothed output reaches the logic threshold voltage (Vt), a clear signal that becomes "0" is generated and a clear operation is executed.

In this embodiment, the clear signal is formed depending on whether or not the clear signal a is output, so unlike the auto clear circuit in the prior art, a reliable auto clear circuit is not affected by the rise of the power supply voltage. IJA operations can be performed.

In other words, after the power is turned on and the oscillation circuit and frequency dividing circuit start operating, the clearing operation is canceled after a certain period of time, thereby ensuring that the logic circuit to be cleared is cleared. I can do it.

As shown in FIG. 2, when the power is temporarily turned off, the clock pulse a is no longer output, the smoothed signal d is reduced, and when the power is turned on again, the above-mentioned clear signal is formed. I can do it.

In particular, even when the oscillation operation is temporarily stopped when the power is turned on, according to this embodiment circuit,
It is possible to form a clear IJ signal.

The present invention is not limited to the embodiments described above, but may use an integrating circuit instead of the inverter circuit (IN,, IN2), the integrating circuit (C, .R,), and the exclusive OR circuit (Ex). It's okay.

In this case, the differential output (C,) shown in FIG. 2 is obtained at the input of the smoothing circuit, and the pulse signal as described above can be detected.

That is, the differential output is output only when the input level changes. Furthermore, in a synchronous logic system for watches, in order to divide the reference oscillation frequency to form a 1-second pulse, as shown in Figure 3,
Focusing on the fact that it has an oscillation circuit 2 and a multi-stage frequency dividing circuit 3, input the division output of multiple values to an AND circuit or an OR circuit to detect all "1" or all "0". By doing so, the operation of the oscillation circuit can be detected. In other words, since the probability that all inputs will be in a predetermined pattern such as "1" or "0" when the power is turned on is extremely small, it is assumed that this will be directly smoothed and the clear release operation will not occur immediately. This is because it will be done.
Further, the above-described embodiment circuit can be used not only as an auto-clear circuit but also as a startup circuit when the power supply is turned off in a constant voltage output circuit, as shown in FIG.

This constant voltage circuit uses a p-channel MISFET (Q2) when the combined voltage (E) is a negative voltage, so that the electrode to which this supply voltage (E) is applied acts as a drain. Use source as output.

In order to make this source output a constant voltage, a reference voltage (
Vref) is applied, the upper source output voltage is applied to the inverting input terminal (1), and this voltage comparison output is applied to the above MISF.
This is applied to the gate of ET (Q2). Since this voltage comparison circuit 6 forms a comparison output whose output voltage matches the reference voltage (Vref) and applies it to the gate of MISFET (Q2), by making the reference voltage a constant voltage, , to obtain an output voltage that is a constant voltage ratio.

This voltage comparator circuit 6 is clock driven in order to reduce its power consumption.

Due to this clock drive, the gate control voltage of MISFET (Q2) is formed only intermittently, but by using the level holding effect of the gate capacitance (C3),
This allows the SFET (Q2) to perform constant voltage output operation. This circuit is not just for making the output voltage a constant voltage, but when using this output voltage as the power supply voltage of the electronic circuits 2 to 4, by making it a low voltage corresponding to the lowest operating voltage of the electronic circuit, This is an attempt to reduce the power consumption of electronic circuits.

In this circuit, even if the MISFET (Q2) is an enhancement type MISFET or a depression type MISFET, due to the substrate effect, the MISFET (Q2) is in an off state or close to an off state when the power is turned on.
On the other hand, since the voltage comparison circuit 6 is clock driven, it does not operate unless the oscillation circuit operates. Therefore, as shown in the figure, a starting circuit is required in a synchronous logic system in which the oscillation circuit 2, frequency dividing circuit 3, and timepiece control circuit 4 are operated with the constant voltage output.

Therefore, by using the auto clear circuit 5 described above and controlling the starting MISFET (Q3) provided in parallel with the MISFET (Q2) with its output, it can also be used as a starting circuit.

That is, by setting the power supply of at least the inverter circuit, which is the output circuit of the auto clear circuit, to the above supply voltage, from the time the power is turned on until the oscillation circuit 2 starts operating,
The MISFET (Q3) is turned on to supply power until the oscillation circuit 2 etc. start operating, and when the clock signal is formed and the voltage comparator circuit 6 is ready to operate, it is automatically turned off. This is because the electronic circuit can be operated based on the constant voltage output. In this embodiment, the constant voltage output circuit has a voltage supply terminal (MIS
A dummy MISFET and a source load resistor may be provided at the drain of the FET Q2, and the source output thereof may be applied to the inverting terminal input of the voltage comparison circuit 6.

This is because by making this dummy circuit equivalent to the MISFET (Q2) and the electronic circuit on its source side, the output voltage can be made substantially constant.

[Brief explanation of the drawing]

FIG. 1, FIG. 3, and FIG. 4 are circuit diagrams each showing an embodiment of the present invention. FIG. 2 is an operational waveform diagram of the circuit of FIG. 1. FIG. 5 is a circuit diagram of the rectifier circuit. 1... Clock generation circuit, 2... Oscillation circuit, 3... Frequency dividing circuit, 4... Clock circuit, 5... Auto Clear circuit, 6...Voltage comparison circuit. Younger brother 1 figure Younger brother 2 figure 5 figure 4 figure 5

Claims (1)

[Claims] 1 A circuit that takes the output of the timing pulse generation circuit as an input and detects a pulse signal, which detects a change in the output signal of the timing pulse generation circuit, and a detection circuit that takes the output of this detection circuit as input and detects the smoothed signal. An auto clear circuit comprising: a smoothing circuit that forms a clear signal; and a waveform shaping circuit that receives the output of the smoothing circuit as an input and forms a clear signal.