JPS6025895B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, for example, in a planar type semiconductor device, the substrate is covered with an insulating layer, the necessary diffusion etc. have already been performed, a barrier hole is provided on the substrate on which the element is formed, and aluminum is deposited on the entire surface, and then the photo processing method (PEP) and aluminum etching are applied. It is known as a general method to manufacture a semiconductor device by performing the following steps. Although aluminum (A) has various drawbacks, it is widely used because of its workability and ease of connection with semiconductor substrates such as Si. Recently, shallow diffusion has come to be used in semiconductor devices as integrated circuits become denser and faster.

In this case, a phenomenon occurs in which Si invades into the AZ at the Si layer (diffusion layer) outside the A, and shallow junctions are likely to be destroyed.
Regarding this, an attempt has been made to create a two-layer structure by interposing refractometal, which does not easily react with Si, under A.

However, as the wiring becomes more integrated, extremely thin wiring is required, and in a two-layer structure, it is extremely difficult to etch the upper and lower layers simultaneously. Further, for example, Mo or the like has the disadvantage that the lower part is over-etched because it is corroded excessively by the solution used to etch the A-line, which tends to cause peeling of the A-Z wiring.

Furthermore, even in the case of using two layers, there is a drawback that the wiring may be broken at the entrance of the electrode connection portion to the element.

The present invention has been made in view of the above circumstances, and a first object thereof is to provide a method for manufacturing a semiconductor device that allows effective wiring for a semiconductor element having a shallow diffusion layer or the like.

A second object of the present invention is to provide a method for forming a bulky semiconductor device that does not cause breakage or the like at barrier portions.

A third purpose is to provide a manufacturing method that facilitates multilayer wiring. The purpose of these methods is to selectively form a first metal layer on a substrate coated with an insulating layer having contact holes, and then form a second metal layer, which is a wiring layer, over the entire surface. This can be achieved by doing this.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below by way of an embodiment with reference to the drawings.

In the figure, A to D correspond to each manufacturing process and are shown in alphabetical order. First, a substrate 1 on which a semiconductor element is formed
A structure with a field insulating film 2 provided thereon is manufactured in step A. Here, a Si gate field effect transistor (hereinafter referred to as FET) will be described as an example of a semiconductor element. This Si gate FET consists of a source 3, a drain 4, a gate electrode 5, and a gate insulating film 6, and a channel is formed between the source 3 and the drain 4. Further, the gate electrode 5 is protected by a covering film 7. In this step, the surface of the substrate is exposed at the contact portion to the element.
Next, in step B, a first metal layer 8 is selectively formed on this contact portion. For example, using MoF6 as a source, vapor phase growth (CVD) of Mo is performed at a substrate temperature of 400 to 500° C. in nitrogen gas mixed with a certain amount of hydrogen at a ratio of 2/N220.05. At this time, the time was 3 to 15 minutes. As a result, M of 500 to 3000 angstroms
o grows on the substrate. Mo hardly grows on the field insulating film 2 and the covering film 7. In particular, when the temperature range is 4/N2 (volume ratio)*0.05 to 0.1, Mo does not grow on the insulating film at all and the molybdenum metal layer has excellent adhesion to the semiconductor substrate. was gotten. Furthermore, by introducing a larger amount of nitrogen gas in addition to MoF6 and hydrogen, it is possible to prevent the selectively grown molybdenum metal layer from becoming porous and to improve the uniformity of the metal layer. Here, if necessary, for example, 30
Mo can be grown to about 1# by performing precipitation for minutes. Of course, it is also possible to almost eliminate the step difference between the insulating film and the substrate surface. In this way, since the second metal layer, which will be described next, is connected to the flat portion, the phenomenon of contact failure will not occur. Moreover, there is a first layer on the insulating film.
The metal layer is not attached, and Mo can be applied only to the contact portion by self-alignment. Therefore, selective growth can be performed without changing the mask or the like. Next, in step C, a second metal layer, such as an aluminum layer 9, is formed over the entire surface.

This aluminum layer 9 is deposited using conventional vapor deposition techniques. In this way, the aluminum layer is directly deposited on the insulating film, and the aluminum layer is deposited on the contact (connection) portion with Mo interposed therebetween. Thereafter, in step D, the aluminum layer 9 is processed into a wiring shape according to a predetermined pattern. This completes the wiring 10 to the source and the wiring 11 to the drain. The electrical properties of the device thus completed were much more stable than when the wiring was made only of aluminum.

In the above example, the case where MoF6 was used as the source was explained, but similar results were obtained with WF6.

The same results were obtained even when other halides such as Ti, Cr, and Ta were used. Experimental results showing the relationship between the vapor phase growth conditions of molybdenum, tungsten, titanium, chromium, and tantalum fluorides, their selectivity, and film thickness are as follows.
For comparison, experimental results without using hydrogen are also listed.

Vapor phase growth of molybdenum Boiling point of MoF6: 0 degrees, evaporator temperature containing MoF6: room temperature, carrier gas supplied to the evaporator (
N2) amount: 10/min, gases added to the carrier gas containing MoF6: nitrogen and hydrogen, growth time: 2 pieces.

Boiling point of tungsten vapor phase growth WF6: 1 crab○, WF6
Temperature of the evaporator containing: room temperature, amount of carrier gas (N2) supplied to the outside of the evaporator: 5/min, gas added to the carrier gas containing WF6: nitrogen and hydrogen, growth time: 20 minutes.

Vapor phase growth of titanium Boiling point of TiF4: 284oo, temperature of evaporator containing TiF4: 18pi○, amount of carrier gas (N2) supplied to the evaporator: 80'/min, gas added to carrier gas containing TiF4: nitrogen and hydrogen, growth time:
20 minutes.

Vapor phase growth of tantalum Boiling point of TaF5: pine 9.5℃, evaporator temperature containing TaF5: i80℃, carrier gas (N2) amount supplied to the evaporator: 50'/min, in addition to the carrier gas containing TaF5 Gases used: nitrogen and hydrogen, growth time: 2 generations.

Vapor-phase growth of chromium Evaporator containing CrF4 Temperature: 14 pm, Amount of carrier gas (N2) fed to the evaporator: 50 gas/min, C [Gas added to the carrier gas containing F4:
Nitrogen and hydrogen, growth time: 206.

According to the present invention, the M
O, W, etc. can be precipitated, and A-line wiring can be effectively performed without causing penetration into shallow diffusion layers, etc., without changing the conventional process.

Incidentally, depending on the PEP used, it has been difficult to obtain similar effects due to limitations in mask alignment accuracy or etching technology. In the case of Mo, the thickness is several angstroms to 1000
The thickness of angstrom or more was particularly good. Another feature of the present invention is that it can be used in combination with the anodic oxidation method.

A-containing anodization is one method for multilayer wires, but with a two-layer structure of Mo and A, it is difficult to anodize the underlying Mo. Therefore, the present invention exhibits great merits when considering the combined use of A-ku anodic oxidation technology.

Further, although the embodiment has been given in the case of A-end wiring, it is not necessarily limited to A-end wiring. That is, the invention can be applied to the purpose of suppressing the reaction between metal and Si that causes phenomena such as penetration. Furthermore, if it is recognized that some degree of adhesion occurs on SiQ, the substrate temperature is not limited to 400 to 500 qC, and the substrate temperature may be raised higher, and the N2/N5 ratio may also be higher.

This can increase the growth rate. When hydrogen is not used, the metal growth concentration is limited to about 300 to 500A, but by adding hydrogen to the metal halide as in the present invention, the metal growth thickness can be increased to, for example, 1000A.
A or higher is possible. Also, instead of the nitrogen gas, Ar,
Of course, it is also possible to use an inert gas such as He.

The schematic explanatory diagrams in the drawings are process sectional views for explaining one embodiment of the present invention.

In the figure, 1... substrate, 2... field insulating film, 8... first metal layer, 9... second metal layer.

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Claims (1)

[Claims] 1. A step of forming an insulating layer in which an opening for wiring connection to the semiconductor element is provided on a substrate on which a semiconductor element is formed, and a metal halide of molybdenum, tungsten, titanium, chromium, or tantalum. and a selective vapor phase growth step in which a gas containing hydrogen is introduced and a heating temperature is set so that a metal layer is vapor phase grown on the surface of the semiconductor substrate surrounded by the opening, and the insulating layer is grown from above the metal layer. A method for manufacturing a semiconductor device, which comprises a step of forming a wiring layer extending upward. 2. A step of forming an insulating layer in which an opening for wiring connection of the semiconductor element is provided on the substrate on which the semiconductor element is formed, and a step of forming a metal halide of molybdenum, tungsten, titanium, chromium, or tantalum, hydrogen, and an inert element. a selective vapor phase growth step of introducing a gas containing gas and setting a heating temperature so that a metal layer is vapor phase grown on the surface of the semiconductor substrate surrounded by the opening; A method for manufacturing a semiconductor device, which comprises a step of forming a wiring layer.