JPS6026184B2 - Rotating body rotation speed display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rotational speed display device for a rotating body, and provides a device that can extremely easily confirm a deviation from a reference rotational speed.

Conventionally, this type of device, for example in a record player, uses a neon tube or the like that flashes at regular intervals to irradiate strobe lights placed near the outer periphery of the turntable, so that the rotation speed of the turntable reaches a reference level. When the rotation speed of the turntable reaches a rotation speed (for example, 33 1/3 pm), the strobe manuscript appears stationary, and when the rotation speed of the turntable becomes farther than the reference rotation speed, the strobe manuscript appears to flow in the rotation direction. A structure in which the strobe plate appears to flow in a direction opposite to the rotational direction when the rotational speed of the turntable becomes slower than the reference speed has been widely used.

However, with such a strobe-based rotation speed display device, if the rotation speed of the turntable deviates significantly from the standard rotation speed, it can be confirmed at a glance from a few places away. (If there is only a slight deviation, the movement speed of the strobe light slows down, so there was a problem that it was difficult to tell unless you got close and looked at it for a while.)

In addition, especially in record players, the need to provide a strobe screen near the outer periphery of the turntable imposes significant constraints on the design of the record player, and also increases the manufacturing cost of the turntable. It was the cause of the invitation.

The rotational speed display device for a rotating body of the present invention solves the above problems.

FIG. 1 shows a block diagram of a rotational speed display device for a rotating body according to an embodiment of the present invention.

In FIG. 1, the output of a crystal oscillator 2 having a crystal oscillator 1 is applied to a frequency divider 3, and the output of said divider 3 is monostable whose monostable time is controlled by the output frequency of said crystal oscillator 2. The voltage is applied to the input terminal X of the circuit 4, and the output terminal Z of the monostable circuit 4 is connected to a smoothing circuit consisting of a resistor 5 and a capacitor 6, and a resistor 7 and a resistor 8 having the same resistance value are connected in parallel with the capacitor 6. A voltage dividing circuit is connected thereto, and the non-inverting input terminal ga of the comparator amplifier 9 is connected to the voltage division midpoint of the voltage dividing circuit. On the other hand, capacitor 1
The output terminal J of the voltage controlled oscillator 11 having 0 is the input terminal X of a monostable circuit 12 having exactly the same configuration as the monostable circuit 4
2, the output terminal Z of the monostable circuit 12 is connected to a smoothing circuit consisting of a resistor 13 and a capacitor 4,
A resistor 15 and a variable resistor 16 are connected in parallel with the capacitor 4.
In addition, a voltage dividing circuit is constituted by a low resistor 17 having the same low resistance value as the low resistor 15, and the inverting input terminal 9b of the comparison amplifier 9 is connected to the midpoint of the variable resistor 16, which is the midpoint of this voltage division. is connected, and the output of the comparison amplifier 9 is applied to the control input terminal K of the voltage controlled oscillator 11.

The output signal of the crystal oscillator 2 is applied to the control input terminal Y of the monostable circuit 4 and the control input terminal Y2 of the monostable circuit 12.

Further, the output signal of the voltage controlled oscillator 11 is applied to a frequency divider 19 having a switch 18 for switching the frequency division ratio. The voltage is applied to one input terminal 21a of the device 21. On the other hand, a speed detector 23 is connected to the motor 22 connected to the rotating body, the output signal of the speed detector 23 is applied to an amplifier 24, and the output signal of the amplifier 24 is applied to the other side of the phase comparator 21. is applied to the input terminal 21b of the monostable circuit 25, and is also applied to the input terminal X3 of the monostable circuit 25.

The output terminal Z of the monostable circuit 26 is connected to one input terminal Q of the combining circuit 26, and the output signal of the phase comparator 21 is applied to the other input terminal R of the combining circuit 26.

The support terminal T of the synthesis circuit 26 is connected to the input terminal of a motor drive circuit 27, and the motor 22 is connected to the output side of the motor drive circuit 27.

Incidentally, the output signal of the frequency divider 19 is applied to the control input terminal Y3 of the monostable circuit 25. Now, the output signal of the voltage controlled oscillator 11 is also applied to one input terminal 28a of the AND gate 28, and the output signal of the frequency divider 3 is applied to the input terminal V of the trigger pulse generation circuit 29. The output terminal W of the trigger pulse generation circuit 29 is connected to the other input terminal 28b of the AND gate 28, and the output signal of the public ND gate 28 is connected to the monostable circuit 30.
The output terminal B of the monostable circuit 30 is connected to the input terminal of the frequency divider 31, and the output signal of the frequency divider 31 is applied to the input terminal 32a of the AND gate 32.
0 is applied to the input terminal V2 of the trigger pulse generation circuit 33 and the input terminal 34a of the AND gate 34. Z On the other hand,
The inverting input terminal 35b of the comparator amplifier 35 is connected to the output side of the smoothing circuit constituted by the low resistor 5 and the capacitor 6, that is, the connection point between the low resistor 5 and the capacitor 6. The non-inverting input terminal 35a of the comparator amplifier 35 is connected to the output side of the smoothing circuit, that is, the connection point between the low resistor 13 and the capacitor 14, and the output signal of the comparator amplifier 35 is connected to the output side of the AND gate 32. It is applied to the input terminal 32b and is applied to the input terminal 3 of the AND gate 34 via the inverting amplifier 36.
4b. Further, the output terminal W2 of the trigger pulse generation circuit 33 is connected to the input terminal X5 of the monostable circuit 37.
The output terminal Z of the monostable circuit 37 is connected to the input terminal of the inverting amplifier 38, and the input terminal 32c of the double-mounted ND gate 32 and the AND gate 3
4, and the AND gate 32
The output signal of the AND gate 34 is applied to an amplifier 39, and the output signal of the AND gate 34 is applied to an amplifier 40.
3 Furthermore, the output side of the inverting amplifier 38,
Light emitting diodes 44, 45, 46 used as display elements are connected to the output side of the amplifier 39 and the output side of the amplifier 40 via low resistors 41, 42, 43, respectively. 3. In the device shown in Figure 1, the low resistance values of low resistance 5 and low resistance 13 are the same, the capacitances of capacitor 6 and capacitor 14 are also the same, and the combined low resistance of low resistance 7 and low resistance 8 is the same. Anti 15, variable low resistance 16, low resistance 17
It is assumed that the synthetic resistance of is also the same value.
4 In the device shown in FIG. 1, a crystal oscillator 2, frequency divider 3, comparison amplifier 9, voltage controlled oscillator 11, frequency divider 19, frequency divider 20, phase comparator 21, amplifier 24, synthesis circuit 26, motor drive The circuit 27, the frequency divider 31, the comparison amplifier 35, the inverting amplifier 36, the inverting amplifier 38, the amplifier 39, and the four amplifiers can all be realized with a well-known circuit configuration, so a description of their configuration and operation will be omitted. However, in Figure 2, CMO
An example of the configuration of the crystal oscillator 2 using an inverting amplifier using an S-IC is shown. FIG. 3 shows an example of the configuration of the voltage controlled oscillator 11 using an inverting amplifier using a CMOS-IC. In b and c, three configuration examples of the composite circuit 26 using a low resistor or a low resistor and a capacitor are shown. In FIG. 2, terminal G is a signal output terminal, in FIG. 3, terminal S is a power supply voltage supply V supply terminal, J is a signal output terminal, and K is a control input terminal, and the control input terminal K is a P channel It is connected to the gate of enhancement type MOS transistor 47.

Note that the low resistor 4 connected between the drain and source of the P-channel enhancement type MOS transistor 47
8 is a low resistor for control, and the voltage controlled oscillator shown in FIG. 3 uses the P channel enhancement type M
The oscillation frequency is controlled by the OS transistor 47. FIG. 4a shows the most commonly used synthesis circuit, which sets the phase control gain by adjusting the low resistance ratio of the low resistance connected to the Q terminal and the low resistance connected to the R terminal.

The synthesis circuit shown in FIG. 4b is one in which the digital output signal obtained from the phase comparator 21 and the digital output signal obtained from the monostable circuit 25 are converted into direct current by a smoothing circuit and then synthesized. The synthesis circuit shown in FIG. 4c is a simplified example of the circuit shown in FIG. 4b.

In addition, switching circuits, gate circuits, etc. are inserted into the synthesis circuit when it is desired to provide the synthesis circuit with multiple functions.

Now, in Fig. 1, the trigger pulse generation circuits 29 and 33 generate differential pulses with a very short time width when the level of the input signal changes. 5 and 6, and an outline of the following operation will be explained.

In FIG. 5, an input terminal IA of a NAND gate A is connected to an input terminal V, and an output terminal OA of the NAND gate A is connected to an input terminal IC of an NNJD gate C.

On the other hand, the input terminal V is connected to the input terminal IE of the inverting amplifier E.
is connected, and the output terminal OE of the inverting amplifier E is NA
connected to the input terminal IB of the ND gate B, and connected to the input terminal IB of the ND gate B;
The output terminal OB of the gate B is connected to the input terminal ID of the NAND gate ○, and the input terminal IF of the inverting amplifier F.
It is connected to the.

Further, the other input terminal 2C of the NAND gate C is
The other input terminal 2D of the NAND gate D is connected to the other input terminal 2A of the NAND gate A and the output terminal OD of the NAND gate D, and the other input terminal 2D of the NAND gate D is connected to the other input terminal 2B of the NAND gate B. ' and is also connected to the output terminal OC of the NAND gate C.

Further, the output terminal OF' of the pre-inverting amplifier F is connected to the output terminal W. Now, the operation of the trigger pulse generation circuit shown in FIG. 5 will be explained using the signal waveform diagram of each part shown in FIG. 6.

In the signal waveform diagram of Fig. 6, the high potential state is defined as day,
Let L be a state of low potential (zero potential).

First, when the potential applied to the input terminal V is at L level,
The output level of each NAND gate is uniquely determined, and the NAND
ND gate A is set to day, NAND gate B is set to day, NAND gate C is set to L, and NAND gate D is set to day. That is, since the level of one input terminal IA of the NAND gate A is L, the output terminal OA of the NAND gate A is definitely set to day.

If the NAND gate C is on, i.e. its output terminal O
Assuming that the level of C is day, the level of its input terminal 2C must be L.

In order for the level of the input terminal 2C of the NAND gate C to be L, the level of the output terminal OD of the NAND gate D must be L, and this means that the input terminal ID of the NAND gate ○ is This means that the input terminal IB of the NAND gate B must be at L level in order for the input terminal ID of the NAND gate D to be at a low level. However, since the level of the input terminal V is low, the level of the input terminal IB of the NAND gate B is low.

That is, when the level of the input terminal V is L, the NA
It is impossible for the level of the output terminal OC of the ND gate C to become low, and it is always low.

Now, as shown in FIG. 6V, if the level of the input terminal V suddenly rises and moves from L to
Since the level of input terminal 2A of
The level of the output terminal OA of the ND gate A changes from 1 to 2, and at the same time, the level of the output terminal OC of the NAND gate C also changes from L to 1.

As a result, the level of the input terminal 2D of the NAND gate D changes from L to 1, so the level of the output terminal OD of the NAND gate D changes from 1 to L, and the level of the output terminal OA of the NAND gate A changes from L to 1. Back to the day.

These operations end instantaneously, and the NAND gate A
As shown in FIG. 6A, the level of the output terminal OA becomes very short at the moment the input level changes from L to L, and changes from 1 to L for a period of time.

While the level of the input terminal V is maintained, the sixth
As shown in Figures B, 6C, and 6D, the level of the output terminal OB of the NAND gate B is 1, the level of the output terminal OC of the NAND gate C is 1, and the level of the output terminal OD of the NAND gate D is 1. I'm getting used to L. At the moment when the level of the input terminal V suddenly drops and changes from 1 to 0, the level of N
Since the level of the input terminal 2B of the AND gate B is set to 1, the level of the output terminal OB of the NAND gate B shifts from 1 to 0, and the level of the output terminal OD of the NAND gate D changes from 1 to 2. rise in the day.

At this time, the level of the output terminal OB of the NAND gate B is very short and changes from 1 to 0 for a period of time. While the level of the input terminal V is held at L, as mentioned above, the level of the output terminal OA of the NAND gate A is 1, the level of the output terminal OB of the NAND gate B is 1, and the level of the output terminal OB of the NAND gate B is 1, 2,
The level L of the output terminal OC of the AND gate C and the level of the output terminal OD of the NAND gate D are at the same level.

After that, the same operation is repeated every time the level of the input terminal V changes from L to day or from day to day, and eventually,
When the level of the input terminal V changes as shown in FIG. 6V, the level of the output terminal OA of the NAND gate A, NA
Changes in the level of the output terminal OB of the ND gate B, the level of the output terminal OC of the NAND gate C, and the level of the output terminal OD of the NAND gate D are shown in FIG. 6A, FIG. 6B, and FIG.
It becomes as shown in FIG. 6C and FIG. 6D.

That is, due to a positive change in the input signal, the NAND
A negative trigger pulse is generated at the output terminal OA of the gate A, and a negative trigger pulse is generated at the output terminal OB of the NAND gate B due to a negative change in the input signal.

In the trigger pulse generation circuit shown in Fig. 5, the input terminal IF of the inverting amplifier F is connected to the output terminal OB of the NAND gate B, and the output terminal OF of the inverting amplifier F is connected to the output terminal W. , a signal waveform Z as shown in FIG. 6W appears at the output terminal W. Next, among the blocks shown in Fig. 1, monostable circuits 4, -12, 25, 30, and 37 all operate in the same way as a monostable multipipulator, but their input terminals × It generates an output signal having a monostable circuit corresponding to an arbitrary cycle of the signal applied to the control input terminal Y during one cycle of the signal applied to the control input terminal Y.
FIG. 8 shows a basic configuration example, FIGS. 8 and 9 show signal waveform diagrams of each part, and FIGS. 10 and 11 show other configuration examples and signal waveform diagrams of each part, respectively.

In Fig. 7, the signal input terminal × in Fig. 1 has two inputs N
The input terminal 2a of the AND gate a is connected, and the output terminal oa of the 2-input NAND gate a is connected to the input terminal 2b of the 2-input NAND gate b.
It is connected to the input terminal 2c of the ND gate c, and the two inputs N
The output terminal ob of the AND gate b is connected to the input terminal la of the 2-input NAND gate a, and further connected to the 3-input NAND gate a.
It is connected to the input terminal 2f of the D gate f.

Further, the second signal input terminal Y, which is the reference signal input terminal, is connected to the input terminals 4c and 2 of the 4-input NAND gate c.
The input terminal 2j of the input NAND gate j and the input terminal ln of the inverting amplifier n are connected, and the input terminal 2g of the 2-input NAND gate g and the input terminal 2m of the 2-input NAND gate m are connected to the output terminal ON of the inverting amplifier n. It is connected.

Furthermore, the output terminal oc of the 4-input NAND gate c is connected to the input terminal 2d of the 2-input NAND gate d, and the output terminal od of the 2-input NAND gate d is connected to the input terminal 1g of the 2-input NAND gate g. and is connected to the input terminal 3e of the 3-input NAND gate e,
The output terminal oe of the 3-input NAND gate e is connected to the input terminal ld of the 2-input NAND gate d, as well as the input terminal lb of the 2-input NAND gate b and the input terminal lc of the 4-input NAND gate c. ing. The output terminal 0g of the 2-input NAND gate g is connected to the input terminal 2h of the 2-input NAND gate h, and the output terminal oh of the 2-input NAND gate h is connected to the input terminal li of the 2-input NAND gate i. , is connected to the input terminal 3i of the 3-input NAND gate i and the input terminal 11 of the 2-input NAND gate, and the output terminal oi of the 3-input NAND gate i is connected to the 2-input NAND gate i.
It is connected to the input terminal lh of the AND gate h, and
It is connected to the input terminal 10 of the inverting amplifier ○, and the output terminal 00 of the inverting amplifier ○ is connected to the signal output terminal Z.

Further, the output terminal oj of the 2-input NAND gate i is 2
The output terminal ok of the 2-input NAND gate k is connected to the input terminal 2k of the input NAND gate k, and the output terminal ok of the 2-input NAND gate k is connected to the 2-input NAND gate k.
It is connected to the input terminal lm of the D gate m, and is also connected to the input terminal 21 of the two-input NAND gate m and the third input terminal lm.
It is connected to the input terminal lf of the input NAND gate f, and the output terminal 01 of the input NAND gate is connected to the input terminal lf of the input NAND gate f.
1M input terminals are connected to the ND gate k, and the 2 inputs N
Output terminal of AND gate m. om is the 3-input NAND
connected to the input terminal 2e of the gate e and the input terminal 2i of the 3-input NAND gate i;
The output terminal of of the gate f is the 3-input NAND gate e.
input terminal le and the 3-input NAND gate i
is connected to the input terminal li of.

Now, to explain the operation when the signal waveforms shown in FIG. 8 are applied to the signal input terminals X and Y of the monostable circuit shown in FIG. 7, first, the time t=t
Since the levels of the X and YO terminals are L at point o, the output level of NAND gate a is 1, and NA
The output level of the ND gate c, the output level of the NAND gate f, and the output level of the NAND gate j are also all 1.

Also, NAND gate e and NAND gate i are at time t=
t.

Since they were previously reset by NAND gate m, their output levels are both at day. Therefore, the output levels of NAND gate b and NAND gate d are both L. On the other hand, the output level of inverting amplifier n is 1, but since the output level of WAND gate d is L, the output level of NAND gate g is day, N
The output level of AND gate h becomes L, and thereby the output level of NAND gate k becomes L.

Further, the output level of the NAND gate m is 1, and the output level of the inverting amplifier ○ is L. Time t = Riko, X
NAND gates a, c, e, f, g, whose terminal signal level changes from L to day, but whose output level becomes day
1, 1, 1, and m all have other input terminals whose level is L, so the output level of each NAND gate does not change.

At time t=la', when the signal level of the Y terminal shifts from L to 1, the input terminal l of the NAND gate c up to that point
Since the levels of c, 2c, and 3c are days, the NAND
The output level of gate c shifts from 1 to 0.

At this moment, the output level of NAND gate d changes from L to 1, the output level of NAND gate e changes from 1 to L, and this causes the output level of NAND gate b to change to L.
At the same time, the output level of the NAND gate a shifts from day to L.

When the output level of the NAND gate a shifts from day to low, the output level of the NAND gate c returns from low to day. Figure 8 a, b, c, d, and e are each NAND
It shows changes in the output levels of gates a, b, c, d, and e.

At time t=W, when the signal level of the Y terminal shifts from 1 to 1, the level of the input terminal 1g of NAND gate g has reached 1 by then, so the output level of the NAND gate g becomes Shift from day to L.

As a result, the output level of the NAND gate h changes from L to 1, and at the same time, the output level of the NAND gate i changes from 1 to 1.

Figure 8 g, h, and i are NAND gates g, h, and i, respectively.
This shows the change in the output level.

At time t=riko, the signal level of the × terminal shifts from 1 to 2, and as a result, the output level of NAND gate a shifts from L to 2, but the output level of NAND gate e remains at L. So NAND gate b and NA
The output level of ND gate c does not change. At the same time, the signal level of the Y terminal changes from L to
The output level of the ND gate g changes from L to 2.

Furthermore, since the level of the input terminal lj of the NAND gate j has been set to 100 until then, the output level of the NAND gate j simultaneously shifts from 1 to 0, and thereby the NAND gate
The output level of the ND gate k changes from L to 1, and at the same time, the output level of the NAND gate 1 also changes from 1 to L.

Figure 8 i, k, 1 are NAND gates i, k, 1, respectively
This shows the change in the output level. At time t=W, when the signal level of the Y terminal shifts from 1 to 2,
The output level of NAND gate m transitions from 1 to 2, which causes the output levels of NAND gate e and NAND gate i to transition from L to 2. Further, the output level of the NAND gate j also shifts from L to day.

When the output level of the NAND gate e shifts from L to 11, the output levels of the NAND gates b and d also shift from 1 to 11, and as the output level of the NAND gate i shifts from L to 11, the output level of the NAND gate h shifts from L to 11.
The output level of NAN also shifts from day to low, which causes NAN
The output level of the D gate shifts from L to day, and at the same time it changes to N.
The output level of AND gate k shifts from 1 to 0.

When the output level of the NAND gate k shifts from 1 to 2, the output level of the NAND gate m returns from L to 1, but since the other input terminals of NAND gates e and i have already become L, Output level does not change.

FIG. 8m shows the change in the output level of the NAND gate m.

Further, a signal waveform as shown in FIG. 8 Z appears at the signal output terminal Z.

Now, at time t=t6, the signal level of the Y terminal changes from L to day, but the NAN whose output level is day
Since the D gates a, c, e, f, g, 1, j, 1, and m all have other input terminals whose level is L, the output level of each NAND gate does not change.

When the signal level of the X terminal changes from L to 1 at time t=, the input terminal lc of the NAND gate c up to that point
, 2c, and 3c are at day, so the output level of the NAND gate c shifts from day to L.

At this moment, the output level of NAND gate d changes from L to 1, the output level of NAND gate e changes from 1 to L, and this causes the output level of NAND gate b to change to L.
At the same time, the output level of the NAND gate a shifts from day to L.

When the output level of the NAND gate a changes from 1 to 1, the output level of the NAND gate c returns from L to 1. When the signal level of the Y terminal changes from 1 to 1 at time t=1, the level of the input terminal 1g of the NAND gate g has reached 1 by then, so the output level of the NAND gate g changes. moves from Sun to L.

As a result, the output level of the NAND gate h shifts from L to 1, and at the same time, the output level of NAND gate j shifts from 1 to L.

At time t=1, the signal level of the Y terminal changes from L to 1, and thereby the output level of the NAND gate g changes from L to H'.

Also, since the level of the input terminal lj of the NAND gate i has reached 100 by then, the output level of the NAND gate i simultaneously shifts from 20 to 200, and thereby
The output level of the AND gate k changes from L to H', and at the same time, the output level of the NAND gate also changes from 1 to L.

At time t=t, o, the signal level of the X terminal changes from 1 to L.
, the output level of NAND gate a changes from L to 1, and at the same time, when the signal level of the Y terminal changes from 1 to L, the output level of NAND gate m changes from 1 to L. NAND gate e and NA
The output level of ND gate i shifts from L to 2.

Further, the output level of the NAND gate i also shifts from L to 2.

When the output level of the NAND gate e shifts from L to day, the output level of NAND gates b and d also shifts from H to L, and as the output level of the NA state D gate i shifts from L to day. NAND gate h
The output level of NAN also shifts from day to low, which causes NAN
The output level of the D gate shifts from L to day, and at the same time it changes to N.
The output level of AND gate k shifts from 1 to 0.

When the output level of the NAND gate k shifts from 1 to 2, the output level of the NAND gate m returns from L to 1, but since the other input terminals of NAND gates e and i have already become L, Its output level remains unchanged from day to day.

As can be seen from the output signal waveform shown in FIG. 8Z, in the device shown in FIG. 7, one cycle of the signal waveform applied to the X terminal corresponds to one cycle of the signal waveform applied to the Y terminal. It has a monostable time. By the way, the signal waveform shown in FIG. 8 (c) shows the output level of the NAND gate f in FIG. Its function is unknown.

FIG. 9 is a signal waveform diagram of each part shown to explain the function of the NAND gate f. The output level of NAND gate c shifts from 1 to 2, and thereby the output level of NAND gate d shifts from L to 1, and at the same time the output level of NAND gate e shifts from 2 to L, so that the output of NAND gate c As the level returns to day 1 again, the output level of NAND gate b shifts from L to day, and at the same time, the output level of NAND gate a shifts from day to L. Time t=t. 5
When the signal level of the Y terminal shifts from day to low,
The output level of NAND gate g shifts from 1 to 0, and N
The output level of the AND gate h also shifts from L to 1, and at the same time the output level of the NAND gate i shifts from 1 to L.

At time t = t, 6, the signal level of the × terminal changes from 1 to L.
, the output level of the NAND gate a changes from L to 1, but the output levels of the other NAND gates do not change.

Time t=t. 7, when the signal level of the Y terminal changes from L to 1, the output level of NAND gate g changes from L to 1, and the output level of NAND gate j changes from 1 to L, so the output level of NAND gate k changes. is L
At the same time, the output level of the NAND gate changes from day to day.

At this time, both the input terminals lf and 3f of the NAND gate f are set to day.

At time t=t, 8, when the signal level of the X terminal changes from L to 0, the output level of the NAND gate turns from 1 to 2, and the output level of NAND gate e and NAND gate i changes from L to 1. .

This causes NAND gate d and NAND gate b
, the output level of NAND gate h, and NAND gate k shift from 1 to 2, and the output level of NAND gate 1 changes to L.
Transition from to day.

Immediately after that, the output level of the NAND gate c changes from 1 to 0, the output level of the NAND gate d changes from 1 to 1, and a new cycle begins.

It should be noted that immediately after the output level of the NAND gate f changes from day to L, the output level of NAND gate k changes from day to L, so the output level of the NAND gate k immediately returns to day.

Now, at the same time as the output level of the NAND gate d shifts from L to 1, the output level of the NAND gate e shifts from 1 to 2, the output level of NAND gate b shifts from L to 1, and at the same time, the output level of NAND gate a shifts from Output level is L
becomes.

At time t=t,9, the output level of NAND gate g shifts from 1 to 2, and thereby the output level of NAND gate h shifts from L to 9, and at the same time, the output level of NAND gate i changes from 2 to L. to move to.

At time t=t2o, the signal level of the X terminal changes from 1 to L.
When transitioning to , only the output level of NAND gate a becomes L.
Transition from to day.

At time t=t2, when the signal level of the Y terminal shifts from L to day, the output level of NAND gate g shifts from L to day, and the output level of NAND gate j shifts from mark to L. The output level of the NAND gate k changes from L to 1, and at the same time the output level of the NAND gate k changes from 1 to L.

At time t=t22, when the signal level of the X terminal shifts from L to 1, the output level of the NAND gate f shifts from 1 to L, and the same operation is repeated thereafter.

That is, when the output level of the NAND gate k is 1, and the signal level of the X terminal changes from L to 1, the NAND gate generates a reset pulse and the signal level of the This prevents changes from being hidden.

In the circuit shown in FIG. 10, the first signal input terminal
The second signal input terminal Y is connected to the input terminal 3c of the three-input NAND gate c, the input terminal ln of the inverting amplifier n, and the input terminal 2i of the two-input NAND gate j. The output terminal oc of the 3-input NAND gate c is connected to the input terminal 2d of the 2-input NAND gate d, and the output terminal od of the 2-input NAND gate d is connected to the input terminal 2e of the 2-input NAND gate e. The output terminal oe of the two-input NAND gate e is connected to the input terminal lg of the two-input NAND gate g.
d, and the output terminal 0 of the 2-input NAND gate g is connected to the input terminal 2h of the 2-input NAND gate h, and the output terminal oh' of the 2-input NAND gate h or the input terminal 2i of the 2-input NAND gate i. and the input terminal lj of the two-input NAND gate i, and the output terminal oi of the two-input NAND gate i is connected to the input terminal Ih' of the two-input NAND gate h, and the inverting amplifier The output terminal oo of the inverting amplifier 0 is connected to the output terminal Z.

On the other hand, the output terminal ot of the 2-input NAND gate t is 2
The 4-input NA is connected to the input terminal lu of the input NAND gate u and constitutes 3 sets of T flip-flops.
Input terminal 2a of ND gate a, input terminal 2b of 4-input NAND gate b, input terminal le of 3-input NAND gate e, input terminal lk of 3-input NAND gate k, input terminal of 3-input NAND gate q. lq respectively.

The output terminal ou of the 2-input NAND gate u has 2 inputs N
The input terminal lw of the AND gate w is connected to the input terminal lx of the 2-input NAND gate x.The output terminal ov of the inverting amplifier v is connected to the input terminal 2w of the 2-input NAND gate w. The output terminal ow is the input terminal 2x of the 2-input NAND gate x.
is connected to the output terminal o of the two-input NAND gate x.
x is connected to the input terminal 2t of the 2-input NAND gate t and the input terminal 2u of the 2-input NAND gate u, respectively. Also, 4-input NAND gate a, 4-input NAND gate
AND gate b, 2-input NAND gate c, 2-input NA
ND gate d, 3-input NAND gate e, 2-input NAN
The 6 NAND gates of the D gate Z toner are a well-known set of T
Similarly, 3-input NAND gate A, 3-input NAND gate h, 2-input NAND gate i, 2-input NAND gate j, and 3-input NAND gate k constitute a flip-flop.
, 2-input NAND gate, and even 3-input ZNAND
Gate m, 3-input NAND gate n, 2-input NAND gate o, 2-input NAND gate 2, 3-input NAND gate 9, and 2-input NAND gate r are also each connected to the well-known T
It constitutes a flip-flop.

The output terminal oi of the two-input NAND gate j is the first stage T.
Input terminal 3a of 4-input NAND gate a, input terminal 3a of 4-input NAND gate a, and input terminal 3b of 4-input NAND gate b constituting a flip-flop.
The output terminal 0 of the 2-input NAND gate N which constitutes the first stage T flip-flop is connected to the input terminal 2g of the 3-input NAND gate A and the input terminal 2g of the 3-input NAND gate h which constitute the second stage T flip-flop. terminal 2
output terminal 0 of the 2-input NAND gate m which constitutes the second stage T flip-flop, and 1 is connected to the input terminal 2m of the 3-input NAND gate m which constitutes the third stage T flip-flop and the 3-input NAND It is connected to the input terminal 2n of gate n. In addition, the 4-input NAND
The output terminal oa of the gate a is connected to the input terminal 1 of the inverting amplifier 2, and the output terminal 0 of the inverting amplifier 2 is connected to the input terminal ls of the 3-input NAND gate s, which is the second stage T flip-flop.

Output terminal ok of 3-input NAND gate k that constitutes the chip
is connected to the input terminal 2s of the 3-input NAND gate s, and the output terminal oq of the 3-input NAND gate q constituting the third stage T flip-flop is connected to the input terminal 2s of the 3-input NAND gate s.
It is connected to the input terminal 3s of the gate s. Now, the first
Of the circuits shown in Figure 0, the three sets of T flip-flops, each composed of six NAND gates, have a well-known configuration, so a detailed explanation of their operation will be omitted, but they constitute the signal input line for reset. NAN doing
Input terminal 2a of D gate a, input terminal 2b of NAND gate b, input terminal le of NAND gate e, input terminal lk of NAND gate k, input terminal 1 of NAND gate 4
While applying a signal waveform as shown in FIG. 11 t to each of the NAND gates 4 and 4, a signal waveform as shown in FIG. 11 i was applied to the input terminal 3 a of the NAND gate a and the input terminal 3 b of the NAND gate b. When, NAND gates a, b
, c, d, e, f, k, 1, 4, the changes in the output signal levels on Figure 11 a, b, c, -d, e, f, k, 1, q
, r.

By the way, the NAND gates t, u, w, x and the inverting amplifier v constitute a negative direction trigger pulse generation circuit, and its operation is as follows.

First, when the potentials applied to the input terminal lt of the NAND gate t and the input terminal lv of the inverting amplifier v are at L level, the output level of each NAND gate is uniquely determined,
NAND gate t day, NAND gate w day, NAN
The D gate u is set to L, and the NAND gate x is set to day.

That is, since the level of one input terminal lt of the NAND gate t is L, the level of its output terminal ot is definitely equal. If NAND gate u is day, i.e.
Assuming that the level of the output terminal ou is day, the level of the input terminal 2u must be L.

In order for the level of the input terminal 2u of the NAND gate u to be L, the level of the output terminal ox of the NAND gate x must be L, and this means that the input terminal 2x of the NAND gate x is This means that the input terminal 2w of the NAND gate w must be low in order for the input terminal 2x of the NAND gate x to become low. However, the input terminal lv of the inverting amplifier v
Since the level of is L, the level of the input terminal 2w of the NAND gate w is 1.

That is, when the level of the input terminal lv is L, the level of the output terminal ou of the NAND gate u cannot be the same, but is always L.

Now, if the levels of the input terminals lt and lv suddenly rise and move from L to day, the level of the input terminal 2t of the NAND gate t becomes day, so the above-mentioned NAND
The level of the output terminal ot of the gate t changes from 1 to L,
At the same time, the level of the output terminal ou of the NAND gate u also changes from L to day. As a result, the level of the input terminal lx of the NAND gate x changes from L to day.
The level of the output terminal ox of the D gate x shifts from 0 to 0, and the level of the output terminal ot of the NAND gate t returns from L to 0 again.

These operations end instantaneously, and the NAND gate t
The level at the output terminal ot becomes very short at the moment the input level changes from L to 0, and then transitions from 0 to L for a period of time.

While the levels of the input terminals lt and lv are maintained, the level of the output terminal ow of the NAND gate w is 1, the level of the output terminal ou of the NAND gate u is 1, and
The level of the output terminal ox of the AND gate x is L.

At the moment when the levels of the input terminals lt and lv suddenly fall and change from 1 to 0, the level of the input terminal lw of the NAND gate w has been 0 until then, so the NA
The level of the output terminal ow of the ND gate w shifts from 1 to 0, thereby causing the output terminal ox of the NAND gate x to
The level of increases from L to day.

At this time, the level of the output terminal OW of the NAND gate w is always kept short and changes from 1 to 0 during the period.

While the levels of the input terminals lt and lv are held at L, the level of the output terminal ot of the NAND gate t remains low, and the level of the output terminal o of the NAND gate w remains low, as described above.
The level of w is also 1, the level of the output terminal ou of the NAND gate u is L, and the level of the output terminal ox of the NAND gate x is 1.

Thereafter, the same operation is repeated every time the level of the input terminals lt and lv changes from L to 1, or from H to L, and eventually the level of the input terminals lt and lv reaches the 11th level.
When the voltage changes as shown in FIG. i, the level of the output terminal ot of the NAND gate t becomes as shown in FIG. 11t. That is, a negative trigger pulse is generated at the output terminal ot of the NAND gate t due to a positive change in the input signal.

Now, when a signal waveform as shown in FIG. 11 is applied to the input terminals X and Y, first, the change in the signal level applied to the X terminal from L to 1 causes the NAND gate t to generate a negative trigger pulse. That is, since a reset pulse is generated and the outputs of NAND gates a, b, e, k, and q are set to day, the output of NAND gate s is also set to day.

As a result, the output terminal oc of the NAND gate c has a signal waveform that is applied to the input terminal Y, that is, the input terminal 3c of the NAND gate c, while the levels of the input terminals lc and 2c are maintained at the same level. An inverted output appears.

By the way, the output level of NAND gate s is L before the signal level applied to input terminal has become,
The output levels of NAND gate d and NAND gate h are at L.

At the moment the output level of the NAND gate c changes from low to low, the output level of the NAND gate d changes from low to low, and the output level of the NAND gate e changes from high to low. From the moment the output level of the NAND gate d reaches 1, a signal having the same waveform as the signal applied to the input terminal Y appears at the output terminal 0g of the NAND gate g.

At the moment when the output level of the NAND gate g changes from low to low, the output level of the NAND gate h changes from low to low, and the output level of the NAND gate i changes from high to low.

From the moment the output level of the NAND gate h reaches 1, an inverted signal of the signal waveform applied to the input terminal Y appears at the output terminal oi of the NAND gate j.

In this way, NANO gates c, d, e, g, h,
The output levels of i and i are shown in Figure 11 c, d, e, and g, respectively.
, h, i, j.

Now, when a signal waveform as shown in FIG. 11i is applied to the input terminal of the first stage T flip-flop, and a signal waveform as shown in FIG. 11t is applied to the reset signal input line, the flip-flop.

NAND gates a, b, c, d, e'f that make up the block
, upper, ↓, 1, and upper bells are shown in Figure 11 a and b, respectively.
, c, d, e, f, k, ↓, 9, r, the output level of NAND gate a is L, the output level of NAND gate k is day, and the output level of NAND gate 9 is day. At the moment when the output level of the NAND gate s becomes low, the output level of the NAND gate s shifts from 1 to 1, and the output levels of the NAND gates c, e, and i all become 1. (However, if the signal level of the × terminal becomes L before the output level of the NAND gate s becomes L, the output level of the NAND gate c becomes 100% before this time.) The state is held until the signal level at the X terminal changes from low to high again and the NAND gate t is reset.

Therefore, in the circuit of FIG. 10, when the signal levels of the X and Y terminals change as shown in FIG. 11 A signal waveform as shown appears.

As is clear from the signal waveform shown in FIG. 11 Z, the output signal of the circuit shown in FIG.
It has a monostable time corresponding to 7 cycles of the signal applied to the Y terminal during a cycle, and the time of one cycle of the signal applied to the × terminal corresponds to 7 cycles of the signal applied to the Y terminal. In this case, the signal level at output terminal Z remains the same forever.

Now, if we divide the device shown in Fig. 1 according to its functions, we will first find a reference frequency generator consisting of a crystal oscillator 2 and a frequency divider 3, a monostable circuit 4, a low resistance 5 and capacitor 6, voltage dividing circuit with low resistor 7 and 8, comparator amplifier 9, voltage controlled oscillator 11, monostable circuit 12, smoothing circuit with low resistor 13 and capacitor 4, low resistor 15 and 17 and variable low resistor. A variable frequency generator constituted by a voltage dividing circuit using resistor 16, frequency dividers 19, 20, phase comparator 21, amplifier 24, monostable circuit 25, combining circuit 26, motor drive circuit 27, and speed detector 23 for controlling the rotational phase of the rotating body to be synchronized with the output signal from the variable frequency generator; a discriminating circuit for discriminating whether the
a conversion circuit that obtains a periodic signal (display pulse) that changes depending on the reference value of the rotational speed of the rotary body; and a second display unit that causes a display to blink according to the periodic signal.
In the example shown in FIG. 1, the discrimination circuit includes a trigger pulse generation circuit 33, a comparison amplifier 35,
It is constituted by a monostable circuit 37, and the first display means is A.
ND gate 32, AND gate 34, inverting amplifier 36,
38. Consisting of amplifiers 39 and 40, the conversion circuit includes a logical sugar circuit that obtains an AND output of the output signal obtained from the variable frequency generator and the reference frequency signal, that is, an AND circuit using an AND gate 28, and a trigger pulse generation circuit 29.
, a monostable circuit 30, and a frequency divider 31.
The display means is composed of an AND gate 32, an AND gate 34, an amplifier 39, and an amplifier 401, and a display is composed of light emitting diodes 44, 45, and 46.

As described above, the configuration of the apparatus shown in FIG. 1 can be classified according to function, and an outline of the operation of each block will be explained below.

First, to explain the variable frequency generator, if the monostable circuit 4 and the monostable circuit 12 shown in FIG. 10 are used as shown in FIG. and becomes L during the non-monostable period.

The H level of the monostable circuits 4 and 12 is equal to the supply voltage Vq
, and assuming that the L level potential is zero, the constants of the resistors 5 and 13 and the capacitors 6 and 14 that constitute the smoothing circuit are determined so that the output signals of the monostable circuits 4 and 12 are sufficiently smoothed. When set, low resistance 5, 7, 8,
1 3, 1 5, 17, and the low resistance values of the variable resistance reducer 16 are R5, R7, R8, R, 3, R, 5, R, 7, R, respectively.
6. The monostable time of the monostable circuit 4 is TH, the non-monostable time is TL, the monostable time of the monostable circuit 12 is TH2,
When the non-monostable time is TL2, the voltage y6 across the capacitor 6 and the voltage V, 4 across the capacitor 14, which are smoothed voltages, are as follows.

VG: Rank 5 Harmful Poison Sanhai Ashikura Sozo ≦ 3L. ) [11V.
4 = (R.3 all yellow; table cover youth poisonous safety monkey three-handed sheep TL2)
■By the way, as mentioned earlier, the low resistance values of low resistance 5 and low resistance 13 are the same, and the composite low resistance value of low resistance 7 and low resistance 18 is the same as that of low resistance 1.
5, 17 and the variable resistor 16 are also set to be equal, and the monostable circuit 4 and the monostable circuit 12 have exactly the same circuit configuration, so R70R8
R, 50R, 60R, 7R50R70R
80Vcc=R, 3+R, 50R, 60R, 7・Vcc
=Vk'3'TH, =TH2=TH
(4}.

Using this VK, TH and rewriting the {1), ■ equation, we get v
6=〒Taiko-VK ■TH
On the other hand, the voltages Va and Vb applied to the input terminals 9a and 9b of the comparator amplifier 9 are as follows: if the input impedance of the input terminals can be regarded as infinite, then Va=R; V6 '7} Since R7=R8, Va=Vzu=aT King≠TL. )-Vk [81 Low resistance value R of 15 and the said low resistance value R of 5 and variable resistance resistor 1 6
Synthetic low resistance R with low resistance value of side 5, low resistance value R of low resistance 17,
7 and the low resistance value of the resistors 1 and 7 of the variable resistance resistors 1 and 6 is R, then □ ○ The frequency of the output signal from the frequency divider 3 is 〆s, If the output frequency is Nav, then 1'IQ〆S=phrase h▽・ku11) NaV=Shunkuku holds true.

Now, in the device shown in FIG. 1, the oscillation frequency of the voltage controlled oscillator 11 is controlled by the output of the comparator amplifier 9.

That is, since a feedback control loop is formed, the comparison amplifier 9 functions as an error amplifier,
Control is performed so that the difference between the voltage ya applied to the input terminal 9a and the voltage Vb applied to the input terminal 9b becomes zero.
Therefore, Va=Vb (12)
■～(If we organize the 12 methods, 〆V: {Hanaichi Totsuru}・MeS (13) From the formula (13), the voltage controlled oscillator 11
The frequency of the output signal V depends on the frequency S of the output signal of the crystal oscillator 2 and the voltage dividing ratio of the voltage dividing circuit by the variable resistor 16, and is determined by sliding the midpoint of the variable resistor 16. It can be seen that the output is continuously variable.

Next, explaining the phase control means, the output signal of the voltage controlled oscillator 11 is transmitted to the switch 1 for switching the frequency division ratio.
8 is applied to a frequency divider 19 having a
The output signal is applied to the next-stage frequency divider 20 and to the control input terminal Y3 of the monostable circuit 25. on the other hand,
The output signal of the speed detector 23 is amplified by the amplifier 24, and the output signal amplified until it becomes a rectangular wave is applied to the input terminal X3 of the monostable circuit 25, and is also applied to the input terminal The phase is compared with the output signal.

The output signal of the phase comparator 20 is applied to a motor drive circuit 27 via a synthesis circuit 26, and the phase of the output signal of the speed detector 23, that is, the rotational phase of the motor 22 and the phase of the output signal of the separator 20 is applied. A general phase comparator has a finite gain for the phase difference, but it has a finite gain for the frequency difference of the signal applied to the input terminal. (Strictly speaking, the velocity gain in steady state is infinite, but
The slope of the gain with respect to speed change is zero.

), since the transient response of the rotating body becomes extremely unstable if only the phase control system is used, a separate frequency control system is also used as a means of synchronization pull-in. That is, in the device shown in FIG. 1, when the rotational speed of the motor 22 deviates considerably from the set value, the frequency control system using the monostable circuit 25 controls the rotational speed of the motor 22 until it becomes close to the set value, and then the phase changes. The detected phase signal obtained from the speed detector 23 by the phase control system using the comparator 21, that is, the motor 2
Phase control is performed so that the phase difference between the rotational phase signal No. 2 and the reference phase signal obtained from the frequency divider 20 remains constant.

Now, if we operate the switch 18 and set the output frequency of the frequency divider 19 to be high, the frequency of the reference phase signal applied to the input terminal 21a of the phase comparator 21 will become high, and the monostable circuit Is the monostable time of 25 short?
Become. When the monostable time of the monostable circuit 25 becomes shorter, the average level of the output signal appearing at its output terminal Z decreases, and the motor drive circuit 27 operates in a direction to accelerate the rotational speed of the motor 22. When the rotational speed of the motor 22 is accelerated and the average level of the output signal of the monostable circuit 25 returns to its original state, that is, the ratio of the H level period to the L level period of the output signal has changed to switch 18. When the state becomes the same as before the operation, the input terminal 21 of the phase comparator 21
The frequencies of the reference phase signal applied to a and the detected phase signal applied to the input terminal 21b of the phase comparator 21 become equal, and phase control is now performed.

In this way, in the phase control means of FIG. 1, the monostable time of the monostable circuit that constitutes the frequency control system is automatically switched in response to switching of the reference frequency signal, so when switching the rotation speed, It is only necessary to operate one switch 18, and the reference frequency (
Even if the rotation phase (for controlling the rotational phase) is changed continuously, the monostable time of the monostable circuit 25 changes automatically to follow the change, so the average output level of the wave number control system is always kept constant. can be maintained.

In the embodiment of the present invention shown in FIG. 1, the rotational speed display means of the rotating body is connected to the motor rotational speed (rotational phase) control device as described above.

The rotational speed display device of the present invention shown in FIG. , the output signal of the voltage controlled oscillator 11, or the output signal of the frequency divider 20). In other words, in a phase control system, the phase deviation shows a finite value, but
This was done by focusing on the fact that the speed deviation is always zero, and even if the periodic signal changes depending on the difference between the signal frequency from the reference frequency generator and the signal frequency from the variable frequency generator, This indicates the deviation of the rotational speed from the standard. Now, assuming that the output signal of the frequency divider 3 is as shown in FIG. 12a, the trigger pulse generation circuit 2
A differential pulse train as shown in FIG. 12b appears at the output terminal W of 9.

Now, if we adjust the variable resistor 16 to make the rotational speed of the motor 22 a little faster than the reference rotational speed, the output signal waveform of the voltage controlled oscillator 11 at that time will be as shown in Fig. 12c.
The result will be as shown below.

The signal waveform in FIG. 12c is the input terminal 2 of the AND gate 28.
8a and the other input terminal 28b of the AND gate 28, that is, the signal waveform of FIG. 12b and the signal waveform of FIG. Since the output of the gate 28 is at H level, the output side of the AND gate 28 has the first
A signal waveform as shown in FIG. 2d appears.

Here, if the monostable time of the monostable circuit 30 is made slightly longer than the repetition period of the signal waveform shown in FIG. This is possible by configuring the monostable circuit 30 to have a monostable time corresponding to 15 cycles of the signal applied to the control input terminal Y4.

), the monostable circuit 30 is triggered by the first pulse of the signal waveform shown in FIG. 12d, and before the monostable period ends, the second pulse is applied and the monostable period starts again. . That is, after the first trigger pulse (differential pulse) is applied to the monostable circuit 301, the output of the monostable circuit 30 continues to be maintained at the H level, and after the fifth trigger pulse is applied, the output of the monostable circuit 30 continues to be maintained at the H level. After the monostable period of the circuit 30 ends, the output level of the monostable circuit 30 returns to L'. In the end, the monostable circuit 3 in Figure 12 d
When a signal waveform as shown in FIG. 12 is applied, the output signal waveform becomes as shown in FIG. 12e. Next, if the rotational speed of the motor 22 is further adjusted to be faster than the reference rotational speed, the output signal waveform of the voltage controlled oscillator 11 becomes as shown in FIG. is as shown in FIG. 12g.

The monostable circuit 3 is activated by the trigger pulse train shown in Fig. 12g.
0' is triggered, and the output signal waveform becomes as shown in FIG. 12h.

Now, if the rotational speed of the motor 22 becomes further, the output signal waveform of the voltage controlled oscillator 11 AND gate 2
The output signal waveform of 8 and the output signal waveform of the monostable circuit 30 are as shown in FIG. 12 i, FIG. 12 j, and FIG. 12 k, respectively. Repeat level changes at short intervals.

On the other hand, when the rotation speed of the motor 22 is adjusted to be slightly slower than the reference rotation speed, the voltage controlled oscillator 1
The output signal waveform of 1 is as shown in Figure 13c, and
The output signal waveforms of the gate 28 and the monostable circuit 30 are as shown in FIGS. 13d and 13e, respectively.

When the rotational speed of the motor 22 becomes even slower, at Z,
Similarly, the output signal waveforms of the voltage controlled oscillator 11, the AND gate 28, and the monostable circuit 30 are as shown in FIG.
It becomes as shown in FIG. 13M.

When the rotation speed of the motor 22 becomes slower, the output signal waveforms of the voltage controlled oscillator 11, the AND gate 28, and the monostable circuit 30 become as shown in FIGS. 13i, 13j, and 13k, respectively. Incidentally, the frequency divider 31 to which the output signal of the monostable circuit 30 is applied counts down the level change of the output signal of the monostable circuit 30 into a slow level change. 46 is inserted to slow down the blinking cycle. Of course, divider 3
If the blinking period of the light emitting diode 45 or the light emitting diode 46 is slow even without passing through the frequency divider 31, the frequency divider 31 becomes unnecessary. In addition, in the above explanation, the monostable circuit 30 that can be triggered as shown in Fig. 1 is used, but if the monostable circuit shown in Fig. 7 is not possible Even if a monostable circuit is used, although some drop-off occurs during the H level period of waveform e in FIG. 12, the ability to determine whether the deviation in rotational speed is large or small is not lost. By the way, when the variable resistor 16 is adjusted so that the rotating body speed of the motor 22 is set to be faster than the reference rotation speed, the potential at the input terminal 35a of the comparator amplifier 35 becomes lower than the potential at the input terminal 35b. At this time, the output level of the comparator amplifier 35 becomes high.On the other hand, when the rotational speed of the motor 22 is set to be slower than the reference rotational speed, the output level of the comparator amplifier 35 becomes high. The output level becomes L than the potential of the input terminal 35a.

By the way, when the frequencies of the digital signals applied to the input terminal 28a of the AND gate 28 and the input terminal V of the trigger pulse generation circuit 29 are different, the digital signal having a repetition period depending on the difference is a monostable circuit. As mentioned above, if the frequencies of both digital signals are exactly the same, the repetition period of the digital signal appearing at the output terminal B of the monostable circuit 30 is infinite. However, depending on the phase difference between the two digital signals, the level of the output terminal B of the monostable circuit 30 may be high or low. To explain this situation using Fig. 14, when the phases of the output signal obtained from the tube divider 3 (Fig. 14 a) and the output signal of the voltage controlled oscillator 11 shown in Fig. 14 c become almost equal. , the output signal of the AND gate 28 is the fourteenth
This becomes a continuous pulse train as shown in FIG. d, and the output of the monostable circuit 30 remains at H level.

0 On the other hand, the output signal of the voltage controlled oscillator 11 is
As shown in FIG. 14, when the phase is shifted by approximately half a phase from the signal in FIG. 14a, as shown in FIG. 14g, the output of the AND gate 28 is kept at L level. Therefore, the monostable circuit 30 is not triggered at all, and its output remains zero as shown in FIG. 14h.

This is very inconvenient when you want to display that the rotational speed of the motor 22 has become equal to the reference rotational speed. This solves the inconvenience.

That is, the basic circuit configuration of the monostable circuit 37 connected to the output side of the frequency divider 31 via the trigger pulse generation circuit 33 is the same as that of the monostable circuit shown in FIG. The monostable time is set to be much longer than the monostable time of the monostable circuit 30 by increasing it further.

When the level of the 0 output signal of the monostable circuit 30 or the separator 31 changes, the trigger pulse generating circuit 3
3 generates a differential pulse, which causes the monostable circuit 37 to be at the daily level for a very long time, and the output of the inverting amplifier 38 maintains the L level, so that the light emitting diode 4
4 is not lit.

At this time, if the rotational speed of the motor 22 is far from the reference rotational speed, the output level of the comparator amplifier 35 will be 0.
1 output signal appears, and the light emitting diode 45 is caused to repeat blinking by the amplifier 39 at a blinking period dependent on the deviation of the rotational speed of the motor 22 from the reference rotational speed.

While the output level of the comparison amplifier 35 is high, the output level of the inverting amplifier 36 is L, so the output level of the AND gate 34 and amplifier 40 is L, and the light emitting diode 46 does not light up.

On the other hand, if the rotational speed of the motor 22 is slower than the reference rotational speed, the output level of the comparison amplifier 35 becomes L.
Therefore, the output signal of the frequency divider 31 appears on the output side of the AND gate 34, and the light emitting diode 46 flashes at a blinking period depending on the deviation of the rotational speed of the motor 22 from the reference rotational speed. Repeated flashing. While the output level of the comparison amplifier 35 is L, the AN
The output level of the D gate 32 and amplifier 39 becomes L, and the light emitting diode 45 does not light up.

On the other hand, when the rotational speed of the motor 22 becomes equal to the reference rotational speed, there is no change in the output level of the monostable circuit 30 or the frequency divider 31, as shown in FIGS. 14e and 14h. The output level of the stabilizing circuit 37 remains L, and the output level of the inverting amplifier 38 becomes 1, so the light emitting diode 44 lights up.The output level of the AND gate 32 and the AND gate 34 both become L, so the light emitting diode 45 lights up. , 46 are not lit.

That is, when the rotational speed of the motor 22 becomes faster than the reference rotational speed, only the light emitting diode 45 repeats blinking at a blinking period that depends on the deviation from the reference rotational speed, and the rotational speed of the motor 22 becomes the reference rotational speed. When the match occurs, only the light emitting diode 44 lights up and the motor 22
When the rotational speed becomes slower than the reference rotational speed, only the light emitting diode 46 repeats blinking at a blinking period that depends on the deviation from the reference rotational speed.

Now, the rotational speed display device of the present invention shown in FIG. Because the display element blinks, it is easier to check for discrepancies in rotation speed than with conventional rotation speed display devices that use strobe cotton.Also, the light emitting diode, which is the display element, can be placed anywhere in the device. Since there is no problem even if the device is used, the degree of freedom in designing the device (equipment) is considerably increased.

Another disadvantage is that the electronic circuit is more complex than the conventional strobe cotton display device, but in devices that use phase control, many parts such as the reference frequency generator and variable frequency generator are controlled by the control circuit. If the circuit is integrated into an IC, it will not be a big problem compared to the need to provide strobe stripes around the outer periphery of a turntable or the like.

In the rotational speed display device for a rotating body according to the present invention shown in FIG. Since the display means is driven by a synchronization signal that changes according to the difference between the frequency and the frequency of the output signal from a reference frequency generator with a fixed frequency, the display rate remains constant even when the rotation of the rotating body is changed. has the effect that it remains unchanged.

To explain this in detail, let us now set the output frequency of the frequency divider 3 as "s," set the output frequency of the voltage controlled oscillator 11 as "v," and set the output frequency of the monostable circuit 30 as "s."

Then, the following equation holds true in the region where ``na'' and ``v'' are not significantly different.Na.

=l NaS-NaVl (14)
If the frequency division ratio of the frequency divider 31 is 3, its output frequency n is m=8·na.

=B·l〆S−mayl (15) Nam is also the blinking frequency of the light emitting diode 45 or the light emitting diode 46.

Here, to explain with specific numerical values, it is assumed that the output frequency n of the frequency divider 3 is 100 KHz.

When the rotational speed of the motor 22 is increased by 1% from the reference rotational speed, the output frequency nv of the voltage controlled oscillator 11 becomes 101KHz, and from equation 14, ・na.

=・(KHZ) The frequency division ratio B of the frequency divider 31 is 1 every 100 nights.
If set to , then n = 1 (world).In other words, when the rotational speed of the motor 22 is increased by 1% from the reference rotational speed, the light emitting diode 45 will repeat blinking at a rate of once per second. .

Similarly, when the rotational speed of the motor 22 is lowered by 1% from the reference rotational speed, the light emitting diode 46 repeats blinking at a rate of once per second.

Next, when the rotational speed of the motor 22 is increased by 2% from the reference rotational speed, 〆V=102 (KHZ
) 〆m=2 (world) In other words, when the rotational speed of the motor 22 is increased by 2% from the reference rotational speed, the light emitting diode 45
The light emitting diode 46 repeats blinking at a rate of two times per second, and when the light is lowered by 2%, the light emitting diode 46 repeats blinking at the same rate.

Therefore, according to the present invention, it is possible to know the percentage deviation from the reference rotation speed by checking how many times the display element blinks within a certain period of time or by measuring the blinking cycle of the display element. can. For example, in the device shown in FIG. 1, if the light emitting diode 45 blinks at one stage, then the motor 22 is 0.1% faster than the reference rotation speed.

By the way, in the apparatus shown in FIG. 1, this display rate does not change depending on the rotational speed.

In the device shown in Fig. 1, even if the rotational speed of the motor 22 is changed by operating the switch 18, there is no change in the rotational speed display area, so the light emitting diode flashes at intervals of 1 step before the rotational speed switch. If the deviation from the reference speed is 0.1%, even after switching the rotational speed, if the light emitting diode blinks at 10 second intervals, the deviation is 0.1%. By the way, to explain how the rotation speed is displayed using the conventional strobe cotton, it is the rotation speed N (rpm) of a turntable with strobe stripes on the outer periphery and the strobe stripe irradiation frequency F (ship).
, and the number of movements of the strobe cotton per second when a deviation occurs in the rotational speed (number of rotations) can be determined as follows.

The number of strobe wires installed around the outer circumference of the turntable is 2.
Then, when the turntable rotates, the number of strobe stripes passing per second at an arbitrary point near the outer periphery of the turntable is n', where n=magazine X2
If the strobe stripe irradiation lamp goes out per second and the number n of passing stripes are exactly the same, the strobe stripes will appear to stop; if the number of times the strobe stripe irradiation lamp goes out and the number of passes differ, the difference will be It appears to move by the number of strobe stripes per second.

Therefore, when driving the strobe cotton irradiation lamp with a pulse signal, X=magazine.

X2-F (17) When x takes a positive value, the strobe stripes appear to move in the rotational direction, and when x takes a negative value, the strobe fringes appear to move in the opposite direction to the rotational direction.

Now, let us assume that 180 strobe wires are arranged at equal intervals around the outer circumference of the turntable.

When the rotation speed of the turntable is 331'3 rpm, the strobe lamp irradiation frequency to make the strobe cotton appear stationary can be found by substituting x=0 in equation (17) and using the following equation.○ Ru.

F device.

X2 Substituting leg N, = 331/3, 2 = 180, taF. When the irradiation frequency of the strobe lamp on the instrument side o=loo side is set to 10 seconds, the number of movements of the strobe stripes per second when the rotation speed of the turntable increases by 1%,
When I tried to find it, I found that = high.

X331'3XLo1x180-10031-0 That is, the stripe moves for one second. Next, when the rotation speed of the turntable is 48 pm, the strobe lamp irradiation frequency F2 to make the strobe stripes appear stationary is (180,000 yen, F2 = device x 18o = 13
5 (place) When the strobe lamp irradiation frequency is set to 138 seconds (naturally, it becomes necessary to switch the strobe lamp irradiation frequency at the same time as switching the rotation speed).

If we calculate the number of strobe stripes moving per second, X2, when the rotational speed of the turntable increases by 1%, we get:
35:1,35, or about 0. One strobe stripe moves every second. As described above, the conventional method of displaying the rotational speed using a single strobe stripe has the drawback that the display rate also changes when the rotational speed is switched.

To solve this problem, it would be possible to separate strobe stripes for each rotation speed into any number of strips, but in that case, when switching the rotation speed, the strobe strips for checking the rotation speed must also be checked at different locations. It is extremely inconvenient.

Furthermore, when the output frequency of a speed detector connected to a rotating body such as a turntable or a motor is used to display a deviation in rotational speed, exactly the same problem as in the case of a strip of strobe cotton occurs.

In comparison, the rotational speed display device for a rotating body of the present invention shown in FIG. 1 has a major feature in that the display rate does not change even when the rotational speed is switched. By making full use of these features, it is also possible to realize a device as shown in FIG. 15.

FIG. 15 shows another embodiment of the present invention, in which blocks and elements that are exactly the same as those in FIG. 1 are designated by the same figure numbers.

In FIG. 15, the input side of a counting circuit 47 is connected to the output terminal Z of the monostable circuit 30, and the output signal of the counting circuit 47 is applied to the number display element group 49 via the driving circuit 48, and The counting circuit 47 includes a crystal oscillator 2.
A clock pulse is applied from

Further, the output signal of the comparison amplifier 35 is applied to the plus sign display element 51 via the amplifier 50, and the output signal of the inverting amplifier 36 is applied to the minus sign display element 52.

In the apparatus shown in FIG. 15, the counting circuit 47 and the driving circuit 48
, the number display element group 49 constitutes a well-known frequency counter, which displays 1.0 when the input frequency is IKHz, and 100.
When it is Hz, 0.1 is displayed.

Now, if the output frequency of the frequency divider 3 is set to 10 Hz as in the device shown in Fig. 1, when the rotational speed of the motor 22 becomes 1% faster than the reference rotational speed, The plus sign display element 51 lights up, and the number display element group 49 displays 1.0, and the overall number is "11.
0" is displayed.

Similarly, when the rotational speed of the motor 22 becomes 1% slower than the reference rotational speed, "-1.0" is displayed.

Also, the rotational speed of the motor 22 is 0% lower than the reference rotational speed.
．． When the speed increases by 1%, the monostable circuit 3
The output frequency of 0 is 0.1KHz, so "100.1"
Similarly, when the delay is 0.1%, the display of "-0.1J" is performed.

In this way, in the device shown in Fig. 15, the rotating body (motor 22)
It is possible to instantly read by what percentage the rotational speed of the motor deviates from the reference rotational speed in the positive or negative direction.

Of course, when the rotational speed of the rotating body matches the reference rotational speed, the display becomes "±0.0", and these display rates do not change by switching the rotational speed, similar to the device shown in FIG. In the embodiments of the present invention shown in FIGS. 1 and 15, the variable frequency generator is one that compares the output frequencies of a reference frequency generator and a voltage controlled oscillator to control the oscillation frequency of the voltage controlled oscillator. However, even if a general astable multipipulator or relaxation oscillator, in which the oscillation frequency is determined by a capacitor and a low resistance, is used as the variable frequency generator, regardless of the stability of the control system, the Exactly the same effect can be obtained as a display device.

Furthermore, the conversion circuit can be realized not only by the combination of the AND circuit and the monostable circuit shown in the embodiment, but also by the combination of the well-known D flip-flop and other flip-flop circuits, or by the analog type used in radio receivers, etc. It is also possible to use a conversion circuit.

As described above in detail with respect to its operation and effects, the rotational speed display device for a rotating body of the present invention includes a discrimination circuit for determining whether the rotational speed of the rotating body has become farther or slower than the reference rotational speed. Since the rotational speed display means is driven by a conversion circuit that generates a periodic signal that changes according to the deviation of the rotational speed of the rotating body from the reference rotational speed, it is very easy to determine that the rotational speed of the rotating body is from the reference rotational speed. It is possible to check whether there is a deviation from the rotational speed and the direction of the deviation, and there are no restrictions on the external design of the device as with conventional display devices that use strobe stripes. It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a rotational speed display device for a rotating body including phase control means for a rotating body according to an embodiment of the present invention, FIG. 2 is a circuit connection diagram showing a specific example of a crystal oscillator, and FIG. 3 is a circuit wiring diagram showing a specific example of a voltage controlled oscillator, FIG. 4 is a circuit wiring diagram showing a specific example of a synthesis circuit, and FIG. 5 is a circuit wiring diagram showing a specific example of a trigger pulse generation circuit. Figure 6 is a signal waveform diagram of each part, Figure 7 is a circuit connection diagram showing a specific example of a monostable circuit, Figures 8 and 9.
The figure is a signal waveform diagram of each part, Figure 10 is a circuit connection diagram showing another specific example of a monostable circuit, Figure 11 is a signal waveform diagram of each part, Figures 12, 13, and 14. are signal waveform diagrams of various parts of the conversion circuit for explaining the operation of the device shown in FIG. 1, and FIG. 15 is a block diagram of a rotational speed display device for a rotating body in another embodiment of the present invention. 33, 35, 37...discrimination circuit, 32, 34, 36,
39, 40... first display means, 28, 29, 30,
31... Conversion circuit, 32, 34, 39, 40... Second display means, 44, 45, 46... Display device. Fig. 2 Fig. 3 Occupation map Swallow Leopard Fig. 4 Leopard Fig. 5 Fig. 6 Fig. 8 Fig. 9 Fig. Snake Fig.

Claims (1)

[Claims] 1. A speed detector connected to a rotating body, an output signal from the speed detector is supplied to an input terminal on the detection side, and an output signal from the variable frequency generating means is supplied to the input terminal on the reference side. a phase comparator to which the rotating body is supplied, a driving means for driving the rotating body based on the output of the phase comparator, and an output signal of a separately provided reference frequency generator and an output signal from the variable frequency generating means. a conversion circuit that compares and generates a display signal whose period changes according to the deviation; and a determination that determines whether the output signal frequency of the variable frequency generating means is higher or lower than the frequency of the output signal of the reference frequency generator. a circuit, at least two indicators each having a lit state and an unlit state, and a first display unit that causes one of the two indicators to be in a lightable state depending on the output of the discrimination circuit. a second display means for causing at least one of the indicators to blink at a blinking cycle dependent on the shift based on the output of the conversion circuit; a frequency divider disposed on the path leading to the rotor, the frequency division ratio of which is switched in accordance with switching of the rotational speed of the rotating body;
An output signal from the variable frequency generation means via the frequency divider is supplied to the reference side input terminal of the phase comparator, and an output signal not via the frequency divider is supplied to the conversion circuit and the discrimination circuit. A rotational speed display device for a rotating body, characterized in that: 2. A conversion circuit is connected to an AND gate whose one input terminal is supplied with the output signal from the reference signal generator and whose other input terminal is supplied with the output signal from the variable frequency generator, and the output of the AND gate. The rotation of the rotating body according to claim 1, characterized in that the rotation of the rotating body is constituted by a monostable circuit that is triggered by the above-described monostable circuit, and a second frequency divider that divides the output signal of the monostable circuit. Speed display device. 3. A speed detector connected to a rotating body, and a phase comparison in which the output signal from the speed detector is supplied to the input terminal on the detection side, and the output signal from the variable frequency generation means is supplied to the input terminal on the reference side. a drive means for driving the rotary body based on the output of the phase comparator, and a separately provided reference frequency generator that compares an output signal from the variable frequency generation means with the output signal from the variable frequency generation means to detect a difference therebetween. at least two types: a conversion circuit that generates a display signal whose period changes according to the frequency, and a determination circuit that determines whether the output signal frequency of the variable frequency generating means is higher or lower than the frequency of the output signal of the reference frequency generator. a first display device capable of displaying a decimal value; a second display device capable of displaying a decimal value; 1 display means, a second display means for counting the output signal of the conversion circuit and referencing the result to the second display, and a second display means on the path leading to the reference side input terminal of the phase comparator. A frequency divider is arranged and the frequency division ratio is switched according to switching of the rotational speed of the rotating body, and the variable frequency generating means is connected to the input terminal on the reference side of the phase comparator via the frequency divider. 1. A rotational speed display device for a rotating body, characterized in that an output signal is supplied from the converter circuit and the discrimination circuit is supplied with an output signal that does not go through the frequency divider.