JPS602638B2 - time display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time display device that displays the time of a clock circuit on the screen of a color television receiver, etc., and facilitates the identification of correct or incorrect displayed time.

There is a means for displaying the time on a cathode ray tube screen by incorporating a clock circuit into the television receiver body.

In this case, only the hours and minutes are displayed, and the seconds are usually not displayed because they are not necessary. Therefore, in order to confirm that the clock is working, it is necessary to wait at most one minute for the minute digit to change. Another way to indicate that the clock is working properly is to display a semicolon between the hours and minutes and make the semicolon blink for one second.However, in the case of a television receiver, the display contents It is very disturbing when a part of the screen blinks. Another option is to detect when the clock is not working properly and flash the entire display as a warning, but this method would stop the clock when setting the time, which would indicate an abnormality. It is difficult to set the time because the display blinks. Furthermore, if the clock installed inside the television receiver has a timer function and displays similar things such as the clock time and the timer set time, the displayed content may be the clock time or the timer set time. A means of distinguishing whether it is the time is needed. The present invention has been made in order to cope with the above-mentioned circumstances, and it is possible to easily identify whether the displayed time of a clock circuit is correct or incorrect, and also to easily distinguish between the set time of a timer and the clock time, and also to make it easy to set the time. The purpose of this invention is to provide a time display device that can be obtained in the following manner.

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 7.

That is, in FIG. 1, 11 is a clock circuit built into a color television receiver, and a clock signal from this clock circuit 11 is applied to a character signal generating circuit 12. This character signal generating circuit 12 generates a character signal corresponding to a time signal, and applies this character signal to a character display means 14 including a cathode ray tube 15 via a first gate circuit 13.
The time signal is obtained as a digital signal, and when this signal is applied to the character generation circuit 212, this circuit superimposes the generated character signal at a predetermined position in the vertical and horizontal scanning periods of the television signal. Further, for the character display means 14, the output of the back gate signal generation circuit 16 is transmitted to the second gate 2.
, are added via the gate circuit 17.

This back gate signal generation circuit IS is for generating a back gate signal that serves as a border and a contrast when the character signal is displayed on the screen of the cathode ray tube 15. For example, as shown in FIG. 2, a back gate B is created for the letter A. Therefore, the back gate signal needs to be synchronized with the character signal at a predetermined pupil in the vertical and horizontal scanning periods of the television signal. A synchronizing signal (horizontal synchronizing signal) from the means 14 is added.The back gate signal which is the output of the back gate signal generating circuit 16 is sent to the character display means via the second 40 gate circuit 17 as described above. This back gate signal is also applied to the gate opening/closing control terminal of the first gate circuit 13.

This configuration is one of the features of the present invention, and its operation and effects will be described in detail later. The clock circuit 11 is provided with a time setting function, which is obtained by operating the time setting switch 19 to speed up the pulse counting operation within the clock circuit.

Then, time counting is started by operating the start switch 20. The time setting switch 19
, the output of the start switch 20 is the control circuit 1
It can also be added to 8. The control circuit 18 receives a time setting signal a from the time setting switch 19, a start signal b from the start switch 20, and also receives a clock signal c and an initialization signal d. This control circuit 18 will be explained in detail with reference to FIG. That is, 21 is an AND circuit to which a time adjustment signal a and an initialization signal d are applied to first and second input terminals, respectively. An output terminal of this AND circuit 21 is connected to a first input terminal of a NAND circuit 22. An output terminal of this NAND circuit 22 is connected to a first input terminal of a NAND circuit 23. The start signal d is applied to the second input terminal of this NAND circuit 23.
Further, the output terminal of the NAND circuit 23 is connected to the NAND circuit 22.
It is connected to the second input terminal of the NAND circuit 22, and forms a flip-flop circuit together with the NAND circuit 22. The output terminal of this flip-flop circuit, that is, the output terminal of the NAND circuit 22 is connected to the third input terminal of the NAND circuit 24. The time adjustment signal is also applied to the second input terminal of this NAND circuit 24, and the clock signal c is also applied to the first input terminal. This clock signal c is from the clock circuit 11 and is synchronized with, for example, a second pulse of the clock circuit 11. Therefore, the output of the NAND circuit 24 is added to the control terminal of the back gate signal generating circuit 16. It will be done. This back gate signal generation circuit 1
6, the output of the back gate signal is controlled on/off by the output signal from the control circuit 18. The first embodiment of the present invention is constructed as described above, and it is assumed that within the main body of the color television receiver, for example, the clock circuit 11 and the control circuit 18 are driven by a power source separate from the main body of the receiver. .

First, the power of the television receiver is turned on, and then the clock circuit 11 is turned on, and an initialization signal d is obtained from the circuit as shown in FIG.

In other words, the output of the inverter 28 is logic "1" but the power supply Vp. is applied to the resistor 25 and capacitor 26, an initialization signal d is obtained due to the influence of the capacitor 26. Therefore, Z logic "1" and "0" are added to the input terminal of the AND circuit 21, and the flip-flop circuit is set and the output becomes logic "1". Therefore, the first input terminal of the NAND circuit 24 receives the clock signal, the second
Logic “1” “1” will be added to the third input terminal,
A control signal synchronized with the clock signal c is obtained at the output terminal J. As a result, the back gate signal is turned on and off, so that the back gate B blinks in the display state. Furthermore, since the back gate signal at this time also controls the first gate circuit 123, the character A in the display state also blinks. In this display state, it can be recognized that the clock circuit 11 has just been turned on, and it is not known whether the displayed characters match the current time or not. Usually they don't match. Therefore, the time must be set next. In the case of time adjustment, the time adjustment signal a is applied to the AND circuit 21 and the NAND circuit 24.

Therefore, when there is a time adjustment signal a, logic "0" is always applied to the second input terminal of the NAND circuit 24.
The output holds logic "1". Therefore, when setting the time, the back gate B does not blink, and only the clock advance 3 of the letter A is obtained. Therefore, since the back gate B does not blink, the time can be adjusted in an easily visible state. After the time adjustment is completed, it is necessary to start the clock circuit 11 when the current time and the displayed contents match. Therefore, after four times the time has been set, the flip-flop circuit remains set, so the display contents start blinking again as before. In this case, the display content flashes at intervals of seconds synchronized with the clock signal c to warn that the clock circuit 11 is stopped. Next, when the letter A on the clock circuit 11 matches the current time, it is necessary to operate the start switch 20 to start the clock circuit 11.

When the start switch 20 is operated, the NAND circuit 22
, 23 is reset, logic "0" is added to the third input terminal of the NAND gate circuit 24, and no control signal appears at the output terminal of this circuit, and the back gate and character will no longer blink. Then, constant speed counting of time begins. Therefore, when the displayed content is normal, the display is stable and does not bother the user while looking at the screen. In addition, if there is an abnormality (when you turn on the power or set the time), the display will flash, so you can immediately know this.Furthermore, when setting the time, set the back gate so that it does not flash. You can set the time while the text is displayed in an easy-to-read manner. In addition, since the initialization signal can be obtained even when the clock is out of order due to a power outage, etc., a warning can be obtained by flashing the display. Furthermore, as long as the first gate circuit is controlled by the control circuit, the present invention can be applied even when no back gate signal generating means is provided. In the above embodiment, a device having only the clock circuit 11 has been described, but a second embodiment will be described with reference to FIG. 5, which also includes a timer device as a timer signal generating means.

Note that the same parts as in FIG. 3 are given the same reference numerals, and the explanation will be omitted.
In this case, the clock time signal from the clock circuit 11 is applied to the character generation circuit 12 via the select gate circuit 30.

Further, a set time signal from the timer device 31 is also applied to the character generation circuit 12 via the select gate circuit 30. The select gate circuit 30 can introduce either or both of the clock time signal and the set time signal from the clock circuit 11 to the character signal generation circuit 12, and this can be set by a signal from the changeover switch 32. be done. Moreover, the switching signal from the switching switch 32 is the clock circuit 1 1,
It is also added to the timer device 31, character generation circuit 12 and back gate signal generation circuit 16. This means that if the switching signal from the functional switch 32 selects the time signal of the clock circuit l1, the data sending direction of the select gate circuit 30 is sent from the clock circuit 11 to the character generation circuit 12. Furthermore, since the input data in this character signal generating circuit 12 is only a time signal, a decoder corresponding to a clock time signal is operated. Furthermore, in the back gate signal generation circuit 16, the area of the back gate is only large enough to compare the characters based on the clock time signal, so the generation time is set. Next, if the switching signal from the changeover switch 32 is a signal that displays only the set time signal of the timer device 31, the data sending direction of the select gate circuit 30 is switched from the timer device 31 to the character signal generation circuit 12 direction. Furthermore, in this character signal generation circuit 12, since the input data is only the set time signal,
The decoder corresponding to the set time signal is operated. In addition, in the back gate signal generation circuit 16, since the back gate area may be large enough to compare the characters generated by the set time signal, the generation timing is set in the same way as in the case of only the two-time signal. Next, when a switching signal for simultaneously displaying the characters of the set time signal from the timer device 31 and the clock signal from the clock circuit 11 is added, the 2 select gate circuit 30 detects that the time signal and the set time signal are the character signals. It is switched so that the generation circuit quantity 2 can be introduced.

Further, in the character signal generation circuit 12, a decoder corresponding to each time signal is set to operate. Further, in the back gate signal No. 3 generating circuit 16, the generation time is set so as to create a back gate having an area large enough to compare the characters generated by each time signal. As with the clock circuit, the set time of the timer device 31 can be adjusted in three ways using a time setting switch.

In particular, in the present invention, when both characters representing the clock time signal and characters representing the set time signal are displayed, it is possible to identify which one is the set time signal. will be done.

This means can be implemented in various ways, but for example, when the character signal generating circuit 12 generates a character corresponding to a set time signal, it simultaneously generates a bar 3 above or below the character.
3 may be set as shown in FIG. 6 to distinguish it from the time display.

That is, in FIG. 6, AI is a clock time character, A2 is a set time character, and B1 and B2 are back gates. The set time character A2 also includes a bar 33, and the side to which this is attached can be identified as the set time by the timer device. Furthermore, the bar 3
3 may be blinked in units of minutes, for example. in this case,
A minute-by-minute clock signal may be applied to the character signal generating circuit 12. The reason for setting it in units of minutes is that since the lower digits of the clock time character AI change in units of minutes, if they were blinked at the same time, it would be less distracting than if they were to blink all the time. Alternatively, the bar 33 may be removed and the semicolon indicating the set time may be blinked in minutes.

Furthermore, the colors of the back gates for the time character display and the set time character display may be different for identification.

In color television receivers, color reference signals (3
．． Since the color can be changed depending on the phase of the color signal with respect to 58 MHz, it is sufficient to set the color signal phase of each back gate signal by changing it. It is also possible to distinguish the clock time characters and the set time characters by setting them to different colors. Furthermore, in the present invention, the first,
A display/non-display switching device as shown in FIG. 7 can be provided in the gate circuits 13 and 17 of the second implementation column.

This device uses a flip-flop circuit 34 which is set by the initialization signal d mentioned above.The display changeover switch 35 non-inverts the flip-flop circuit 34, and the output f at this time is the output of the gate circuits 3 and 17. The gate can be rubbed in 'hidden mode' to close it. When the power is turned on, the initialization signal d can be used to set the display mode. Providing this device is convenient because it allows you to turn off the non-display mode when the time display is at a standstill. Furthermore, when the display mode is returned, a switching means for inverting the flip-flop circuit 34 may be provided.As explained above, the present invention can easily identify whether the displayed time of the clock circuit is correct or not. It is possible to easily distinguish between the set time and the clock time, and furthermore, it is possible to provide a time display device in which the time can be easily set.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the time display device of the present invention, FIG. 2 is an explanatory diagram showing a display example of the device shown in FIG. 1, and FIG. 3 is a specific circuit of the control circuit of the device shown in FIG. Example, 4th
5 is a circuit diagram showing the initialization signal generating means, FIG. 5 is a configuration explanatory diagram showing another embodiment of the present invention Z, FIG. Figure 1, 5th
FIG. 3 is a diagram showing an example of display mode switching means provided in the device shown in the figure. 11...Clock circuit, 12...Character signal generation circuit, 1
3, 17... Gate circuit, 14... Character display means,
15... Cathode ray tube, 16... Back gate signal generation circuit, 18... Control circuit, 19... Time setting switch, 20... Start switch, 21... AND circuit, 22, 23, 24... Nasodo circuit, 30...
Select gate circuit, 31... timer device, 32.
...Choice switch. Figure 1 Figure 2 Figure 4 Figure 3 Figure 5 Figure 6 Figure 7

Claims (1)

[Scope of Claims] 1. A time signal generating means, a character signal generating means for generating a character signal from the time signal, and a character display means for driving a cathode ray tube in response to the character signal and displaying characters on the cathode ray tube. , gate means provided on a line for supplying the character signal to the character display means, time adjustment means for stopping the time signal generation means and adjusting the time signal, and supplying an operating power source to the time signal generation means. outputs a signal to open and close the gate continuously when the time signal is supplied, outputs a signal to open the gate when the time is being adjusted, and outputs a signal to open the gate when the time signal is not adjusted, and the time signal generating means stops when the time signal is not adjusted. and a control means including a control circuit that outputs a signal to continuously open and close the gate when the time signal generating means is restarted, and generates a signal to open the gate when the operation of the time signal generating means is resumed. Time display device. 2. The control means includes means for generating a backgate signal around the character, and the backgate signal is used as a signal for controlling the gate signal. time display device. 3. The time signal generating means has a timer signal generating means and sends a switching signal to the character signal generating means or backgate signal generating means so that it can be identified when the clock time and set time are displayed on the character display means. 2. The time display device according to claim 1, further comprising an additional changeover switch.