JPS6027059B2 - interrupt control adapter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an adapter used in addition to an interrupt processing unit (generally an interface control unit: ICU) for connecting a process terminal to a general-purpose computer.

Conventional ICUs have a wide variety of interfaces, but
Among these, in an ICU that transmits only interrupt signals from a process terminal to a host computer, if a plurality of interrupt signals are randomly generated, an interrupt may not be accepted.

The present invention is an adapter that is added to the input side of the ICU to solve this problem, and will be described in detail below with reference to the drawings.

FIG. 1 shows an example of the above ICU, which has a large number of processes (P
The interrupt signals (L to ln) from the signals (o to Pn) are input to each bit of the register R, and the high-speed clock (CLK)
The sample is always held.

When an interrupt signal (positive polarity pulse) occurs in any of L to ln and it is sampled and held, the output of NOR gate GI becomes "0" and AND gate G2 is closed, so the current lo to ln state is frozen. On the other hand, the output of the gate GI is notified to the interrupt processing circuit IRT as an interrupt representative signal, and the mT indicates which bit in the register R is set to "1" by sequentially giving the address AD and transmitting one bit to the multiplexer M. While selecting one value at a time, processing is performed according to the value. (Multiple bits may be set at the same time.) When all bits have been discussed, the
gives a reset signal RST to the register R, and when the output of the register R becomes all "0", the output of the gate GI returns to "1", so that the gate G2 is opened and sample and hold is started again. Here, it takes a considerably longer time (TI) than the period of the clock CLK to read the register R by the above-mentioned clock T.

Therefore, any new interrupt signal input during that period will not be held in register R and will be ignored. FIG. 3a is a time chart showing this. For example, first an interrupt signal lo is generated, and then the IRT is activated at a time TI.
However, the interrupt signal ln generated during that period is ignored. In such a case, the present invention delays the signal ln generated later and inputs it again as an interrupt signal after the time TI associated with L' has elapsed.

FIG. 2 is a circuit diagram of an embodiment of the present invention, in which FFo to FF
n is a flip-flop, G3 to G5 are AND gates, O
SC is a clock oscillator, and PG is a control pulse generator.

The period of OSC is as fast as the above-mentioned CLK (therefore, CLK may be used), and signals generated asynchronously from L to ln are sampled and held at FFo to FFn. However, in these FFo to FFn, only sampling and holding of data "1" is performed in synchronization with the output signal CI of the OSC. Data “0” sample and hold is not performed, and the reset terminal R
It is assumed that it is reset when S falls from "1" to "0". A person skilled in the art can easily create an FF with such a function. PG divides the signal CI,
It has a period T2 slightly longer than the operating time TI of the IRT in the ICU, and its pulse width is equal to that of the interrupt signal lo~ln.
Create a pulse C2 with the same pulse width as the gate G3.
~ Give to one input of G5. Also, each gate G3 to G5
The output of is connected to the reset terminal RS of each FFo to FFn, and also to each input terminal of the register R of the ICU. The operation of this circuit is as shown in FIG. 3b.
First, the signal FFo is sampled and held by the pulse CI, and its held output is output as Lo' from the gate G3 by the pulse C2, and FFo is reset at the fall of the signal. The output L' is set in the register R of the ICU, and processing is performed by the cucumber T for a time TI. On the other hand, the signal ln generated during that time is sampled and held in FFn by the pulse CI, but is not output from the gate and continues to be held until the next pulse of C2 occurs. When the next C2 pulse is reached, it is output from gate G5 as output ln',
At this time, since the previous IRT operation by L' has been completed (because T2>TI), it is set in the register R again and processed by the melon T. As described above, by adding a simple adapter provided with holding means (FFo to FFn) and gate means (G3 to G5) as in the present invention, it is possible to ensure that any interrupt signal that occurs asynchronously is not ignored. will be processed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a general ICU, FIG. 2 is an embodiment of the present invention, and FIG. 3 is a conventional time chart a and a time chart b of an embodiment of the present invention. In the figure, lo to ln are interrupt signals, FFo to FFn are flip-flops, and G2 to G5 are AND gates. Figure 1 Figure 2 Figure 3 'Q) Figure 3 attached)

Claims (1)

[Claims] In an interrupt processing device that has a plurality of interrupt signal input terminals, and when at least one of the interrupt signals is input, the state of each input terminal at that time is frozen for a certain period of time (T1) and the state is read. , an interrupt control adapter inserted before the input terminal, comprising means for asynchronously holding the plurality of interrupt inputs, and a means for holding the plurality of interrupt inputs asynchronously;
1) Providing means for propagating the value of the holding means to the input terminal every longer period (T2), and means for resetting the corresponding holding means when the propagated signal is a specific value. An interrupt control adapter featuring: