JPH0476532B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a pulse width modulation output device. Conventional technology In recent years, microcomputers have become highly integrated due to advancements in LSI technology, with DMA, timer/counter, serial interface, port, A/D
Peripheral hardware such as converters has come to be mounted on a single chip. Among them, those equipped with pulse input/output devices include VTRs, video discs,
It is indispensable for controlling motors in both the consumer field such as CDs and the OA field such as printers, plotters, and floppy disks. Pulse output devices are especially important for controlling external devices such as motors, and when controlling many external devices at the same time,
There also arises a need to provide multiple channels of pulse output. Generally, such pulse output devices include:
Register for controlling pulse width (Pulse
A pulse width modulation output device (hereinafter abbreviated as a “PWM output device”) consisting of a width modulation register (hereinafter abbreviated as a “PWM register”) and a down counter is used. FIG. 5 shows a conventional PWM output device. In the figure, the PWM output device 20 has a PWM section 21 as its basic configuration, and has three units having the same configuration as the PWM section 21, thereby having four types of independent PWM output functions. There are four units included in this PWM output device 20.
1PWM registers 701 to 704 specify the high level period of the output pulse. Also,
The other four second PWM registers 711 to 714 are for specifying the low level period of the output pulse. The four down counters 801-804 are connected to these PWM registers 701-704 and 711-
After presetting the value of 714, clocks 811~
814 and performs subtraction counting. Borrow lines 851-854 of these four counters 801-804 are connected to four T flip-flops 511-554. The output terminals of the T flip-flops 551 to 554 that respond to the clock 560 have a PWM output terminal 60.
1 to 604 are connected. PWM registers 701-704 and 711-
714 is connected to other control devices (not shown) via peripheral bus 900. The operation of one PWM section 21 of the PWM output device 20 configured as described above will be described below, but the other three PWM sections also operate in a similar manner. First, the down counter 801 is connected to the first PWM register 701 from another control device via the peripheral bus.
and the value set in the second PWM register 711 are alternately subtracted and counted. That is, the down counter 801 subtracts and counts the value of the second PWM register 711, and when an underflow occurs, the down counter
1 The value of the PWM register 701 is preset, the borrow line 851 is made active, and the T flip-flop 551 is set. Next, the down counter 801 subtracts the value of the first PWM register 701, and when an underflow occurs, the borrow line 851 becomes active and the T flip-flop 551 is reset. At the same time, the down counter 801 presets the value of the second PWM register 711 and performs subtraction counting. Due to this operation, the down counter 80
1 alternately subtracts and counts the value of the first PWM register 701 and the value of the second PWM register 711, so that the PWM 21 outputs a continuous pulse signal from the PWM output terminal 601. The repetition period of this output pulse signal is determined by the first PWM register 7.
It is determined by the sum of the value of 01 and the value of the second PWM register 711. Further, the high level period of the pulse signal is determined by the value of the first PWM register 701. When changing the ratio of the high level period to the period of the pulse signal output from the PWM section 21 (duty ratio), set values of the first and second PWM registers 701 and 711 can be set from another control device via the peripheral bus 900. change.
The duty ratio changes depending on the timing at which the changed values of both registers 701 and 711 are preset into down counter 801. Therefore, four PWM output terminals 601 to 604
A pulse width modulated pulse signal will be output from each of them. Problems to be Solved by the Invention However, in such conventional PWM output devices, one
It requires two down counters and two PWM registers. As a result, the device configuration becomes large, and especially when it has a large number of PWM output terminals, the device configuration becomes extremely large and expensive. The present invention has been made in view of these points, and it is an object of the present invention to provide a pulse width control output device with a simple configuration. Means for Solving the Problems The pulse width modulation output device according to the present invention comprises: a free-running counter for counting a predetermined count clock; and a device connected to the free-running counter for transmitting the value of the free-running counter. a comparison signal line; a first storage means for holding pulse width modulation information; a timing control section; and under control of the timing control section, the first
a data holding section that holds the pulse width modulation information transferred from the storage means, and a comparison signal that the timing control section outputs when the value held in the data holding section matches the value on the comparison signal line. a second storage means having a comparison function that outputs a coincidence detection signal in response to a timing signal; and a second storage means that sets an output pulse to a first theoretical value in response to an overflow signal of the free running counter; setting the output pulse to a second logical value in response to the coincidence detection signal,
An output control section that generates a pulse output signal by inverting the logical value of the output pulse; Operation In the pulse width control output device configured as described above, the free running counter counts a predetermined count clock, outputs information representing the counting state, and generates an overflow signal when an overflow occurs. Transfer of pulse width modulation information from the first storage means to the second storage means is controlled by a timing control section. The counting state information from the free running counter and the pulse width modulation information are compared by the second storage means, and if a certain relationship is established between the two pieces of information, a detection signal is generated. According to the detection signal and the overflow signal, the output control section controls the pulse width and generates a pulse output signal. Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. here,
This is an 8-bit pulse width modulation output device. -1 Overall Configuration In FIG. 1, a RAM section 100 is connected to a peripheral bus 900 in order to receive pulse width data from another control device (not shown). Further, the RAM section 100 transfers data to a content addressable memory (hereinafter referred to as "CAM") section 200 that can detect a match between the stored data sent via the bus 900 and a count described later. For this purpose, they are connected by a PWM bus 270. A latch 410 that holds the count value of a free running counter (hereinafter referred to as FRC) 400 that counts a predetermined count clock 402.
is connected to the CAM section 200 via the comparison data bus 280.
It is connected to the. Four CAMs 201 forming the CAM section 200
~204 each correspond to four match signal lines 21
1 to 214, the four R-S flip-flops (hereinafter referred to as R-S-FF) section 500 are
It is connected to each of the S-FFs 501 to 504. The four timing control signal lines from the timing control section 450 form the RAM 100.
each of RAM101 to 104 and
It is commonly connected to each of the four CAMs 201 to 204 of the CAM section 200. Further, the overflow signal line 401 of the FRC 400 is connected to the timing control section 450 and the R-
It is commonly connected to each of the four flip-flops 501 to 504 of the S flip-flop section 500. The output terminals of the four RS-FFs 501 to 504 are connected to four PWM output terminals 601 to 604. -2 Functions of each component The functions of each component shown in Figure 1 will be explained. () RAM section 100 The RAM section 100 is a memory for temporarily holding data to be written to the CAM 200, and is made up of four RAMs 101 to 104. When the four timing signal lines 411 to 414 connected to these become active,
PWM the data held in RAM101 to 104
Output via bus 270. () CAM section 200 The CAM section 200 is for comparing two data, and contains four CAMs 201 to 20.
It consists of 4. The data held in the RAM 100 supplied via the PWM bus 270 is compared with the data held in the latch 410 supplied via the comparison data bus 280, and when they match, the four match signal lines 211 to 214 are activated. do. In addition, four timing signal lines 411 to 4
14 becomes active, PWM bus 27
The data on CAM 201-204 is taken in and held. () FRC400 FRC400 is a predetermined count clock of 40
2, and when an overflow occurs, the overflow signal line 401 is activated. () Latch 410 The latch 410
It holds the count value of FRC400,
The data bus 280 constantly compares its retained data.
It is output to. () Timing control unit 450 When the overflow signal line 401 becomes active, the timing control unit 450 outputs control signals to the four timing signal lines 411 to 414, and sequentially transfers the values held in the RAMs 101 to 104 to the CAMs 201 to 204. Forward. () R-S flip-flop section 500 The R-S flip-flop section consists of four reset priority type R-S-FFs 501 to 504. Each R-S-FF501~504
It consists of Each R-S-FF has four
Match signal lines 211 to CAM201 to 204
If each of 214 is active at a predetermined timing, it is reset. Further, each of the coincidence signal lines 211 to 214 is "inactive" at a predetermined timing,
Overflow signal line 4 from FRC400
It is set if 01 is active. FIG. 2 shows a CAM cell 210 for one bit of four CAMs 201 to 204, which includes a data holding section 220, a comparison section 230, a write gate 260, a match signal line 211, a data line 27
1. Comparison line 281, write signal line 261,
The sample signal line 251 has a sample signal line 251, and the match signal line 211 has a precharge gate 240 and a precharge signal line 241. (a) Data line 271 and comparison line 281 The data line 271 consists of a positive logic data line (hereinafter referred to as "Q line") 272 and a negative logic data line (hereinafter referred to as "line") 27
Consists of 3. Similarly, the comparison line 281 is also a positive logic comparison line (hereinafter referred to as "CQ line").
) 282 and a negative logic comparison line (hereinafter referred to as "CQ line") 283. (b) Data holding unit 220 The data holding unit 220 has a write signal line 26
1 becomes active, the write gate 26
0 is opened and the data on the Q line 272 and the data on the line 273 are taken inside and held. (c) Comparison unit 230 The comparison unit 230 includes four comparison gates 231 to
234 and sample gate 250. In order to detect coincidence between the data holding section 220 and the comparison line 281, first the precharge signal line 281 is
Precharge gate 24 with 1 active
By opening 0, the match signal line 211 is precharged. After that, sample gate 250
open. When both the CQ line 282 and the negative logic holding line 223 are "1", or when the CQ line 283 and the positive logic holding line 222 are both "1", that is, the values of the comparison line 281 and the data holding section 220 are When they do not match, the signal level of the match signal line 211 becomes "0". In addition, the comparison line 281 and the data holding section 22
Sample gate 2 when the values of 0 match
When the match signal line 211 is opened, the signal level of the match signal line 211 remains at "1". By performing the precharge operation and sampling operation in this way, the CAM cell 2
10 and the comparison data bus 280 can be detected. Such a CAM cell 210 is connected to the match signal line 2.
11 is connected in parallel to form a CAM 201. When all eight CAM cells are precharged and sampled when they match the comparison data bus 280, the match signal line 211
becomes active. Furthermore, data line 27
1 and comparison line 281, connect four similar configurations in parallel to connect four CAMs 201.
~204 are configured. Overall Operation Next, the overall operation of the above-mentioned configuration will be explained. Here, the basic timing of the PWM output device 10 is based on the timing of each level transition of the count clock 402. period consisting of one clock period
It is designed to perform repetitive operations from T ₁ to _{T 4} . -1 Transfer from RAM section 100 to CAM section 200
The FRC 400 performs an increment operation based on the count clock 402 shown in FIG. 3A in synchronization with time _t1 shown in the same figure (see FIG. 3B). Furthermore, the latch 410 latches the count value of the FRC 400 in synchronization with time _t2 (see FIG. 3C). When the FRC 400 performs counting and overflows, the overflow signal line 401 is activated (see FIG. 3D). This active state continues from time t ₁ to time t ₁ of the next cycle, and times t ₁ to _{t 8} in between are defined as times t _a to t _h . In synchronization with this time point t _a , the timing control unit 4
50 connects the timing control signal line 411 to the period
It is active for T ₁ (see Figure 3). In this way, the timing control signal line 4
11 becomes active, the RAM 101 of the RAM section 100 stores its retained data.
It is output to the PWM bus 270 (see Figure 3 E). Next, in synchronization with time t _b , the CAM section 200
CAM201 is RAM10 on PWM bus 270
A value of 1 is taken in and held (see Figure 3, G). In the same manner, the timing control unit 450
are other timing control signal lines 412, 413
and 414 are sequentially activated during periods T ₂ , T ₃ and T ₄ (see FIG. 3).
The held value is output onto the PWM verse 270 (see FIG. 3, E). Furthermore, in synchronization with the timings of time t _d , t _f and _th , the RAMs 102 and 103
and the retained value of 104 is CAM202, 203
and is written and held in 204 (third
(see figures nu, wa and ta). By such operation, CAM201~2
Information on the high level width of the output pulse is set in 04. -2 Comparison of data Next, CAM201 to 204 and latch 410
The operation of comparing both data will be explained. The CAM 201 precharges the coincidence signal line 211 in synchronization with time _t2 (see FIG. 3, H).
By performing a sample operation in synchronization with the subsequent time point _t3 , all CAM cells of CAM201 and latch 4 are
When all 10 bits match, the match signal line 211 becomes "1". By this,
A match between CAM 201 and latch 410 is detected. In the same way, precharge at time t ₄ ,
CAM202 by sampling at time t ₅
A match is detected (see Figure 3). Also,
Match detection of CAM203 at time _t6 , _t7, time _t6 ,
At t ₁ , coincidence detection of the CAM 204 is performed (third
(See Figures C and R). -3 Pulse Width Varying Operation Next, the output pulse width varying operation will be explained.
RS-FF501, at time _t4 , CAM20
If the coincidence signal line 211 of FRC 1 is active, it is reset, and at time _t4 , the coincidence signal line 211 of CAM 201 is inactive and FRC 4 is reset.
Set when the 00 overflow signal line 401 is active. For example, when data 01H is set in CAM201, the active level of overflow signal line 401 of FRC400 is set to R-S-FF501 at time _t4 .
is detected and enters the set state. And then the next point
At _t4 , the active level of the match signal line 211 of the CAM 201 is detected and the reset state is entered (see FIG. 3, so). With such an operation, the other connected control device can easily set the width of the high level pulse output by simply setting the information data for setting the length of the pulse output high level width in the RAMs 101 to 104. It can be changed. In the embodiment described above, the timing control unit 450 uses the overflow signal 401 to
Data held in RAM101-104 is transferred to CAM20.
1 to 204 is controlled. In contrast, the timing control section 450
Match signal lines 211-21 of CAM201-204
RAM101-104 depending on the active
Data transfer from the CAMs 201 to 204 may be controlled. The timing in that case is shown in FIG. 4, and will be explained below with reference to FIGS. 1 and 4. When the timing control unit 450 detects that the coincidence signal line 211 of the CAM 201 is active, the timing control unit 450 makes the timing signal line 411 active for a period _T1 (see FIGS. 4F and 4G). In this way, while the timing signal line 411 is active, the RAM 101 stores its retained data.
It is output to the PWM bus 270 (see Figure 4 D).
The CAM 201 synchronizes with the time t _b during the period when the timing signal line 411 is active, and outputs the PWM bus 2.
The value held in the RAM 101 on the RAM 70 is fetched and held (see FIG. 4, E). Similarly, the match signal lines 212, 213 and 214 of other CAMs 202, 203 and 204
becomes active, the timing control section 450
activates the timing signal lines 412, 413, and 414 during periods _T2 , _T3, and _T4, respectively (see N, W, and T in FIG. 4). These timing signal lines 412, 413 and 41
4 is active, RAMs 102, 103, and 104 output their held values to PWM bus 270. And CAM202, 203 and 20
4 are timing signal lines 412, 413 and 41
The values held in the RAMs 102, 103, and 104 are captured and held in synchronization with time points t _d , t _f , and _th during the period in which RAM 4 is active. Note that the operations other than the data transfer operation to the CAM section 200 are the same as those in the case described above. In this way, you can convert PWM to RAM, CAM and FRC
By using the overflow of the FRC, PWM output terminals can be added simply by adding RAM and CAM. RAM and CAM have an array structure, so
The hardware is extremely small compared to a data counter. Furthermore, since the CAM has a dedicated bus for comparison in addition to the data bus, there is a large degree of freedom in timing when comparing data. Therefore, multi-channel PWM hardware is easy to implement. Effects of the Invention According to the present invention as detailed above, a multi-channel pulse width modulation output device can be realized without increasing the scale of the device configuration, and is extremely effective in practical use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a pulse width modulation output device according to an embodiment of the present invention. Second
FIG. 1 is a connection diagram showing the circuit configuration of a unit bit cell of the CAM shown in FIG. FIGS. 3A to 3B and 4A to 4C are timing diagrams for explaining the operation of the embodiment of the present invention, respectively. Fifth
The figure is a configuration block diagram showing a conventional example. (Main reference numbers), 10, 20...Pulse width modulation output device, 100...RAM section, 200...
CAM section, 210...CAM cell, 211-214
... CAM coincidence signal line, 220 ... data holding section, 230 ... comparison section, 270 ... PWM bus, 280 ... comparison data bus, 400 ... free running counter (FRC), 401 ... overflow signal line , 411-414...timing signal line, 500...R-S flip-flop unit, 701-704, 711-714...PWM
Register, 801-804...down counter,
900... Area bus.

Claims (1)

[Scope of Claims] 1. A free-running counter that counts a predetermined count clock; a comparison signal line that is connected to the free-running counter and transmits the value of the free-running counter; and holds pulse width modulation information. a first storage means for storing the data; a timing control unit;
a data holding section that holds the pulse width modulation information transferred from the storage means, and a comparison signal that the timing control section outputs when the value held in the data holding section matches the value on the comparison signal line. a second storage means having a comparison function that outputs a coincidence detection signal in response to a timing signal; and a second storage means that sets an output pulse to a first theoretical value in response to an overflow signal of the free running counter; setting the output pulse to a second logical value in response to the coincidence detection signal,
A pulse width modulation output device comprising: an output control section that generates a pulse output signal by inverting the logical value of an output pulse; and a pulse width modulation output device.