JPS6027269B2 - voltage conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage conversion circuit, and more particularly to a circuit for obtaining relatively low voltage direct current from relatively high voltage alternating current or pulsating current.

The purpose is to obtain a voltage conversion circuit that has little power loss for conversion and can obtain a large DC current relative to the effective input current value.

Hereinafter, the present invention will be explained in detail based on circuits of embodiments. In FIG. 1, P, P2 are terminals to which an AC input signal is applied, and P3 and P4 are terminals from which a DC output signal is obtained.

A diode D, a capacitor C, a diode D3, and a capacitor C2 are connected in series between the terminals P and P2. Further, a diode D2 is connected between the connection point between the capacitor C and the diode D3 and the terminal P2. Q, R, and D are npn transistors, resistors, and diodes for configuring an output circuit as described later. In the above circuit, terminal P2 is maintained at the reference potential of the circuit. During the period when the AC signal applied to terminal P is at a positive level, diode D, capacitor C,
, diode D3, and capacitor C2. As a result, capacitors C and C2 are charged in series from the AC signal source. The input is Figure 2A
As shown in , the peak value is E. If the voltage is a sine wave voltage of volts, the sum of the fin pressures generated on capacitors C and C2 as a result of charging will be approximately E, volts.

By choosing the capacitances of C and C2 to be equal,
Since the amount of charge between the terminals of each capacitor C is equal, the voltage between the terminals of each capacitor C is half of the peak voltage E, respectively.
If the input sinusoidal voltage in Figure 2A is greater than or equal to E,/2, diode D2 is reverse biased and capacitor C,
As shown by the curve in FIG. 2B, a voltage approximately equal to the input voltage appears between the line to which one terminal is connected and the terminal P2 or F4.

If the input sine wave voltage key is equal to or less than E,/2, diode D2 becomes 0 bias or forward biased, and a voltage E,/2 equal to the charging voltage of capacitor C is connected between the line and terminal P2 or P4. A voltage of volts appears. Situation P
On the one hand, a current is supplied from the line through the diode D4 to a load (not shown) connected between the line 3 and P4.

Transistor Q. receives the voltage generated in the diode D4 between the base and emitter, so that a current is supplied to the load from the diode on the other hand through the transistor Q. When the power supply voltage is greater than E,/2, current from the power supply flows through transistor Q. Power supply voltage is E,/2
When the diode D2 becomes smaller than , the diode D2 exhibits a forward characteristic with respect to the discharge of the capacitor C, so that the charging voltage of the capacitor C is connected between the wire and the terminal P2 or P4 as described above. appears. During this period, the base-collector voltage required for the operation of the transistor Q appears due to a slight drop in the potential of the line due to the discharge of the capacitor C2. Current is supplied from the transistor Q to the load. In the above circuit, the discharge period of capacitor C is shorter than the discharge period of capacitor C2, so the current amplification factor of the transistor and the base current setting resistor R are adjusted to increase the discharge current value of capacitor C. , are set appropriately, and the average charge and discharge charges of the two capacitors are made equal. In the circuit of FIG. 1, an output voltage of approximately E,/2 can be obtained by making the capacitances of capacitors C, , C2 equal. This circuit uses a capacitor to reduce the voltage, so there is less power loss for conversion.

Furthermore, since the capacitor is connected substantially in series with the charging path and the capacitor is connected in parallel with the charging path, a large direct current can be obtained compared to a small current from an alternating current power source. Furthermore, in the present invention,
Since transistor Q operates as an emitter follower transistor with low output impedance, terminals P3 and P
Regardless of changes in the load connected between terminals P2 and
This has the advantage that the output voltage during P4 is stabilized.

FIG. 3 shows a circuit of another embodiment.

In this circuit, three capacitors C and C2 are connected in series to the charging path from the AC power supply connected between terminals P and P2, so by making the capacitances of C and C3 equal, the input AC voltage Almost one-third of the peak value of
DC voltage can be obtained. FIG. 4 shows an example using a circuit 1 which is the same as the circuit in FIG. 1, and a circuit 2 in which the diodes of the circuit in FIG. 1 are connected in reverse and the transistors are replaced with pnp type transistors.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is an operating waveform diagram thereof, and FIGS. 3 and 4 are circuit diagrams of other embodiments. P,, P2, P3, P4, P5...Terminal, D,, D2, D
3, D4, D5, D6・"Diode, Q,, Q2...Transistor, C,,C2,C3...Capacitor, R,
, R2...resistance. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 A pair of terminals P_1 to which alternating current or pulsating current is applied,
P_2, a first capacitor C_1, a second capacitor C_2, a first switch means D_1, a second switch means D_2, a third switch means D_3, and an emitter follower transistor Q_1. One terminal of the first switching means D_1 is connected to one terminal P_1 of the pair of terminals P_1 and P_2, and the terminal P_1 of the pair of terminals P_2 is
1, the second switch means D_ to the other P_2 of P_2.
2 is connected to the first switch means D.
The first capacitor C_1 is connected between the other terminal of the second switch means D_2 and the other terminal of the second switch means D_2, and the third switch means is connected to the other terminal of the second switch means D_2. Connect one terminal of D_3,
The second capacitor C_2 is connected between the other terminal of the third switch means D_3 and the other terminal P_2 of the pair of terminals P_1 and P_2, and the collector and base of the emitter follower transistor Q_1 are connected. 1st above
connected to the other terminal of the third switch means D_1 and the other terminal of the third switch means D_3;
A voltage conversion circuit characterized in that an output is obtained from the emitter of the emitter follower transistor Q_1.