JPS602739B2 - Circuit with equivalent resistance using FET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an equivalent resistance circuit using FETs, and particularly to an equivalent resistance circuit having a circuit configuration that is easy to fabricate on a semiconductor integrated circuit chip.

The background of the present invention will be explained below with reference to FIG.

Although the present invention will be described assuming an n-channel FET, this has nothing to do with the essence of the operation, and it goes without saying that a similar circuit can be constructed with a p-channel type. In FIG. 1, 1 is a human body connected to a commercial AC line through an air volume 2. 3 is an FET that detects contact or proximity of a human body, 4 is a diode for rectification, and 5 is a resistor for discharging.

6 and 7 are a capacitance and a resistance, respectively, forming a time constant.

Note that 6 and 7 only need to maintain sufficiently large time constants with respect to the commercial frequency as will be described later, and when a junction capacitance is used as the capacitor 6, the resistor 7 may be an equivalent leak resistance thereof. When a human body touches or approaches point A, the stray capacitance is usually about S F, which is sufficiently larger than the input capacitance 9 of the FET 3, and induces a voltage of several volts to several tens of volts at the gate of the FET 3. Therefore, a rectified waveform such as V shown in the figure is obtained. Point B is charged when a positive voltage is applied to the gate of FET 3, and discharged with a time constant formed by 6 and 7 after V^ reaches its peak. Therefore, a waveform like VB can be obtained by setting this time constant to be equal to or greater than the period of 20 ms of the commercial AC line. For this reason, 8 input terminals B to the system
It can be seen that a single contact or proximity causes a single pulse to be applied, resulting in the desired contact or proximity detection circuit operation. FIG. 2 shows another example of a neighbor detection circuit.

Contrary to Figure 1, when the human body touches or approaches point A, V^
While a positive voltage is applied to FETII, FET II conducts and makes point B the ground potential, but when the human body moves away from point A,
4, point B is charged, resulting in a waveform like V8 in the figure. As can be seen from the above explanation, the time constant of the input circuit is formed by the resistors 5 and 13 and the capacitors 9 and 18, but this is 20ms in order to prevent unnecessary charges from being stored at point A.
The smaller the size, the better.

Furthermore, if the impedance of the input circuit is low compared to the capacitance of 2,101, a sufficient voltage cannot be induced at point A. The impedance of stray capacitance varies depending on the location, but when a human body approaches or contacts a switch, it is in close proximity to the system, and a voltage is generated by capacitive coupling from the power transformer. As a result of the experiment, resistances 5 and 13 are at most MQ
It was found that sufficient voltage could be obtained. Capacitors 6 and 15 connected to point B and resistor 7 for discharging or charging
, 14 is preferably greater than 20 ms. The advantage of this type of contact circuit is that the circuit construction is very simple and therefore can be constructed at a very low cost.

Further, although integration was difficult in the conventional example, a circuit can be constructed from resistors, capacitors, and FETs, and integration is extremely easy. For example, MOS-L such as electronic desk calculator
In an electronic system using SI, this circuit can be used as a MOS-
can be manufactured on the same substrate and in the same process as 1. Therefore, instead of the conventionally required keyboard, only a switch made of a metal piece can be used, and the system cost can also be reduced. In an integrated circuit, a problem in realizing the basic circuits shown in FIGS. 1 and 2 is that it is difficult to create a large resistance value in an integrated circuit.

For example, since the capacitances 15, 18, 6, and 9 in Figs.
In order to make it larger than s, it must be set to 2000mMQ, but among these, low resistance 5, 13 can be realized by, for example, polycrystalline silicon or FET. On the other hand, equivalently 20000M at 7,1 4
In order to realize a resistance of 0 or more, the following steps may be taken.

FIG. 4 and FIG. 5 show an embodiment of the present invention, in which the capacity 32,
Alternatively, a method of equivalently configuring a time constant of 45 ws and about 20 ws is shown.

In the figure, ET35, 34 and 41, 42 are clocks ◇,,? 2 are turned on at different times. Therefore, in the case of Fig. 4, the charge stored in the capacitor 32 is
When is at a high level, it is divided into 33 capacities, and then ◇
2 becomes high level, only the charge in the capacitor 33 is discharged. In addition, in Fig. 5, the capacity is 4 due to ◇, contrary to the above.
4 is once charged, then the capacitor 45 is charged by the charge transferred from the capacitor 44 according to step 2. These two FETs 34, 35, or 4
1, 44 and capacitors 33, 44. The circuit formed by capacitors 33, 44 acts as a resistance steel with R and R values. Here is f. , is the frequency of 2. Therefore, C
By reducing 2 or f, it is possible to achieve an equivalently high resistance value, that is, a time constant of about 20 s. Therefore, for example, 50 to 60 days, which is the frequency of the commercial AC line, 2. 2
By using this, the time constant formed by this circuit and the capacitors 32 and 45 can be easily set to about 20 s. FIG. 6 is a plan view of the actual integrated circuit layout of the embodiment shown in FIG.
1 corresponds to the input capacitance 29 of the FET 31 and the gate,
53 is the capacitor 32, 54 and 56 are FETs 35 and 34,
57 correspond to the capacitance 33, respectively. Approximately 20 from Figure 6
It can be seen that the chip can be integrated in an area of about 1,000 French yen, and the chip area is extremely small. FIG. 3 shows another example of the equivalent resistance circuit.

FET 25 is biased to a value of gate voltage V, which is a low current region below the threshold voltage where the drain current of FET 25 flows from 10-10 to 10-11 A. In such a case, the charge of the capacitor 23 decreases at a constant rate over time, and the rate of this decreases as the current increases by 10-11
When A, if the capacitance is lpF, it will drop by about 2V in 20ms, producing the same effect as when a large low resistance is attached.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams explaining the proximity detection circuit, Figure 3 is a diagram explaining the proximity detection circuit;
6 to 6 are diagrams showing embodiments of the present invention. Human body...1,17,19,27,47,37, Capacity of human body and commercial AC line...2,10, System...8,16,26,36,46,69, Input capacity·
...9,18,22,29,39, Rectifier diode...4,12,21,30,49,40, Input resistance...5,13,20,28,38, Input FET
...3, 11, 24, 31, 51, 43, capacity...6, 15, 23, 32, 45, 33, 44, 57,
FET...25, 34, 35, 41, 42, 54, 56
,53,Resistance...7,14,Contact hole,・
…” 48, 50, 52, 55.

Claims (1)

[Claims] 1 First and second FETs are connected in series, the first and second FETs have a first capacitor connected to the series connection point, and a second capacitor is connected to one end of the source or drain other than the series connection point.
the first and second capacitors have other ends fixed to ground potential, the other ends of the sources or drains are fixed to the power supply potential or ground potential, and the first and second capacitors F of
1. A circuit having an equivalent resistance using an FET, characterized in that first and second clock pulses are applied to the gates of the ET, respectively, and the first and second FETs are turned on at different times.