JPS6027425B2 - Hard error detection method for memory devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hard error detection method for a memory device that makes it possible to easily detect the occurrence of burst hard errors in a memory device.

FIG. 1 shows an example of the configuration of a storage device, with 1
2 indicates a memory element, 2 an address decoder, and 3 a read data register.

The memory element 1 is, for example, 64K×1 bit, and one word of read data consists of 64 bits and 18 parities. When configuring a 64K word storage device, 6
It is sufficient to arrange 72 xl-bit memory elements in parallel, apply the same address information to the address terminals of each memory element, and apply a chip select signal at the same time.

By the way, when a one-bit error occurs in a burst in a memory element corresponding to a certain bit position, early detection and discrimination of this memory element is important from the viewpoint of memory maintenance such as replacing the memory element. As memory devices become highly integrated these days, intermittent failures are more likely to occur due to the influence of wires and the like. For this reason, if a memory element with a fixed burst failure is left unattended, if an intermittent failure like the one described above occurs within the same word, it will become impossible to correct the error and the data processing device will go down. I end up. One possible method for detecting the occurrence of burst-like hard failures in a memory element is to perform a read operation on all memory addresses contained in the memory element, but this method is Even though it is possible to check for errors, if they are not checked (for example, fixed 1-bit errors), it takes a huge amount of time and has a serious impact on the performance of a system whose constituent unit is memory. It is not appropriate because it gives The present invention is based on the above consideration, and provides a hard error detection method for a memory element that can easily and quickly detect the occurrence of burst hard errors in a memory element. is intended to provide.

Therefore, the hard error detection method for memory elements of the present invention is designed to detect a 1-bit error in a memory device having a plurality of memory elements that are supplied with the same address information to their address terminals and are enabled to operate at the same time. When detected, perform the issuing operation a predetermined number of times using the FF address with one or more bits inverted as the issuing address, count the number of times a 1-bit error occurs at the same bit position, and calculate the counted value. This method is characterized in that it is determined whether or not a burst hard error is occurring. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a diagram illustrating the basic concept of a hard FF detection method for a memory device according to the present invention, and FIG. 3 is a block diagram of one embodiment of the present invention.

Now, assume that a 1-bit F- is detected at address "1010".

When a one-bit error is detected, one or more bits in the error address are inverted as shown in FIG.

In the example shown in FIG. 2, first, the leftmost bit, ie, the first bit, of the error address is inverted to create an address "0010", and a read access is performed using this address.
Assuming that a 1-bit error is detected in the data read from the address "0010" and the ef bit is at the same bit position, the counter is incremented by 1. Next, invert the second bit of the error address "1010" and read "
1110" is generated, and data is read from the address "1110." It is also determined whether a 1-bit error has occurred in this data, and if a 1-bit error has occurred, it is checked whether or not it is at the same bit position, and if it is at the same bit position, , turn the counter to 11. Next, invert the third bit of the error address "1010" to generate "1000", read the data from the address "1000", check whether a 1-bit error has occurred, and If an error has occurred, it is checked whether the bit positions are the same, and if the bit positions are the same, the counter is incremented to 11. The above process is performed a predetermined number of times, and the count value of the counter is checked.
If the count value of the counter is greater than or equal to the predetermined value N,
It is determined that a hard error has occurred in a burst,
Processes such as replacing the FF memory element with an alternative memory chip are performed. FIG. 3 is a block diagram of one embodiment of the present invention, in which 4 is an address register, 5 is an AND gate, 6 is an error address register, 7 is an exclusive OR circuit, and 8 is a fixed data register. , 9 is a right 1-bit shifter, 1 is a river counter, 11 is an ECC circuit, 12 is a syndrome register, 1''3 is a syndrome storage section, 1
4 is a comparison circuit, and 15 is a 1-bit error detection flip.
Flop and MS indicate main memory, respectively.

Next, the operation of the embodiment shown in FIG. 3 will be explained.

The data retrieved from main memory MS is set in read data register 3 and error checked by ECC circuit 11. 1-bit FF error
Will be checked.

If a 1-bit error has occurred, 1-bit error detection flip-flop 15 is set and the address
The contents of register 4 are held in error address register 6, and exclusive OR circuit 7 performs an EOR operation on the contents of error address register and fixed data register 8.

The EOR result is set in address register 4. Simultaneously with the above operation, the contents of fixed data register 8 are shifted one bit to the right by shifter 9, and the shift result is rewritten to fixed data register 8. Furthermore, at the same time, the syndrome created by the ECC circuit 11 is stored in the syndrome storage section 13 via the syndrome register 12. main memory MS by the address modified by the contents of fixed data register 8.
Data is extracted from

If a 1-bit error is detected, ECC circuit 1
The syndrome created in step 1 and the syndrome stored in the storage unit 13 are compared, and if they match, the contents of the counter 10 are incremented by 11.

The contents of the error address are then changed by the contents of fixed data register 8 and set in address register 4, and the contents of the fixed data register are shifted one bit to the right. After a new address is set in address register 4, data is read from main memory MS. After performing the above unit processing a plurality of times, the contents of the counter 10 are compared with a predetermined value.

If the count value of the counter 10 is greater than or equal to a predetermined value, it is determined that a burst of hard errors has occurred. Errors based on the Q-line as mentioned earlier and hard errors that occur in bursts have different error patterns, so the data pattern to be set in the threshold values and fixed data registers must be set in the structure of the memory element. You can create it accordingly. As is clear from the above description, according to the present invention, it is possible to detect the occurrence of a burst hard error in a memory element in a short time with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a storage device, FIG. 2 is a diagram explaining the basic concept of the present invention, and FIG. 3 is a block diagram of one embodiment of the present invention. 1...Memory element, 2...Address decoder, 3
...Read data register, 4...Address register, 5...AND gate, 6... ．．・F address register, 7...exclusive OR circuit, 8・
...Fixed data register, 9...Right 1-bit shifter, 10...Power counter, 11...ECC circuit, 12
...Syndrome register, 13...Syndrome storage unit, 14...Comparison circuit, 15...
...1-bit error detection flip-flop, MS...
main memory. Sai - Out of the picture Z figure Sai 3 figure

Claims (1)

[Claims] 1. When a 1-bit error is detected in a storage device that has multiple memory elements that are supplied with the same address information to the address terminals and become operational at the same time, the error address is inverted by 1 bit or multiple bits. The read operation is performed a predetermined number of times using the read address as the read address, and the number of times a 1-bit error occurs at the same bit position is counted. Based on the counted value, it is determined whether or not hard errors are occurring in bursts. A hard error detection method for a memory element characterized by determining.