JPS6027471B2 - Noise removal circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise removal circuit that can remove noise in color video signals.

Conventionally, there are noise removal circuits as described below for removing noise from a video signal including noise obtained from a magnetic recording/reproducing device or the like.

That is, one method is to supply the video signal to the low-pass reactor waver and the Takagi passer waver, respectively, and adjust the output level of the high-pass reactor waver to zero when the absolute value of the input level is less than a predetermined value. , is supplied to a coring circuit (a type of non-linear circuit) in which the relationship between the input level and the output level is linear when it is above a predetermined value, and the output of the low-pass reactor waver and the output of the coring circuit are sent to a synthesizer. This is a noise eliminator-type noise removal circuit that obtains a video signal from which noise, especially Takagi noise, has been removed by supplying and adding the signals. The other method is to supply the video signal to a Takagi pass-through wave generator, and change the output of the Takagi pass-through wave generator to zero when the absolute value of the input level is above a predetermined value, and to the input level when the absolute value is below a predetermined value. By supplying the video signal to a stripping circuit (a type of nonlinear circuit) that has a linear relationship with the output level, and supplying the video signal and the output of the stripping circuit to a synthesizer and subtracting the latter from the former, noise, especially Takagi This is a noise canceller-type noise removal circuit designed to obtain a video signal from which noise has been removed.

However, with such conventional noise removal circuits, in addition to insufficient separation of the signal component and noise component in the video signal, the signal component of the output of the Takagi pass-through filter is subject to large distortion in the core IJ circuit or stripping circuit. As a result, fine brightness changes in areas with little brightness change, such as the background of the reproduced image, disappear, and as a result, a scale-like pattern is generated in the image corresponding to the part with gradual brightness change.

In addition, on the contrary, smear occurs in an image corresponding to a portion where the luminance changes sharply, and the sharpness of the image deteriorates. In order to remove noise from a video signal without suffering much image degradation, the signal component and noise component should be better separated, and then signal processing for noise removal should be performed. In this case, even if the signal is distorted, the resulting deterioration in image quality should be made so that it is not so noticeable from the human visual characteristics. As a noise removal circuit that satisfies these conditions, the applicant has proposed a noise removal circuit using an orthogonal transform circuit as shown below.

That is, the noise removal circuit consists of a cascade circuit consisting of a serial/parallel conversion circuit, an orthogonal conversion circuit, a nonlinear circuit (for example, a coring circuit), an inverse conversion circuit, and a parallel/serial conversion circuit. A video signal containing noise is supplied, and a video signal from which the noise has been removed is obtained from the parallel/serial conversion circuit. This is a type of noise eliminator type noise removal circuit. Here, orthogonal transformation and its inverse transformation will be explained.

Now, if we represent the block of the video signal sequence that is the input signal as ×, the block of the output signal sequence as Y, the orthogonal transformation matrix as A, and the inverse transformation matrix as B, then Y
=AX X=BY...'1) B=
AT...'21 (However,
AT is a perpendicular matrix)
．． ．． 、． ■Therefore, if the input signal is orthogonalized, y, = a, .
×, 10a, 2 × 20…・”+a, nxny2=a2, ×
, 10a2×20...+a2nxn.・・・． ...'6
1yn near aMXI+a rudder
10b, nyn・…--{7}×nnibMyl+bboard y2
10...10 bnnyn Therefore, the transform coefficient, ie, the orthogonal transform output Y, is a linear combination of the row vector and the input signal.

As this orthogonal transformation, Walsh, Hadamard, Haar, and other orthogonal transformations can be used, but they have the characteristics that they can extract the characteristics of the video signal well and that the inverse transformation can be performed in the same procedure as the transformation. Hadamard transform is preferred.

The present invention relates to a noise elimination circuit using such an orthogonal transform circuit, which, like the noise eliminator type described above, can better separate signal components and noise components, and can be used in subsequent signal processing. Even if the signal is distorted, the resulting deterioration in image quality will not be as noticeable due to human visual characteristics, and when processing video signals by quantizing them, the circuit configuration will be easier compared to the noise eliminator type. This paper aims to propose a simple noise removal circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

This embodiment is a case of a noise removal circuit for a color video signal such as an NTSC system, and the embodiment will be explained with reference to FIG. 1, which shows the overall configuration. In this embodiment, when a color video signal is quantized and subjected to post-noise removal signal processing, the color video signal is separated into a luminance signal and a carrier color signal, and then noise removal signal processing is performed on each of them. . Reference numeral 1 denotes an input terminal to which a color video signal (NTSC color television signal) containing noise is supplied.

The color video signal from this input terminal 1 is sent to the A-D converter 2.
will be supplied and digitized. The color video signal from the input terminal 1 is supplied to a sync separation circuit 3, from which a horizontal sync signal and a color burst signal are separated, and these signals are combined with a clock signal generator 4. Then, the clock signal from the clock signal generator 4 is used as a sampling signal to the A-D converter 2 and the D-A converter 14 (to be described later).
supplied to The frequency of this clock signal is selected to be twice or more, for example, four times in this example, the color subcarrier frequency fsc (=3.58 MHz). The digital color video signal output from the A-D converter 2 is supplied to a separation circuit 5, where it is separated into a digital luminance signal and a digital carrier chrominance signal, which are then sent to a luminance signal noise removal circuit 6A and a carrier chrominance signal noise removal circuit 6B, respectively. Supplied.

The luminance signal noise removal circuit 6A includes a first serial/parallel conversion circuit 7A, a first orthogonal conversion circuit 8A, and a first nonlinear circuit 9.
A - First inverse conversion circuit 10A - First parallel/serial conversion circuit 1 1A vertical stripe circuit and the output of the cascade circuit, that is, the luminance signal, from the output of the 1A vertical stripe circuit and the luminance signal delayed and phase-matched through the delay circuit 96A. and a first synthesizer 95A that subtracts noise components in the filter. The carrier color signal noise removal circuit 6B includes a second serial/parallel conversion circuit 7B - a second orthogonal conversion circuit 8B - a second nonlinear circuit 3B - a second inverse conversion circuit 108 - a second parallel/serial conversion circuit 118 cascaded circuits and a second synthesizer 95B that subtracts the noise component in the output of the cascade circuit, that is, the carrier chrominance signal, from the phase-aligned output after the carrier chrominance signal is delayed through a delay circuit 96B. The luminance signal from which noise has been removed from the luminance signal noise removal circuit 6A is supplied to the synthesizer 13 through the delay circuit 12 for phase compensation, and the carrier color signal from which noise has been removed from the carrier color signal noise removal circuit 6B is supplied to the synthesizer 13. are supplied to this synthesizer 13, and the equally phased ones are added,
The summed output is supplied to the DA converter 14, and its output is supplied to the output terminal 16 through the low-pass filter 15, thereby obtaining a color video signal from which noise has been removed.

Next, the circuits of each part of the noise removal circuit shown in FIG. 1 will be explained with reference to FIG. 2 and subsequent figures.

First, referring to FIG. 2, the separation circuit 5 will be explained. Although the separation circuit 6 can be configured with a low-pass wave generator and a belt-pass wave wave generator that pass the luminance signal and the carrier color signal, respectively, in this embodiment, a comb-shaped wave generator is used. It is a separate circuit. The digital color video signal from the above-mentioned A-D converter 2 is input from the input terminal 17 to the comb wave generators 18a, 1.
8b, and each output thereof is supplied to combiners 23 and 24. In the synthesizer 23, the output of the comb-shaped wave generator 18a and the output of the other comb-shaped wave generator 18b are supplied to the band elimination wave generator 22 whose band center frequency is the color subcarrier frequency fsc. The digital luminance signal is obtained at the output terminal 25. In the combiner 24, the output of the belt-removal waveform generator 22 is subtracted from the output of the comb waveform waver 18b, and a digital carrier color signal is obtained at the output terminal 26. The comb waveform generator 18a is configured such that the input signal from the input terminal 17 and the signal which is supplied to the delay circuit 19 and delayed by one horizontal period are added at the combiner 20. In addition, the other rectangular wave generator 18b is connected to the input terminal 17.
The output signal from the delay circuit 19 is subtracted by the synthesizer 21 from the input signal from the delay circuit 19. The belt-removal wave generator 22 has a digital circuit configuration, and FIG. 3 shows its specific configuration.

That is, each input signal (for example, a 9-bit binary encoded signal) from the input terminal 28 has a delay amount of 2 sampling periods.
It is supplied to the combiner 31 through the delay circuits 29-30 which are multipliers, where it is added to the input signal from the input terminal 28, and the summed output is supplied to the attenuator 32 with the attenuation ratio of Attenuator 32 from the output of delay circuit 29
so that the output of is subtracted and obtained at the output terminal,
This band-removal reactor wave device 22 is configured. Next, the specific configuration of the serial/parallel conversion circuits 7A and 7B will be explained with reference to FIG.

The circuits 7A and 7B in FIG. 4 are used to convert a plurality of consecutive luminance signals and carrier color signals in a certain horizontal scanning section, for example, four This is a serial/parallel conversion circuit for orthogonally converting signals corresponding to unit areas (one unit area is, for example, one pixel). For the input signal Si from the input terminal 36, the delay amount is equal to the sampling period in the serial/parallel converting circuit 7A for the aya signal, and the delay amount is equal to the sampling period in each of the serial/parallel converting circuits 78 for the carrier color signal. Both are delayed through delay circuits 37-38-39 whose delay amount is equal to four times the sampling period, that is, equal to the color subcarrier period, to obtain an output signal Si4 at the output terminal 40, and an output signal Si4 is output from the delay circuit 38 to the output terminal 41. The serial/parallel conversion circuits 7A and 7B are constructed by obtaining the signal Si3, the output signal Si2 from the delay circuit 37 to the output terminal 42, and the output signal Si from the input terminal 36 to the output terminal 43.
Next, the serial/parallel conversion circuit 7A of the noise removal circuit in Fig. 1,
The parallel-to-serial conversion circuits 11A and 11B will be described with reference to FIG. 5 when the circuit 7B described in connection with FIG. 4 above is used.

49, 51, and 53 are parallel-to-serial conversion circuits 11A for luminance signals whose delay amounts are equal to the sampling period;
For 1B, the delay amount is 4 times the sampling period.
The delay circuit is equal to twice the color subcarrier period.

In the parallel/serial conversion circuits 11A and 118, the input signal S'i from the input terminal 45 is transferred to the delay circuit 4.
9 and delay it, and its delayed output and input terminal 46
The synthesizer 50 adds the input signal S'i2 from the input terminal 47 and supplies it to the delay circuit 51, and the synthesizer 52 adds the delayed output and the input signal S'i3 from the input terminal 47 to the delay circuit 51. 53, and the delayed output and the input signal from the input terminal 48 are added in a synthesizer 54 to obtain an output signal S'i at an output terminal 55. Next, another specific configuration of the serial/parallel conversion circuits 7A and 7B will be explained with reference to FIG.

The circuits 7A and 78 in FIG. 6 are used to convert luminance signals and carrier color signals in a plurality of adjacent horizontal scanning sections, in this example two horizontal scanning sections, in the orthogonal transform circuits 8A and 8B of the noise removal circuit in FIG. A serial/parallel conversion circuit for orthogonally converting signals corresponding to a plurality of corresponding and continuous unit areas, for example, two unit areas (one unit area is one pixel, for example), for example, four unit areas in total. It is. A serial/parallel conversion circuit 7 converts the input signal Si from the input terminal 36 into a luminance signal.
In A, the delay amount is equal to one horizontal period and the sampling frequency, and in the serial/parallel conversion circuit 7B for the carrier color signal, the delay amount is equal to two horizontal periods and four times the sampling period, respectively. 158 to obtain an output signal Si4 from the output terminal 4, an output signal Si3 is obtained from the delay circuit 57 to the output terminal 41, and the input signal from the input terminal 36 is sent to the direct/parallel conversion circuit 7A for the luminance signal. In the case of the delay circuit 5, the delay amount is equal to the sampling period, and in the case of the serial/parallel conversion circuit 7B for the carrier color signal, the delay amount is equal to four times the sampling period.
9 and delays the output signal Si2 to the output terminal 42.
output signal Si, from the input terminal 36 to the output terminal 43.
The serial/parallel conversion circuits 7A and 7B are constructed in such a way as to obtain the following. Next, the parallel/serial conversion circuits 11A, 11 in the case where the ones explained in connection with FIG. 6 above are used as the serial/parallel conversion circuits 7A, 78 of the noise removal circuit of FIG.
B will be explained with reference to FIG.

61, 63, and 65, in the parallel/serial conversion circuit 11A for the luminance signal, the delay amount is equal to the sampling period and one horizontal period, and in the parallel/serial conversion circuit IIB for the carrier color signal, respectively. The delay amount is four times the sampling period, four times the sampling frequency, and two horizontal periods.

In the parallel/serial conversion circuits 11A and 11B, the input signal S'i3 is supplied from the input terminal 46 to the delay circuit 61 and delayed, and the delayed output and the input signal S'i4 from the input terminal 45 are The synthesizer 62 adds the input signal S′i, from the input terminal 48 to the delay circuit 63, and the synthesizer 64 adds the delayed output and the input signal S′i2 from the input terminal 47. The delay circuit 65 is supplied with V, and the delayed output and the output signal from the combiner 62 are added in the combiner 66 to obtain the output signal S'j at the output terminal 55. Next, the specific configuration of the orthogonal transform circuits 8A and 8B shown in FIG. 1 will be explained with reference to FIG. 8.

In this example, fourth-order Hadamard transform circuits are used as the transform circuits 8A and 8B. The fourth-order Hadamard transform matrix ratio is as shown in the following equation. Note that 2 to 4 rows of the formula leg matrix can be interchanged.

In Fig. 8, 68 to 71 are input terminals, 72 to 75 and 77 to 79 are combiners, of which 72, 74, and 79 are addition combiners, 73, 75, 77, and 78 are subtraction combiners, and 81 to 8 are
3 is an output terminal.

Then, in the orthogonal transform circuits 8A and 88, the input terminals 68 to
When input signals Si, ~Si4 are supplied to the output terminals 71, output signals S″i2~S″4 that satisfy the following equation are output to the output terminal 81.
It is constructed so as to be obtained from ~83. S″i2=Si
, 10Si2-Si3-Si4S''i3=Si,-Si2
1Si30Si4...'9'S''
i4=Si, -Si20Si3-Si4Although the following formula is normally obtained as the Hadamard transform output, it is not used in a noise canceller-type noise removal circuit, so it is not created.

Si,=Si, 10Si20Si30Si4...
(9') Next, let us examine the properties of the orthogonal transformation outputs S''i2 to S''i4 and the unused output S''i, obtained in this way.

Among the orthogonal transform outputs, the low-order transform output S''i, in this example, tends to include many low frequency components, and conversely, the high-order orthogonal transform output, that is, S ″
i2 to S″i4 are in the cervical direction containing high frequency components.8
This trend is even stronger in the case of high-order transformation matrices such as the next or IQ order.

In other words, by orthogonally transforming a video signal, this video signal is concentrated in the low-order orthogonal transform output, and the higher the order, the less it appears in the orthogonal transform output. It is something. On the other hand, noise contained in a video signal obtained from a VTR or the like is distributed over almost the entire band and is considered to be random noise.

Therefore, when a video signal with such noise is orthogonally transformed, the noise component will be distributed with approximately uniform amplitude in each orthogonal transform output, but the orthogonal transform output with a low order will be
In a high-order orthogonal transform output with a good S/N ratio, noise components become dominant, so the S/N ratio deteriorates. What can be said from these facts is that when the level of the orthogonal transform output is high, it can be regarded as a video signal component.

On the other hand, if the level of the orthogonal transform output is small, it may be regarded as a noise component. Moreover, as mentioned above, the S/N deteriorates in high frequency components, but since the human visual characteristics for this Takagi component generally deteriorate,
Even if the reproducibility in the high frequency region during reproduction is poor, it does not have much influence on the reproduced image. From the above, when the orthogonal transform output is at a low level that is approximately determined by the frequency spectrum of noise, it is sufficient to treat it as a noise component and remove it.

Next, the specific configuration of the inverse transform circuits 10A and 108 shown in FIG. 1 will be explained with reference to FIG.
Since 8B is a Hadamard transform circuit, we are looking for the same configuration for its inverse transform circuit, but the orthogonal transform circuit 8A,
In view of the fact that the output S″i of equation (9') is not obtained in 8B, only a part of the configuration of the synthesizer is different, so the parts in FIG. 9 that correspond to those in FIG. I will explain it by attaching it.

In FIG. 9, 69 to 71 are input terminals, 74 to 79 are synthesizers, of which 74, 76 and 78 are synthesis adders, and 75
, 77 and 79 are synthesis subtracters, and 80 to 83 are output terminals. Then, the input signals So2 to input terminals 69 to 71 are
By supplying So4, the output signal S'i. ~S'j4 are obtained at output terminals 80-83. Si, = So2 ten So3 ten So4 S'i2=So2-SQ-So4 S'i3 knee Smo one So3 ten So4
...tlOS'i4=-So20 So3-
So4 Next, the specific structure of the nonlinear circuits 9A and 9B shown in FIG. 1 will be explained with reference to FIGS. 10 to 12.

FIG. 10 shows the overall configuration of nonlinear circuits 9A and 9B,
The orthogonal transform circuits 8A and 8 of FIG. 8 are connected to the input terminals 86 to 88.
The output signals S''i2 to S''i4 from the converter circuits 8 and 8 are respectively supplied, and the output signals So2 to So4 to be supplied to the inverse conversion circuits 10A and 10B are obtained from the output terminals 93 to 95. In this case, between the input terminal 86 and the output terminal 93, the input terminal 8
7 and the output terminal 94, and between the input terminal 88 and the output terminal 95, as shown in FIG. 11 as nonlinear circuits, when considering analog signals, the output level is A stripping circuit (or a limiter circuit is also possible) in which the relationship between the input level and the output level is linear when it is zero (or a constant value that is not zero) and is less than a predetermined value.
89, 90, and 91 are provided. Since the stripping circuits 89 to 91 are digital circuits in this example, a configuration as shown in FIG. 12 is explored as an example. T, (SIG
N) is a sign bit input terminal, T, (MSB) to T, (
LSB) is the bit input terminal for the most significant digit to the least significant digit, L (SIGN) is the sign bit output terminal, and T2 (M
SB) to T2 (LSB) are bit output terminals for the most significant digit to the least significant digit. And the corresponding input/output terminal T, (S
IGN), T2 (SIGN), T, (MSB), T2
(MSB)...T, (LSB), L(
AND circuits As, A, . . . An are inserted between the LSB). A comparator circuit CMP is provided, in which a reference signal is input from an input terminal Tst and a reference signal is input from an input terminal T, (SI
GN), T, (MSB), ......T, (LSB
) are compared bit by bit, and the comparison output is sent to each of the AND circuits AS, A, . . .
...Supplied to An. Then, the input terminal T, (SIG
N), T, (MSB), ......T, (LS
When the level of the input signal made up of each bit signal supplied to B) is above a predetermined value, the AND circuits As, A, . . . An are all is closed, and when the level of the input signal is below a predetermined value, the AND circuits As, A, . . .
・・・・・・・・・All of An is opened. Another example of the nonlinear circuit 9A will be described with reference to FIG. 13, but parts corresponding to those in FIG. 10 will be given the same reference numerals and redundant explanation will be omitted. 98, 99 and 100 are gate circuits to which signals S''i2, S''i3 and S''i4 from input terminals 86, 87 and 88 are respectively supplied, and the outputs of the black level period of the vertical retrace period are extracted. It will be done.

97 is a black level period detection circuit for the vertical female line period which supplies gate signals to the gate circuits 98, 33 and 10;
A luminance signal from the separation circuit 5 of FIG. 1 is supplied to the input terminal 104.

The outputs of the gate circuits 98, 99, and 100 are connected to a detection circuit 101 that detects direct current fluctuations in the output power.
, 102 and 103. And input terminal 8
Signals S″i2, S″i3 and S from 6, 87 and 88
``i4 is supplied to the stripping circuits 89, 90, and 91, but the input level boundary value at which the input level/output level characteristic changes from linear to zero regardless of the input level is the input level boundary value of the detection circuits 101, 102, and 103. The boundary value of this input level is controlled by the output.The boundary value of this input level is made to vary depending on the noise level of the luminance signal, so that appropriate noise removal is performed.In the case of the nonlinear circuit 9B,
The boundary values of the stripping circuits 89, 90, and 91 are controlled by the detection outputs of the detection circuits 101, 102, and 103 of the nonlinear circuit 9A.

Next, orthogonal transform circuits 8A, 8B and inverse transform circuits 10A, 1
A more specific configuration of 0B and modifications thereof will be described.

In orthogonal transform circuits, high-order orthogonal transform outputs have less energy than low-order ones, and also have high-frequency components corresponding to the contours and details of the image, but low-order transform outputs have less energy than low-order ones. Therefore, higher-order conversion outputs do not require higher accuracy. Therefore, instead of making all of the orthogonal transform outputs have the same precision, we can use low-order transform outputs with high precision (with many bits) and high-order transform outputs with low precision (with low bits).
Even if it does, the deterioration in image quality will be slight.
In the orthogonal transform circuits 8A, 8B and inverse transform circuits 10A, 108 shown in FIGS. 8 and 9, each combiner is assumed to be fully equipped with eight combiners 72 to 79. 72 to 79, when all orthogonal transform outputs have the same precision, the number of bits of the synthesizers 72 to 75 is 9 bits,
The number of bits of the combiners 76 to 79 is 10 bits, but the number of bits of each combiner when obtaining a low-order conversion output with high accuracy and a high-order conversion output with low accuracy is as follows.

Synthesizer Orthogonal transformation circuit Inverse transformation circuit (72)
9 bits 11 bits (73)
8 〃 11″(74) 9
〃 9 ″05) 8 〃
9″ (76) 10 〃
12 〃(77) 8 〃 12
〃08) 8 〃 12 〃(79
) 8 12 Figures 14 and 15 respectively show configurations in which the synthesizers 72 to 79 have a sufficiently large number of bits, and in which the number of bits is limited and the amplitude is limited when the number of bits is exceeded. shows. In FIGS. 14 and 15, A is a synthesizer, T, . , T, 2 are two input terminals, tc is a clock pulse (sampling pulse) input terminal, F,, F2, F3, ...... are flip-flop circuits for waveform shaping, OR,, OR2, O
R3, ...... is an OR circuit, AND,,AN
D2, AND3, . . . are AND circuits, and t is an overflow terminal. In Fig. 14, the composite signal of each bit from the synthesizer A and the pulse from the input terminal tc are applied to each flip-flop circuit F, , F2, F3, . Supplied.

In Figure 15, each AND circuit AND,,AND2
AND3, . . . combined signal of each bit by synthesizer A and terminal t.

The overflow signal from v is supplied to each OR circuit OR,, OR2, OR3, ? Terminal t on... Overflow signal from v and each AND circuit AN
The outputs of D,, AND2, AND3, . . . are supplied respectively to each flip-flop circuit F,, F2, F3.
, ....... each OR circuit OR, , OR2, OR3
, . . . and pulses from the input terminal tc are supplied as set and reset signals, respectively. When orthogonal transform circuits 8A and 8B are configured to obtain low-order transform outputs with high precision and high-order transform outputs with low precision, respectively, orthogonal transform circuits 8A and 8B, inverse transform circuits 10A,
10 and the number of bits of the nonlinear circuits 9A and 9B can be reduced to simplify their configuration.

Next, another embodiment of the present invention will be described, but prior to that, the concept of this embodiment will be explained.

For example, as shown in Fig. 16, consider orthogonal transformation of fine patterns in the image signals SN, SN0, in adjacent horizontal scanning sections. Therefore, the serial/parallel converted signal is Si,
~Si8. If the time series of the input signal is used as it is and the unit area to be orthogonally transformed is expressed in blocks as shown in Figure 17, when a signal representing the contour F as shown by the dashed line in the figure arrives. We consider noise processing operations involving orthogonal transformations of . As is well known, the 8th order Hadamard transformation matrix 8 is expressed by the following equation.

For convenience of explanation, if it is assumed that the level of signals other than those representing the contour F is zero, at the time when the contour F appears only in a part of the area to be orthogonally transformed as shown in FIG. 17A, the input signals Si4 and Only Si8 has a predetermined level a.

That is, Sj,=Si2=Si3koSi5=Si6=Si
7=0 Si4=Si8=a...(1
2) Therefore, the orthogonal transformation outputs S″i, to S″i6 at the time point shown in A in the figure become the values shown by the following equation by using equation (11).

IS″i,l=IS″i4l=IS″j5l=IS″i
8l=lal...(13)S''
i2=S″i3=S″i6=S″i7=0 On the other hand, in the orthogonal transformation output, there are more Takagi components distributed in the higher-order transform output than in the lower-order ones, so Since the level of a high orthogonal transformation output tends to be smaller than that of a low-order one, among the orthogonal transformation outputs shown in equation (13), the higher-order outputs S″i3, S″i4, . . . The level of is not all the same value a, but a gradually decreasing value is sought.

In the state shown in FIG. 17A, the level of the high-order conversion output is still small and is within the linear region of the input level/output level characteristics of the stripping circuit whose characteristics are shown in FIG. Since it is regarded as a component and is output, and then subtracted from the input signal through an inverse conversion circuit and a parallel/series circuit, the signal of contour F will be subject to distortion, and the signals of parts other than contour F will also be distorted. widely dispersed;

As the state of FIG. 17A shifts to the state of FIG. 17B, the level of the high-order conversion output increases and falls outside the linear region of the stripping circuit, and is therefore output as a signal component from the stripping circuit. , the input signal is not distorted.

As the state of FIG. 17B shifts to the state of FIG. 17C, the level of the higher-order conversion output becomes smaller again, and as shown in FIG.
Similar to the situation described above, the signal of the contour F will be subjected to distortion, and the distortion will also be widely dispersed in the signals of the portions other than the contour F.
Since there are very few isolated point signals in the video signal, noise is extracted more faithfully in the center of the conversion block. Therefore, in this embodiment, the occurrence of such distortion is reduced, and the reproduced image is further improved.The output level of the inverse transformation output corresponding to a unit area that is easily susceptible to distortion is set to By attenuating the level of the output and then combining the signals, that is, by performing weighted averaging, the desired output signal from which noise has been removed is obtained.

A part of the embodiment is shown in FIG. 20, and parts corresponding to those in FIG. 1 are given the same reference numerals and will be explained.

Since the orthogonal transform circuit (not shown) uses an eighth-order Hadamard transform circuit, the inverse transform circuits 10A and 10B also have a similar configuration. An attenuation circuit 1 is provided between the inverse conversion circuits 10A, 10B and the parallel/serial conversion circuits 11A, 1IB.
06A, 1068 is inserted. Attenuation circuit 106A, 10
6B is composed of attenuators AT, to AT8, and their respective attenuation ratios are expressed as, in the case of FIG.
In the case of Figure 19, select the quantity, poison, reed, . . ., reed, reed, and reed, respectively. And parallel-
The outputs of the serial conversion circuits 11A and 11B are supplied to attenuation circuits 107A and 107B whose attenuation ratio is the reciprocal of the sum of the attenuation ratios of the above-mentioned attenuators AT and AT8, and the outputs are further supplied with an attenuation ratio that is indescribable. The signal is supplied to attenuation circuits 108A and 108B, and the output thereof is supplied to combiners 95A and 95B as a subtraction signal. When the orthogonal transformation is a Hadamard transformation, its inverse transformation is also represented by the same matrix as the orthogonal transformation.

Therefore, with reference to FIG. 21, an embodiment of a noise removal circuit in which an orthogonal transform circuit is also used as an inverse transform circuit and these circuits are used in a time-division manner will be described. 21 will be described with the same reference numerals assigned to parts corresponding to those in FIG. 1. The outputs of the serial/parallel conversion circuits 7A and 7B are sent to the time division multiplexing circuit 110A,
110B-Orthogonal transformation circuit (also serves as inverse transformation circuit) 8A,
The signal is supplied to a cascade circuit of 88 temporary division/separation circuits 111A and 1118. Orthogonal transformation outputs and inverse transformation outputs are obtained from the time division separation circuits 111A and 111B, and the orthogonal transformation outputs are passed through the time division multiplexing circuit 110A through a cascade circuit of nonlinear circuits (stripping circuits) 9A and 9B and delay circuits 112A and 112B. , 110B. On the other hand, a part of the outputs of the serial/parallel conversion circuits 7A and 7B are connected to the delay circuits 114A and 114A.
148 to the combiners 113A, 113B, from which the inverse conversion outputs from the time division separation circuits 111A, 111B are subtracted, and the
The output of 38 is supplied to parallel/serial conversion circuits 11A and 11B. The time division multiplexing circuits 1 10A and 1 10B are
This is a circuit that time-division multiplexes orthogonal transform output and its inverse transform output.

The orthogonal transform circuits 8A and 8B are Hadamard transform circuits that also serve as inverse transform circuits, and have a configuration as shown in FIG. 22 (the same reference numerals are given to the parts corresponding to FIGS. 8 and 9). , when operating as an orthogonal transform circuit, the output terminal 80
The output of the circuit is not used, and when operating as an inverse transform circuit, no input signal is supplied to the input terminal 68, and this circuit operates as the orthogonal transform circuit and inverse transform circuit of FIGS. 8 and 9 described above. It will be cum. Delay circuits 112A, 112B
is a circuit that realizes a timing shift between the outputs from the serial/parallel conversion circuits 7A, 78 and the outputs from the nonlinear circuits 9A, 9B, which are supplied to the time division multiplexing circuits 1 10A, 1 10B.

The combiners 113A and 113B are the combiners 95A and 9 in FIG.
This corresponds to 5B.

Delay circuits 114A and 1148 are time division multiplexing circuits 110
A, 110B and the time division separation circuits 111A, 111B have a delay amount corresponding to the signal delay amount between them. The sampled luminance signal and carrier color signal are then supplied to the serial/parallel conversion circuits 7A and 7B, respectively, and the parallel/serial conversion circuit 1
A luminance signal and a carrier color signal from which noise has been removed are obtained from signals 1A, 1 and 1B, respectively, and these signals are phase-aligned and output from the first signal.
It is connected to the synthesizer 13 in the figure and added.
The other configuration is the same as that in Figure 1. According to the noise removal circuit shown in FIG. 21, the circuit configuration is extremely simple.

According to the present invention described above, in a noise elimination circuit using an orthogonal transform circuit, it is possible to better separate signal components and noise components similarly to the noise eliminator type, and it is possible to improve the separation of signal components and noise components in subsequent signal processing. Even if the signal is distorted, the deterioration in image quality caused by it becomes less noticeable from the human visual characteristics, and when processing the video signal by converting it into a doji, it is easier to use than the noise eliminator type. Thus, a noise removal circuit with a simple circuit configuration can be obtained.

The above-described embodiment is a case in which the present invention is applied to a noise removal circuit for a color video signal, but it goes without saying that the present invention can also be applied to a noise removal circuit for a monochrome video signal.

In addition, in the above embodiment, the sampled luminance signal and carrier chrominance signal are obtained by separating a color video signal (analog signal) into a luminance signal (analog signal) and a carrier chrominance signal (analog signal). It may also be obtained by sampling.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG.
9 and 10 are block diagrams showing specific examples of a part of FIG. 1, FIG. 11 is a characteristic curve diagram, and FIG.
A block diagram showing a specific example of a part of the diagram, FIG. 13, 1
4 and 15 are block diagrams showing specific examples of parts of other embodiments of the present invention, FIG. 16 is a waveform diagram, FIGS. 17, 18, and 19 are explanatory diagrams, and FIG. 21 and 21 are block diagrams showing a part of still another embodiment of the present invention, and FIG. 22 is a block diagram showing a specific example of a part of FIG. 21. 5 is a separation circuit, 6A and 6B are luminance signal and carrier color signal noise removal circuits, 7A and 78 are first and second serial/parallel conversion circuits, 8A and 88 are first and second orthogonal conversion circuits, 9
A, 9B are the first and second nonlinear circuits, 10A, 10B
are the first and second inverse conversion circuits, 11A, 1 1B are the first
and a second parallel/serial conversion circuit, 95A, 95B are the first
and a second combiner. Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Sphere diagram N Ship chart sphere Fig. 9 Fig. 10 Fig. 11 Fig. 12 Fig. 13 Fig. 14 Fig. 15 Fig. 16 Fig. 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22

Claims (1)

[Claims] 1 Defining a predetermined pixel area for the digital video signal,
A serial/parallel conversion circuit to which pixel signals in the area are supplied, an orthogonal conversion circuit to which parallelized pixel signals from the serial/parallel conversion circuit are supplied, and an output of at least the order of the orthogonal conversion circuit. A nonlinear circuit to which a high orthogonal transformation output is supplied and an orthogonal transformation output below a predetermined level is extracted, an inverse transformation circuit to which the orthogonal transformation output extracted from the nonlinear circuit is supplied, and an output of the inverse transformation circuit is supplied. The parallel/serial conversion circuit converts the digital video signal into the parallel/serial converter.
A noise removal circuit characterized in that noise is removed from the digital video signal by subtracting the output of the serial conversion circuit.