JPS624910B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a noise removal circuit that can remove noise in a video signal. Conventionally, there are noise removal circuits as described below for removing noise from a video signal including noise obtained from a magnetic recording/reproducing device or the like.
That is, the noise removal circuit supplies the video signal to a low-pass waveform and a high-pass waveform, respectively, and changes the output level of the high-pass waveform when the absolute value of the input level is below a predetermined value. When it is zero or above a predetermined value, it is supplied to a coring circuit (a type of nonlinear circuit) in which the relationship between the input level and output level is linear, and the output of the low-pass waveformer and the output of the coring circuit are sent to a combiner. By supplying and adding the signals, a video signal from which noise, particularly high-frequency noise, has been removed can be obtained. However, with this conventional noise removal circuit, in addition to insufficient separation of the signal component and noise component in the video signal, the signal component of the output of the high-pass waveform is subject to large distortion in the coring circuit. Fine brightness changes in parts of the reproduced image where the brightness changes are small, such as the background, disappear, and as a result, a scaly pattern is generated in the image corresponding to the parts where the brightness changes are gradual. Moreover, on the contrary, smear occurs in an image corresponding to a portion where the brightness change is steep, and the sharpness of the image deteriorates. In order to remove noise from a video signal without suffering much image degradation, the signal component and noise component should be better separated, and then signal processing for noise removal should be performed. In this case, even if the signal is distorted, the resulting deterioration in image quality should be made so that it is not so noticeable from the human visual characteristics. As a noise removal circuit that satisfies these conditions, the applicant has proposed a noise removal circuit using an orthogonal transform circuit as shown below. This noise removal circuit consists of a serial/parallel conversion circuit to which an input video signal is supplied, an orthogonal conversion circuit to which the output of this serial/parallel conversion circuit is supplied, and a nonlinear circuit to which the output of this orthogonal conversion circuit is supplied. , has an inverse conversion circuit to which the output of this nonlinear circuit is supplied, and a parallel/serial conversion circuit to which the output of this inverse conversion circuit is supplied, and converts the output of the parallel/serial conversion circuit or this output from the input video signal. The subtracted output is used as an output video signal from which noise has been removed. Here, orthogonal transformation and inverse transformation will be explained. Now, if we represent a block of a video signal sequence as an input signal, a block of an output signal sequence as well, an orthogonal transformation matrix as A, and an inverse transformation matrix as B, we get B=A ^T ………(2) (However, A ^T is the transposed matrix) Therefore, when the input signal is orthogonally transformed, Therefore, the inverse transformation output is Therefore, the transform coefficient, ie, the orthogonal transform output Y, is a linear combination of the row vector and the input signal. By the way, orthogonal transforms such as Warschu, Hadamard, and Haar can be used as this orthogonal transform, but they have the characteristics of being able to extract the characteristics of the video signal well and that the inverse transform can be performed in the same procedure as the transform. A Hadamard transform with . A specific example of such a noise removal circuit will be described below with reference to the drawings. First, the overall configuration of FIG. 1 will be explained. This is the case of a noise eliminator type noise removal circuit. In FIG. 1, reference numeral 1 denotes an input terminal to which a video signal containing noise (in this case, a black-and-white signal that has been A-D converted) is supplied. This noise removal circuit is composed of a cascade circuit 7 consisting of a serial/parallel conversion circuit 2, an orthogonal conversion circuit 3, a nonlinear circuit 4, an inverse conversion circuit 5, and a parallel/serial conversion circuit 6. By supplying the video signal from the input terminal 1 to the cascade circuit 7, a video signal from which noise has been removed is obtained from the output terminal 8. Next, the circuits of each part of the noise removal circuit shown in FIG. 1 will be explained with reference to FIG. 2 and subsequent figures. First, the specific configuration of the serial/parallel conversion circuit 2 will be explained with reference to FIG. The input signal Si from the input terminal 10 is delayed through delay circuits 11-12 with a delay amount of one horizontal period and one sampling period (this sampling period is the sampling period of the A-D converted video signal), respectively. output signal S i4 is obtained at the output terminal 14, and the output signal S _i4 is output from the delay circuit 11 to the output terminal 15.
The output signal S _i3 is obtained from the input terminal 10, and the input signal Si from the input terminal 10 is sent to the delay circuit 1 whose delay amount is one sampling period.
3 and the output signal to the output terminal 16.
Si ₂ is obtained, and the input signal Si is directly supplied to the output terminal 17 to obtain the output signal Si ₁ . Next, as the serial/parallel converter circuit 2 in Fig.
Parallel/parallel when using the diagram explained
The serial conversion circuit 6 will be explained with reference to FIG. The input signal S′i ₁ from the input terminal 19 is supplied to the synthesizer 24, and the input signal S′i ₂ from the input terminal 20 is supplied to the synthesizer 24.
is delayed through a delay circuit 23 with a delay amount of one sampling period and supplied to a synthesizer 24, and the summed output of both signals from the synthesizer 24 is supplied to a synthesizer 28. The input signal S′i ₃ from the input terminal 21 is supplied to the synthesizer 26, and the input signal from the input terminal 22 is
Delay circuit 2 whose delay amount is 1 sampling period for S′i ₄
5 and then supplied to the synthesizer 26. The combined output of both signals from the combiner 26 is supplied to the combiner 28 through a delay circuit 27 whose delay amount is one horizontal period. Then, the summed output of both signals from the combiner 28 is obtained at an output terminal 29 as an output signal S'i. Next, the orthogonal transform circuit 3 and inverse transform circuit 5 in FIG.
The specific configuration will be explained with reference to FIG.
In this case, since the orthogonal transform circuit 3 uses a Hadamard transform circuit, the inverse transform circuit 5 also has the same configuration.
In this example, fourth-order Hadamard transform circuits are used as the transform circuits 3 and 5. The fourth-order Hadamard transformation matrix _H4 is as shown in the following equation. Note that the 2nd to 4th rows of the matrix in equation (8) can be interchanged. In Fig. 4, 38-41 are input terminals, 42-41 are input terminals, and 42-41 are input terminals.
49 is a synthesizer, of which 42, 44, 46, 49
is an addition combiner; 43, 45, 47, and 48 are subtractive combiners; and 50 to 53 are output terminals. In the orthogonal transformation circuit 3, when the input signals Si 1 to Si 4 are supplied to the input terminals 38 to 41, output signals S _″ i ₁ to S″ _{i 4 that} satisfy the following equation are output from the output terminals 50 to 41. 53. As shown in FIG. 5A, a pixel point a ₁ at a certain time point on an adjacent scanning line of a certain field, a pixel point a at a time point one sampling period, one horizontal period, one horizontal period + one sampling period before, respectively. ₂ , a ₃
and a ₄ . If the input signals Si ₁ to Si ₄ are signals of pixel points a ₁ to _{a 4} , respectively, then those portions of the screen will have a planar pattern as shown in FIG. 5B, and a planar pattern as shown in FIG. 5C, respectively. For a horizontal pattern, a diagonal pattern as shown in FIG. 5D, and a vertical pattern as shown in FIG. 5E, the levels of the output signals S″i ₁ to S″i ₄ are adjusted accordingly The absolute value of becomes large. In the inverse conversion circuit 5, by supplying the input signals So _{1 to} So 4 to the input terminals 38 to 41, output signals S'i ₁ to _{S'i 4 satisfying} the following equation are output to the output terminal 50. ~
Obtained at 53. Next, the nonlinear circuit 4 shown in FIG. 1 will be explained with reference to FIG. 6. FIG. 6 shows the overall configuration of the nonlinear circuit 4, in which the output signals S″i ₁ to S″i ₄ from the orthogonal transform circuit 3 in FIG. 4 are supplied to input terminals 55 to 58, respectively, and the output terminal 62 65 to obtain output signals So ₁ to _{So 4} to be supplied to the inverse conversion circuit 5.
In this case, except between the input terminal 55 and the output terminal 62, the nonlinear circuits shown in FIG. When considered as an analog signal that shows the characteristics,
A coring circuit 5 in which the output level is zero when the absolute value of the input level is below a predetermined value, and the relationship between the input level and the output level is linear when it exceeds the predetermined value.
9, 60, and 61 are provided. Next, another example of this type of noise removal circuit will be explained with reference to FIG. 8. This is a noise canceller type noise removal circuit, and parts corresponding to those in FIG. , and redundant explanations will be omitted.
The cascade circuit 7 has approximately the same configuration as that shown in FIG. Circuits 59, 60, 6 in
In the circuit corresponding to 1, when considering an analog signal whose characteristics are shown in Figure 9, the relationship between the input level and output level is linear when the absolute value of the input level is less than a predetermined value, and when it exceeds a predetermined value. This is a stripping circuit with zero output level. Then, a delay circuit 70 for compensating the amount of delay outputs the video signal from the input terminal 1.
The noise signal from the cascade circuit 7 is subtracted from this signal, and the signal is supplied to the synthesizer 71 through the output terminal 8.
The aim is to obtain a video signal with noise removed. By the way, in the above-mentioned noise removal circuit, in the case of a video signal with a fine striped pattern (for example, hair, etc.) with little change in brightness or degree, Equation (9) is used.
Of the output signals S″i ₁ to S″i ₄ , the output signals S″i ₂ to S″i ₃
Since the absolute value of the level becomes significantly small, these output signals S″i ₂ to S″i ₄ are removed from the input video signal, and the playback screen of the output video signal becomes a flat pattern. Put it away. In view of this, the present invention provides a serial/parallel conversion circuit to which an input video signal is supplied, an orthogonal conversion circuit to which the output of this serial/parallel conversion circuit is supplied, and a nonlinear conversion circuit to which the output of this orthogonal conversion circuit is supplied. circuit and
It has an inverse conversion circuit to which the output of this nonlinear circuit is supplied, and a parallel/serial conversion circuit to which the output of this inverse conversion circuit is supplied, and subtracts the output of the parallel/serial conversion circuit or this output from the input video signal. The present invention aims to propose a noise removal circuit that can effectively remove noise with less reduction in the resolution of fine striped patterns in a noise removal circuit that converts the output from noise into an output video signal from which noise has been removed. It is something. The first noise removal circuit of the present invention includes an orthogonal transformation circuit to which an input video signal is supplied, a plurality of nonlinear circuits to which the output of this orthogonal transformation circuit is supplied, and an output of the plurality of nonlinear circuits to which the output of the plurality of nonlinear circuits is supplied. The output of the inverse conversion circuit or the output obtained by subtracting the output from the input video signal is used as an output video signal from which noise has been removed, and Among the multiple output signals of the orthogonal transform circuit supplied to the nonlinear circuit, output signals whose absolute values are below a predetermined level are removed from the input video signal, and the absolute values of all the multiple output signals are removed from the input video signal. When the value is below a predetermined value, at least the output signal with the highest absolute value of the level among the plurality of output signals is not removed from the input video signal. The second noise removal circuit of the present invention includes an orthogonal transformation circuit to which an input video signal is supplied, a plurality of nonlinear circuits to which the output of the orthogonal transformation circuit is supplied, and an output of the plurality of nonlinear circuits to which the input video signal is supplied. The output of the inverse conversion circuit or the output obtained by subtracting this output from the input video signal is used as the output video signal from which noise has been removed, and the output of the inverse conversion circuit is Among the plurality of output signals of the orthogonal transformation circuit supplied to the circuit, the output signal whose absolute value is less than or equal to the first predetermined value is removed from the input video signal, and the levels of all the plurality of output signals are removed. When the absolute value of the output signal is less than or equal to the first predetermined value and greater than or equal to the second predetermined value, at least the output signal of which the absolute value of the level is the largest among the plurality of output signals is not removed from the input video signal. be. Embodiments of the present invention will be described below with reference to FIG. 10 and subsequent figures. In these figures, parts corresponding to those in FIGS. Part of is omitted. Furthermore, Figures 10 and 12
The figure is a diagram showing an embodiment of the first invention.
The figure shows an embodiment of the second invention. First, the embodiment shown in FIG. 10 will be described. 1st
Figure 0 shows a noise eliminator type noise removal circuit. Circuits 2, 3, 5 and 6 are shown in FIGS. 2 and 4 above.
The configuration is similar to that shown in FIGS. Here, the configurations of the nonlinear circuit 4 and the control circuit 102 will be explained. The nonlinear circuit 4 is a nonlinear circuit 59,
60 and 61, each of which is a coring circuit whose characteristics are shown in FIG. In addition, nonlinear circuit 4
Delay circuits 83 to 85, 83' to 85', and 89 to 92 are provided for aligning the signal timings, and delay circuits 83 to 85, 83' to 85', and 89 to 92 are provided to align the signal timing. When the sampling period of the video signal) is T, the delay circuits 83 to 8
5, delay amount of 83' to 85' is 2T, delay circuit 89
The delay amount of is 3T, and the delay amount of delay circuits 90 to 92 is T. The signal S″i ₁ from the orthogonal transformation circuit 3 is directly supplied to the delay circuit 89. The signal from the orthogonal transformation circuit 3
S″i ₂ , S″i ₃ and S″i ₄ or delay circuits 83 and 8 respectively
4 and 85 and gate circuits 86, 87 and 88
are supplied to delay circuits 90, 91 and 92, respectively. And each signal from delay circuits 89 to 92
So ₁ to _{So 4} are supplied to the inverse conversion circuit 5. further signal
S″i ₂ , S″i ₃ and S″i ₄ are supplied to discrimination circuits 80, 81 and 82, respectively.These discrimination circuits 80, 81 and 82 have input/output characteristics as shown in FIG. The output level is 0 when the absolute value of the input level is less than a predetermined value |E ₀ |, and 1 when it exceeds the predetermined value |E ₀ |.The outputs of the discriminator circuits 80, 81, and 82 are sent to delay circuits, respectively. They are supplied as gate signals to gate circuits 86, 87, and 88 through 83', 84', and 85', and the absolute values of the levels of signals S″i ₂ , S″i ₃ , and S″i ₄ are below |E ₀ | When |E 0 | is exceeded, the gate circuits 86, 87, and 88 are closed, and when it exceeds |E ₀ |, they are opened to allow the signals S″i ₂ , S″i ₃ , and S″i ₄ to pass. , etc. gate circuits 86, 87, and 88 are further controlled by a control circuit 102.Next, the configuration of this control circuit 102 will be explained.93-
95, 98, and 100 are delay circuits to align the timing of the signals, and the amount of delay of the delay circuit 93 is
2T, and the delay amount of delay circuits 94, 95, 98 and 100 is T. The signals S″i ₂ , S″i ₃ and S″i ₄ are sent to the delay circuit 93,
94 and 95. Delay circuits 94 and 9
The signals S″i ₃ and S″i ₄ from 5 are supplied to a comparison circuit 96 to compare the absolute values of their levels, and are also supplied to a switching circuit 97. Comparison circuit 96 outputs signal S″i ₃
When the absolute value of the level of is greater than the absolute value of the level of the signal S″i ₄ , an output 1 is obtained, otherwise an output 0 is obtained, and when an output 1 is obtained, the signal S″i ₃ The switching circuit 97 is controlled to output a signal S″i ₄ when an output of 0 is obtained.Furthermore, the output of the switching circuit 97 obtained from the delay circuit 98 and the signal obtained from the delay circuit 93 are controlled. The received signal S″i ₂ is supplied to a comparison circuit 99 and compared. Comparison circuit 99
When the absolute value of the level of the signal S″i ₂ is greater than the absolute value of the level of the output signal of the switching circuit 97, the output 1 is
It is designed so that an output of 0 is obtained when it is not used. The outputs of the discrimination circuits 80, 81 and 82 obtained through the delay circuits 83', 84' and 85'
L ₁ , L ₂ and L ₃ and the output L ₄ of the comparison circuit 99 and the comparison circuit 96 obtained through the delay circuit 100
The output L ₅ is supplied to the logic operation circuit 101, and the outputs K ₁ , K ₂ and K ₃ obtained therefrom are supplied as control signals to the gate circuits 86, 87 and 88.
The truth table of this logic operation circuit 101 is shown below as Table 1. However, in Table 1, "-" means that it may be 0 or 1.

【table】

[Table] In this case, when the signals K ₁ , K ₂ and K ₃ are 1, the gate circuits 86, 87 and 88 are opened. Thus, in this noise removal circuit of Fig. 10,
Among the output signals S″i ₂ , S″i ₃ and S″i ₄ of the orthogonal transformation circuit 3 supplied to the nonlinear circuits 59, 60 and 61, the absolute value of the level is less than or equal to the predetermined value |E ₀ | are not supplied to the inverse conversion circuit 5, and the signals S″i ₂ ,
When the absolute values of all levels of S″i ₃ and S″i ₄ are less than the above predetermined value |E ₀ |, the signals S″i ₂ , S″i ₃ and S″i ₄
Among them, the signal with the highest absolute value of its level is supplied to the inverse conversion circuit 5. Next, an embodiment in which the noise canceling circuit shown in FIG. 10 is configured as a noise canceller type will be explained with reference to FIG. 12. In FIG. 12, parts corresponding to those in FIG. to omit redundant explanation. The nonlinear circuits 59, 60, and 61 are stripping circuits whose characteristics are shown in FIG.
Therefore, if the input/output characteristics of the discrimination circuits 80, 81 and 82 are as shown in FIG.
When the absolute values of the levels of S″i ₂ , S″i ₃ and S″i ₄ are below |E ₀ |, gate circuits 86, 87 and 88 are opened and the signals S″i ₂ , S″i ₃ and S″i ₄ is made to pass, and when it exceeds |E ₀ |, it is made to be closed. The truth table of logic operation circuit 101 is the same as Table 1, but in this case, when signals K ₁ , K ₂ and K ₃ are 1, gate circuits 86, 87 and 88 are closed. Thus, in the noise removal circuit of FIG. 12, the absolute value of the level of the output signals S″i ₂ , S″i ₃ and S″i ₄ of the orthogonal transform circuit 3 supplied to the nonlinear circuits 59, 60 and 61 is The output signal below the predetermined value |E ₀ | is supplied to the inverse conversion circuit 5, and the absolute values of all levels of the signals S″i ₂ , S″i ₃ and S″i ₄ are equal to the predetermined value |
When E ₀ | or less, among the signals S″i ₂ , S″i ₄ and S″i ₄ , the signal with the highest absolute value of its level will not be supplied to the inverse conversion circuit 5. Thus, FIG. And in the noise removal circuit of FIG. 12, nonlinear circuits 59, 60, and 6
The output signal S″i ₂ of the orthogonal transformation circuit 3 supplied to the
Output signals of S″i ₃ and S″i ₄ whose absolute value is less than a predetermined value |E ₀ | are removed from the input video signal and output signals S″i ₂ , S″i ₃ and S″ When the absolute values of all levels of i ₄ are less than the predetermined value |E ₀ |, the signal with the maximum absolute value of the level among signals S″i ₂ , S″i ₃ , and S″i ₄ is input. It will not be removed from the video signal. Next, the embodiment shown in FIG. 13 will be explained. This is a noise eliminator type noise removal circuit, and in FIG. 13, the parts corresponding to those in FIG. Some explanations will be omitted. Here, the nonlinear circuit 4 and the control circuit 102 will be explained. Each nonlinear circuit 5 of the nonlinear circuit 4
Reference numerals 9, 60, and 61 are coring circuits whose characteristics are shown in FIG. The value is the first predetermined value | E ₁
|When the output level is below, the output level is 0, the first predetermined value|
It becomes 1 when it exceeds E ₁ |. and the signal S″i ₂ ,
The absolute values of the levels of S″i ₃ and S″i ₄ are the first absolute values |
E ₁ | Gate circuits 86, 87 and 8 in the following cases
8 is closed, and is opened when exceeding |E ₁ |, allowing the signals S″i ₂ , S″i ₃ and S″i ₄ to pass. Next, the control circuit 102 will be explained. 94 ，
95, 98, 100, 105, 106, 110,
111 and 112 are delay circuits for aligning the timing of signals, and the amount of delay is T for both. Signals S″i ₂ , S″i ₃ and S″i ₄ are each sent to the delay circuit 10
5, 94 and 95. The signals S″i ₃ and S″i ₄ from the delay circuits 94 and 95 are supplied to a comparison circuit 96, and the absolute values of the levels are compared.
The signal is supplied to the switching circuit 97. Comparison circuit 96 is a signal
When the absolute value of the level of S″i ₃ is greater than the absolute value of the level of signal S″i ₄ , the output is 1, otherwise the output is 0
When output 1 is obtained, signal S″i ₃ is obtained, and when output 0 is obtained, signal S″i ₄ is obtained.
The switching circuit 97 is controlled to output .
Furthermore, the output of the switching circuit 97 obtained from the delay circuit 98 and the signal S″i ₂ obtained through the delay circuits 105 and 106 are supplied to a comparison circuit 99 and compared. When the _absolute value of the level of the switching circuit 97 is larger than the absolute value of the level of the output signal of the switching circuit 97, an output 1 is obtained, and an output 0 is obtained when this is not the case. Signals S″i ₂ , S″i ₃ and S″i ₄ from the delay circuits 105, 94 and 95 are sent to the discrimination circuit 1
07, 108 and 109. These discrimination circuits 107 _, 108, and 109 have input/output characteristics as shown in _FIG . When the output level exceeds the second predetermined value |E ₂ |, the output level becomes 0. The outputs of discrimination circuits 107, 108 and 109 are supplied to delay circuits 110, 111 and 112, respectively. The outputs of the discrimination circuits 80, 81 and 82 obtained through the delay circuits 83', 84' and 85'
L ₁ , L ₂ and L ₃ and the output L ₄ of the comparison circuit 99 and the comparison circuit 96 obtained through the delay circuit 100
output L ₅ , delay circuits 110, 111 and 112
The outputs L ₆ , L ₇ and L ₈ are supplied to the logic operation circuit 101, and the outputs K ₁ , K ₂ and K ₃ obtained therefrom are supplied as control signals to the gate circuits 86, 87 and 88. The truth table of this logic operation circuit 101 is shown below as Table 2. However, in Table 2, "-" means that it may be 0 or 1.

【table】

[Table] In this case, when the signals K ₁ , K ₂ and K ₃ are 1, the gate circuits 86, 87 and 88 are opened. Thus _, in _the noise removal circuit shown in FIG _. The output signals below the first predetermined value |E ₁ | are not supplied to the inverse conversion circuit 5 and are removed from the input video signal, and the signals S″i ₂ , S″i ₃ and S″i ₄
The absolute values of all levels of are the first predetermined values |
When _the second predetermined value is equal to _or less than _{E 1} |E ₂ The noise canceling circuit shown in FIG. 13 can also be of a noise canceller type. According to the first and second inventions described above, A serial/parallel conversion circuit to which the video signal is supplied, an orthogonal conversion circuit to which the output of this serial/parallel conversion circuit is supplied, a nonlinear circuit to which the output of this orthogonal conversion circuit is supplied, and an output of this nonlinear circuit It has an inverse conversion circuit that is supplied and a parallel/serial conversion circuit that is supplied with the output of this inverse conversion circuit, and the output of the parallel/serial conversion circuit or the output obtained by subtracting this output from the input video signal is used to remove noise. In the noise removal circuit that outputs a video signal with a 3D image, it is possible to obtain a noise removal circuit that can effectively remove noise with little reduction in the resolution of fine striped patterns.Second invention of the present invention According to the present invention, it is possible to more effectively remove noise in a video signal of a flat screen with very little change in luminance or chromaticity than in the first aspect of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a noise removal circuit previously proposed by the applicant; FIGS. 2, 3, and 4 are block diagrams showing each part of FIG. 1;
The figure is an explanatory diagram, FIG. 6 is a block diagram showing a part of FIG. 1, FIG. 7 is a characteristic curve diagram, and FIG. 8 is another example of the noise removal circuit previously proposed by the applicant. FIG. 9 is a block diagram, FIG. 9 is a characteristic curve diagram, FIG. 10 is a block diagram showing one embodiment of the present invention, FIG. 11 is a characteristic curve diagram, and FIGS. 12 and 13 are other embodiments of the present invention. A block diagram showing an example, and FIG. 14 is a characteristic curve diagram. 1 is an input terminal, 2 is a serial/parallel conversion circuit, 3 is an orthogonal conversion circuit, 4 is a nonlinear circuit, 5 is an inverse conversion circuit, 6 is a parallel/serial conversion circuit, 59, 60, and 6
1 is a nonlinear circuit, and 102 is a control circuit.

Claims (1)

[Claims] 1. An orthogonal transformation circuit to which an input video signal is supplied;
A plurality of nonlinear circuits to which the outputs of the orthogonal transformation circuits are supplied, an inverse transformation circuit to which the outputs of the plurality of nonlinear circuits are supplied, and a control circuit that controls the plurality of nonlinear circuits, the inverse transformation The output of the circuit or the output obtained by subtracting the output from the input video signal is used as the noise-removed output video signal, and the absolute level of the output signal of the orthogonal transform circuit that is supplied to the plurality of nonlinear circuits is Output signals whose values are below a predetermined value are removed from the input video signal, and when the absolute values of all the levels of the plurality of output signals are below the predetermined value, at least that level of the plurality of output signals is removed. A noise removal circuit characterized in that an output signal having a maximum absolute value of is not removed from the input video signal. 2 an orthogonal transformation circuit to which an input video signal is supplied;
A plurality of nonlinear circuits to which the outputs of the orthogonal transformation circuits are supplied, an inverse transformation circuit to which the outputs of the plurality of nonlinear circuits are supplied, and a control circuit that controls the plurality of nonlinear circuits, the inverse transformation The output of the circuit or the output obtained by subtracting the output from the input video signal is used as the noise-removed output video signal, and among the plurality of output signals of the orthogonal transformation circuit that are supplied to the plurality of nonlinear circuits, Output signals whose absolute values are equal to or less than the first predetermined value are removed from the input video signal, and absolute values of all the levels of the plurality of output signals are equal to or less than the first predetermined value and are removed from the second predetermined value. In the above case, at least the output signal having the maximum absolute value of the level among the plurality of output signals is not removed from the input video signal.