JPS602778B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a semiconductor integrated circuit device (hereinafter referred to as IC) having an MNOS structure.

RO of metal film gate CMOSIC with conventional MNOS structure
The M (private memory) section will be explained with reference to FIGS. 1 and 2. 1 and 2, 1 is an N-type semiconductor substrate, , is a P-well diffusion layer, 3 is a field oxide film, 4 is a gate region, 5 is a gate oxide film, 6 is an N+ type source diffusion region, 7 1 is an N0-type drain diffusion region, 8 is a P+-type channel stopper region, 9 is a source diffusion layer contact hole, 10 is a drain diffusion layer contact hole, 11 is a nitride film to prevent ion contamination, and 12 is an aluminum film, etc. This is an electrode wiring made of a metal film. The source and drain diffusion regions 6 and 7 extending linearly in the x (left and right) direction in FIG. A ROM is configured by forming the gate region 4. Writing to the ROM is performed using a mask writing method in which data is written using a mask during gate-type phosphorography, and an ion implantation method in which unnecessary impurities in the gate portion are high-concentrated by ion implantation after all gate bits are formed. There are methods etc. 0 Also, as ICs become larger, ROM capacity also increases.
The area of the ROM section becomes larger.

In an IC with an MNOS structure, when the ROM area increases, the gate threshold voltage VT increases between the ROM peripheral area and the central area.
and the value of mutual conductance gm becomes different. That evening, V. The gm value in the ROM peripheral area matches the value in the area other than the ROM, but the distance from the ROM peripheral area is 600 mm.
The VT value and m value in the central region exceeding ~800 are generally smaller than those in the peripheral region. The reason for this is that the interface between the gate oxide film of the MOS transistor and the semiconductor region is damaged by an electron beam or sputtering during deposition of a wiring metal film, resulting in a change in characteristics. The damage is removed by heat treatment in an atmosphere containing hydrogen in a subsequent process. That is, due to the heat treatment, hydrogen ions enter through the contact hole where there is no nitride film, although hydrogen ions do not easily pass through the nitride film due to its nature, and the characteristics are restored and the VT around the contact,
It is thought that gm is stabilized. Therefore, in the ROM part of FIGS. 1 and 2 with the above-described configuration, if the area where there is no hole such as a contact hole in the nitrided pus is large, there will be a portion that cannot be annealed with hydrogen ions. However, for this reason, the VT and gm values at the center of the ROM are different from those at the periphery, resulting in a disadvantage that the power supply voltage fluctuation margin of the IC is reduced. In the present invention, at least part of the nitride film in the area is removed by providing a dummy contact unrelated to electrical terminal extraction in an area where there is no hole such as a contact hole in the nitride film and making the hole. It is an object of the present invention to provide a semiconductor integrated circuit device that can eliminate the above-mentioned drawbacks of the conventional device.

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 3 and 4 show an MNOS according to the first embodiment of the present invention.
The ROM part of the metal film gate CMOSIC structure is shown. 3 and 4, 21 is an N-type semiconductor substrate, 22 is a P-well diffusion layer formed on the surface of the N-type semiconductor substrate 21, 23 is a field oxide film covering the surface of this diffusion layer 22, and 24 is a P-well diffusion layer formed on the surface of the N-type semiconductor substrate 21. 25 is a gate region, 25 is an N+ type source diffusion region,
26 is an N+ type drain diffusion region, and the source and drain diffusion regions 25 and 26 extend linearly in the X (left and right) direction in FIG. 27 is a P+ type channel stopper diffusion region provided between source and drain diffusion regions 25 and 26; 28 is a source diffusion contact hole; 29 is a drain diffusion contact hole; The contact holes 28 and 29 are filled with nitride film 3.
0 to the bottom surface of the field oxide film 23.

Reference numeral 31 denotes an electrode wiring made of a metal film such as an aluminum film, and most of it extends in a line shape in the Y (vertical) direction in FIG.

The ROM section configured as described above is shown in Figures 1 and 2.
Although it is similar to that shown in the figures, the gate oxide film is not shown in FIGS. 3 and 4. Reference numeral 32 denotes a contact of a diffusion layer distributed around the ROM section, and is connected to the source diffusion layer contact hole 28, the drain diffusion layer contact hole 29 portion of the electrode wiring 31, and the gate electrode line.

In this first embodiment, a nitrided pus 3 hole is formed in the central region of the ROM by forming a dummy contact 33 which has nothing to do with electrical terminal extraction.

Furthermore, after forming the ROM part as described above, heat treatment was performed in an atmosphere containing hydrogen. In the IC of the first embodiment configured as described above, since the contact 32 of the diffusion layer is provided around the ROM section, the RO
The characteristics are stable from the periphery of M to the MOS transistors located about 600 to 800 mounds inside.

In addition, if one side of the conventional ROM part is 1200 μm or more, even if hydrogen ions from the periphery of the ROM are annealed, regions of MOS transistors with different VT and m are created. In the first embodiment, one dummy contact 33 is provided in the central region of the ROM.
Hydrogen enters from this portion through the heat treatment, and the characteristics of the entire ROM area can be made uniform in an IC incorporating a ROM with a side size of 1,200 to 2,400 A. Further, the dummy contact 33 can be connected to the ground terminal by the metal wiring 31 in order to make the ground potential of the P-well diffusion layer more uniform. The dummy contact only slightly increases the area of the ROM, and does not require any additional steps during IC manufacturing.
It's easy to do. In the case of an IC having a ROM of 2400 μm or more on a side, a plurality of dummy contacts may be provided at a ratio of 1×1200 μm. As explained above,
In the first embodiment of the present invention, when the area covered with a nitride film is large, such as the ROM part of an IC, dummy contacts are inserted at appropriate intervals such as 1200 mm to make holes in the nitride. Since a portion free of nitrided pus is provided, hydrogen ions enter from the contact hole of the dummy contact during hydrogen annealing, making it possible to stabilize V, gm of the MOS transistor around the contact hole.

The larger the number of dummy contacts, the more uniform the VT and gm values for the entire ROM will be, but the degree of integration will be lower, so insert them at a pitch that is slightly less than twice the length at which the hydrogen annealing effect from the contact hole is no longer effective. It is optimal to do so, and the VT and gm values can be made uniform over a large capacity ROM, and the stability and reliability of operation can be improved. FIGS. 5 and 6 show R according to the second embodiment of the present invention.
The OM part is shown.

In this embodiment, instead of providing a dummy contact, the RO
The part other than the M central region 41 is covered with photoresist or the like, and using the wiring metal as a mask, only the nitrided pus 30 in the area between the metal wirings 31 is removed, and a hole 42 reaching the field oxide film 23 is made therein. It is. In addition, the second
The configuration of the embodiment other than those described above is almost the same as that of the first embodiment, so the parts corresponding to FIGS. 3 and 4 in FIGS. The same reference numerals as those in the figure are used to omit the explanation. The IC of the second embodiment can provide the same effects as those of the first embodiment described above without reducing the degree of integration. Note that in the present invention, the entire nitride film in the central region of the ROM may be removed.

As mentioned above, the MNOS structure IC according to the present invention has a large capacity because at least part of the nitride film is removed in areas where there are no holes such as contact holes in the nitride film. It has the effect of improving operational stability and reliability, and is particularly effective when used in ICs used in microcomputers, watches, timing devices, and the like.

[Brief explanation of the drawing]

Figure 1 shows a conventional metal film gate CMOS with MNOS structure.
FIG. 2 is a plan view showing the ROM section of the IC, FIG. 2 is a sectional view of the Rolo wire section in FIG. 1, and FIG.
4 is a sectional view taken along the line WW in FIG. 3, FIG. 5 is a plan view showing the ROM portion of an IC according to another embodiment of the present invention, and FIG. 6 is a sectional view taken along the line W- in FIG. 5. FIG. 1, 21... N-type semiconductor substrate, 2, 22... P-well diffusion layer, 3, 23... Field oxide film, 4, 2
4... Gate region, 5... Gate oxide film, 6, 25
. . . N+ type source diffusion region, 7, 26 . . . N + type drain diffusion region, 8, 27 . ...Drain diffusion layer contact hole, 11, 30... Chamber suppuration, 12, 31... Electrode wiring, 32... Diffusion layer contact, 33... Dummy contact, 41... ROM central region, 42...hole. Figure 2 Figure 1 Figure 8 Figure 4 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having an MNOS structure, characterized in that at least part of the nitride film in a region where there is no part for forming a contact hole or the like in the nitride film has been removed. Device. 2. The semiconductor integrated circuit device according to claim 1, wherein a portion of the nitride film is removed by providing a dummy contact unrelated to electrical terminal extraction and making a hole. 3. The semiconductor integrated circuit device according to claim 1, wherein the nitride film is removed using the wiring metal as a mask.