JPS6027990B2 - keyboard instrument practice device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a musical instrument practice device that compares the performance state of a keyboard section with a model performance and scores the performance practice state.

When practicing playing a keyboard instrument, students operate the keys in accordance with the musical score, and repeat this process in order to faithfully reproduce the content expressed in the musical score.The teacher is responsible for determining the content of the performance. This is done by listening to the performance.

In other words, the teacher listens to the student's performance and instructs the student to use the fingers appropriately, to press the keys accurately, and to improve the student's sense of music. Therefore, although this type of teaching method is very effective when teachers and students conduct individual lessons on a one-on-one basis, it is effective when teaching in a group setting where one teacher has a large number of students. It is very difficult to conduct training. In addition, in order for teachers themselves to judge and score students' performance techniques, it is difficult to numerically and objectively assess the occurrence of performance errors, and they must judge the progress of performance practice solely subjectively. No.

Therefore, the direction of guidance for students' performance practice comes to depend on the subjective judgment of the teacher, making it difficult to always provide appropriate guidance that students can fully understand. This invention is
This system was created in consideration of the above points, and is designed to objectively judge students' keyboard performance, especially in response to model performances, and to display scores in a way that students can fully understand and understand. The purpose of the present invention is to provide a musical instrument practice device for playing a musical instrument.

That is, the practice device according to the present invention compares the performance information corresponding to the student's key operations with the model performance, determines whether each key operation is correct or incorrect, and counts the results of this determination. The numerical value is calculated using the number of information from the model performance as a parameter, and the correct answer rate is calculated and displayed as a score.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the schematic configuration of the storage device 11.
Model performance information is written and set for. For example, encoded information corresponding to the notes of the musical score is magnetically recorded on the musical score 12 in which an etude is written, including note marking information in the order of the notes, and this is read by the reading device 13. This is the setting to be written to.
The model performance information recorded in the storage device 11 is read out at note length intervals for each note by a readout circuit 15 that is controlled by a clock signal from a tempo oscillator 14 that generates a tempo clock signal. Musical note information corresponding to musical notes is sequentially latched and stored in the data latch circuit 16. This data latch circuit 16
The pitch information stored in is supplied to a circuit 17 for determining whether the key has been hit correctly. On the other hand, performance information expressing the pitch of the operated key is extracted from the keyboard 18 on which the student practices for practice performance in response to the key press operation, and is compared with the pitch information from the latch circuit 16 in the judgment circuit 17. At the same time, the musical tone signal is supplied to the musical tone forming circuit 19 to generate a musical tone signal corresponding to the key depression operation on the keyboard 18.

This musical tone signal is then sent to the speaker 2 via the amplifier 20.
1, and the sound is produced as the student's practice performance sound. The correct keystroke judgment circuit 17 compares the performance information from the keyboard 18 with the pitch information from the latch circuit 16 to determine whether the keystroke state on the keyboard 18 is correct or not, and calculates information on the number of correct keystrokes. is supplied to the scoring circuit 22.

The scoring circuit 22 is supplied with parameter information of a parameter counter 23 that counts the number of information read from the storage device 11 in accordance with the data latch state in the data latch circuit 16, and correct keystrokes corresponding to the number of information are supplied to the scoring circuit 22. Compute and score numbers,
The accuracy rate is displayed on the display 24, for example, on a 100-point scale. Further, this device is provided with a keyboard 25 on the main unit side for the teacher to perform a model performance, and pitch information from the model performance on this keyboard 25 is supplied to a correct key hitting determination circuit 17.
The information can be compared with the performance information from the keyboard 18.

In this case, the correct key hit determination circuit 17 detects the number of information from the keyboard 25 and takes it out as the count information of the base counter 23. Information from the keyboard 25 is sent to a musical tone forming circuit 26.
is supplied as a signal to the speaker 28 via the amplifier 27.
It is designed to be used as a model performance sound. The tempo clock signal from the tempo oscillation sound 15 is supplied to an automatic rhythm generator 29 and read out by a readout circuit 14.
In the state in which information is read from the storage device 11, a drive command is given, an automatic rhythm sound source signal is generated, and an automatic rhythm performance sound is obtained from the speaker 21 via the amplifier 20.

That is, in the apparatus configured as described above, pitch information is read out from the storage device 11 as model performance information in response to a tempo clock signal from the tempo oscillation sound 15, for example.

At this time, the automatic rhythm generating device 29 is driven in response to the readout of the pitch information, and an automatic rhythm performance sound is obtained, and the practicing student can perform a predetermined rhythmic performance along with the automatic rhythm performance sound. The player operates the keyboard 18 based on the music score. If the performance operation on the keyboard 18 is accurate in accordance with the musical score, the correct key hitting judgment circuit 17 determines the timing of the pitch information supplied from the data latch circuit 16 and the performance information obtained from the keyboard 18. The keys match in terms of pitch, note length, and note length, and it is determined that the keystroke is correct.

Then, the state of the number of correct keystrokes judged by the judgment circuit 17 is calculated in the scoring circuit 22 in accordance with the count value of the parameter counter 23, and the scoring result is displayed on the display 24 as objective information for students practicing. It is something that can be informed. Further, when the teacher performs a model performance on the keyboard 25, the students operate their own keyboards 18 in accordance with the model performance, and the students are graded in comparison with the teacher's model performance.

FIG. 2 shows the readout circuit 14 of the storage device 11 and its related parts in detail.
The signal is supplied to the latch storage unit 16a constituting the data storage unit 6, and is also supplied to the latch storage unit 301 for read control.

A detection signal from a UK mark detection circuit 16b that detects a UK mark expressing pitch (UK) information from read information is supplied to the latch storage unit 16a as a latch command, and the latch storage unit 16a receives the UK mark information. Select and memorize only. In this case, the detection signal from the UK mark detection circuit 16b is detected by the one-shot circuit 16c, and the delay circuit 1 consisting of a delayed flip-flop or the like is detected.
The signal AΔ1 is taken out via 6d. This signal AΔ1 is used as a key-off signal corresponding to the musical notes and rests read from the storage device 11. Further, the existence of a bit in the read signal is detected by the OR circuit 16e, the output signal from the OR circuit 16e and the detection signal from the UK mark detection circuit 16b is supplied to the AND circuit 16f, and the AND circuit 16f outputs musical note information. A signal is extracted in response to the readout. The output signal from the AND circuit 16f is made into a pulse waveform by a one-shot circuit 16g, and is taken out as a signal AΔ2 corresponding to key-on via a delay circuit 16h. Here, the format of the model performance information stored in the storage device 11 is a combination of UK information corresponding to a note and note length information representing the note length, as shown in FIG. The addresses are set and arranged in series, and each piece of information consists of, for example, 8 bits, with the first 2 bits being UK information,
It consists of a UK mark that separates note length information and a note length mark, and the remaining 6 bits constitute a pitch key code and a numerical code that represents note length.

Then, one song is stored sequentially according to the state of the notes, and an end code (FINISH) is written and set at the topmost position.Here, the UK information of the part corresponding to the rest is as follows:
It is composed of all "0"s, so that the AND circuit 16f is in a state where a detection signal is obtained corresponding to each note except for a rest mark. The latch storage unit 3 supplies the detection signal from the note length mark detection circuit 30a from the storage device 11 as a latch command so that the read note length information is latched and stored.

The code length information stored in the latch storage section 30 is stored in the comparison circuit 31.
is supplied to the code length counter 32, and is compared with the counted value of the note length counter 32, and when they match, an output signal EQ is generated. Note length counter 3
2 is reset by the detection signal of the note length mark detection circuit 30a and counts the tempo clock signal from the tempo oscillator 15 described above, and from the time the note length mark is detected, the time corresponding to the latched note length information is counted. When , the equal output signal EQ is generated. Comparison circuit 31
The equal signal EQ generated when the symbol time elapses from , is converted into a differentiated pulse signal by the differentiating circuit 33 , and is set in the flip-flop circuit 35 via the OR circuit 34 .

The OR circuit 34 is also supplied with a differential pulse signal generated from the differential circuit 37 when the start command switch 36 is turned on.
When set to 4 outputs, a gate signal is given to the AND circuit 42, the system clock ◇ is taken out, and the address counter 38 is incremented. This address counter 38 is reset and initialized by the output signal from the OR circuit 39 which is supplied with the signal from the differentiating circuit 37, and the address information corresponding to the counted value is used to address the readout address of the storage device 11. Specify. A flip-flop circuit 35 controls the increment of this address counter 38, and a note length mark detection circuit 3.
Reset control is performed by the detection signal from 0a. The output pulse signal of the differentiating circuit 37 corresponding to the operation of the start command switch 36 is used as a start signal "STRT" for initial setting at the time of start, and also provides a reset command to the flip-flop circuit 401.

This flip-flop circuit 40 is set by a detection signal from an end code detection circuit 41 that detects when an end code is read out from the storage device 11. The set power signal of the flip-flop circuit 40 is supplied to the OR circuit 39 to reset and hold the address counter 38, and the output signal at the time of reset is used as a start signal to drive the automatic rhythm generator 29 described above. The rhythm generator 29 is controlled to generate an automatic rhythm sound source signal. That is, when the start command switch 36 is operated, the address counter 38 is reset and initialized by the corresponding output pulse signal from the differentiating circuit 37, and the flip-flop circuit 35 is set via the OR circuit 34. and gives a gate signal to the AND circuit 42.

Then, the address counter 38 is incremented by the clock, and the stored information in the storage device 11 is read from the first address. That is, the UK information "UK[1}" at the first address in the format shown in FIG. 3 is first read out, and then
The UK information is latched and stored in the latch storage section 16a in response to a command from the K mark detection circuit 16b. In this case, UK
The signal AΔ1 is generated in response to the detection signal from the mark detection circuit 16b, and if the information "UK'1" corresponds to a musical note, the signal AΔ1 is generated in response to the detection signal from the OR circuit 16e. A signal is generated from the AND circuit 16f, and a signal AΔ2 is also generated. In this way, the information “UK[1}
'' is read out, the note length information ``LENOTHm'' is then read out from the storage device 11, and the note length information is stored and held in the latch storage section 3 by the detection signal from the code mark detection circuit 30a. .

At the same time, with the detection signal from the note length mark detection circuit 30a,
The flip-flop circuit 35 is reset, the gate of the AND circuit 42 is closed, and the counting of the address counter 38 is stopped, thereby stopping further reading from the storage device 11. Also, the note length counter 32 is reset, and the note length counter 32 counts the tempo clock signal from the time the note length information is read out.After the time corresponding to the code information has elapsed, the count value of this counter 32 is latched. A state is reached in which the stored code length information in the storage unit 30 matches, and the comparison circuit 31 generates an equal output signal EQ. When the signal EQ is generated from the comparator circuit 31, the flip-flop circuit 35 is set again by the output signal from the differentiating circuit 33, and a gate signal is given to the AND circuit 42, so that the address counter 38
will begin to advance again.

That is, the next UK information "UK■" is read from the storage device 11, and the above-described read operation is repeated. Thereafter, the UK information including the rest mark is sequentially read out from the storage device 11 at corresponding mark length intervals, and signals A△1 and A△2 are generated in response to this.
An end code is read in response to completion of reading all UK information. That is, an output signal is generated from the end code detection circuit 41, sets the flip-flop circuit 40, resets and holds the address counter 38, and stores the memory device 1.
The reading of the model performance information from No. 1 is stopped and completed, and at the same time, the rhythm start signal is cut off to stop the automatic rhythm performance. FIG. 4 shows in detail the configuration of the scoring section after the correct keystroke judgment circuit 17. Signals A△2 and A△1 corresponding to the model performance information are sent to the first and second population counters, respectively. 23a and 23b perform counting, and generate first and second parameter information BOSUI and BOSU2, respectively.

The parameter counters 23a and 23b are each initialized by a start signal STRT. Furthermore, performance information corresponding to key operations from the learning keyboard 18 is supplied to a comparison circuit 43.

This comparison circuit 43 is further supplied with performance information from the keyboard 18 via a delay circuit 44, so that the two input performance information are in a state where they do not match, that is, a key is pressed on the keyboard 18, and a pressed key is not. An output signal is generated from a comparator circuit 43 when performance information changes due to a change in key operation such as being released. The output signal from this comparison circuit 43 is used as the signal MΔ1. Further, the OR circuit 45 detects that the performance information is the pressed key, and the output signal from the OR circuit 45 is supplied to the AND circuit 46 together with the output signal from the comparison circuit 43. That is, when a key is pressed on the keyboard 18, an output signal is obtained from the AND circuit 46, and this signal is used as the signal MΔ2. That is, when the UK information shown by musical notes and rest marks in FIG. 1 and AΔ2 are in the state shown in FIG. 5, and the signal AΔ1 is generated every time UK information including a rest mark is read, and the signal AΔ2 is generated in a state excluding the rest mark.

If an accurate key operation is performed on the keyboard 18 to synchronize the reading of information from the storage device 11 in accordance with the musical score, the signals A△1, A△ as shown in FIG.
A state is reached in which signals MΔ1 and MΔ2 are generated in synchronization with MΔ2. The above signals A△2- and M△2 are
Delay circuit 47a driven by clock TCL,
47b, the signals of the respective input/output devices are detected by OR circuits 48a and 48b, and the signals A△2 and M△2 are each converted into a signal with a width equivalent to two frequencies of the tempo clock TCL, and the AND circuit 49 supply to. That is, signal A
△2 and M△2 are compared in timing with a tolerance width corresponding to two frequencies of the clock signal TCL, and when the signal M△2 is generated within the above tolerance range with respect to the signal A△2, an output signal is output from the AND circuit 49. is generated, and this AND circuit 49
The output signal from is counted by a counter 50a which is initialized by a start signal STRT. This counter 50a
The count value information is extracted as AI and the first
Arithmetic circuit 5 supplied with parameter information "BOSU[11"]
Calculated in 1a, timing correct answer rate information "TEM21"
, and the score is displayed on the display 24a as a timing correct answer rate. That is, when a key is operated on the keyboard 18 at the rhythm timing expressed in the musical score, a score is displayed as correct timing. UK latched in the latch storage section 16a
The information is supplied to the comparison circuit 52 together with performance information associated with key operations on the keyboard 18.

That is, when a key with a pitch corresponding to the UK information is operated on the keyboard 18, the comparison circuit 52 outputs an equal signal EQ.
This signal EQ is sent to a flip-flop via a delay circuit 53 driven by a clock TCL. A set command is given to the top circuit 54. This flip-flop circuit 54 is reset by the signal A△1 prior to the rise of the signal from the delay circuit 53, and when the operated key on the keyboard 18 is of the correct pitch, the flip-flop circuit 54 is set inverted. This is the differential circuit 5
5, it is detected as a pulse signal representing the correct pitch of the operated key. At the same time, this set state is latched into the latch circuit 57 via the delay circuit 56 with the next generated signal AΔ1. Day from differentiation circuit 54.

The correct pulse is counted by the counter 50b which is initialized by the start signal STRT, and taken out as the correct number information A2, and the arithmetic circuit 51b counts the second number corresponding to the note.
The pitch accuracy rate is calculated and displayed on the display 24b. The correct pitch rate is information TE
It is taken out as M3. Signals A△1 and A△2 are
3 bits and 4 bits each driven by clock TCL
The data is supplied to bit shift registers 58 and 59. In the shift register 59, the output signal is taken out when the first and fourth bits are "1", the flip-flop circuit 60 is set with the output signal of the first bit, and the output signal of the fourth bit is sent to the OR circuit 61. Then, the flip-flop circuit 60 is reset. That is, as shown in FIG. 5, the set output signal FI of the flip-flop circuit 60 rises one week period of the clock TCL with a delay of one week period from the rise of the signal A.DELTA.2, and becomes a signal that is delayed by three weeks period. The OR circuit 61 has a start signal STR.
T is supplied. Further, in the shift register 58, the signal at its input terminal is detected and the flip-flop circuit 6
2 is set, the third bit signal is supplied to the OR circuit 63 together with the start signal, and the flip-flop circuit 62 is reset.

That is, the set output signal F2 of the flip-flop circuit 62 rises together with the signal A.DELTA.1, as shown in FIG. 5, and is then used as a signal for the third period of the clock TCL. Further, the signals M△1 and M△2 are differentiated by differentiating circuits 64 and 65 respectively driven by a clock 4TCL having a frequency four times that of the clock TCL, and 8 bits and 10 bits are respectively driven by the clock 4TCL. The signal is supplied to the shift registers 66 and 67 of.

That is, as shown in FIG. 5, the shift register 66 generates the signal KOFF with a delay of 8 pulses (TCL) at 4 TCL from the rising edge of the signal M△1, and the shift register 67 generates the signal KOFF of the signal M△2. Clock 4 from rising
The signal K is delayed by 10 pulses in the TCL as shown in FIG.
ON is generated. The output signal KON from the shift register 67 is supplied to the AND circuit 68 together with the signal FI from the flip-flop circuit 60. A key-on coincidence signal is obtained as shown by AND in the figure. The output signal from this AND circuit 68 sets a flip-flop circuit 69. Further, the signal KOFF from the shift register 66 is transmitted to the delay circuit 70 and the OR circuit 71 driven by the clock 4TCL.
5, the flip-flop circuit 69 is reset as shown by F3 in FIG. The state will be set accordingly. A signal STRT is supplied to the OR circuit 71 so that the flip-flop circuit 69 is reset to an initial state. The set output signal F3 from the flip-flop circuit 69 is supplied to the AND circuit 72 together with the signal F2 from the flip-flop circuit 62 and the signal KOFF from the shift register 66.

That is, the note length corresponding to the generation interval of the signals A△1, A△2 and the key press interval on the keyboard 18 corresponding to the interval of the signals M△1, M△2 are set in the shift registers 59, 58. When the code length falls within the allowable range, the AND circuit 72 generates a signal LR representing the correct code length as shown in FIG.
Here, in the keyboard 18, when one key is pressed and the operation is converted to the next key, the inserted key is pressed and the signal MΔ1 is generated, and then the next key is pressed. Therefore, the output signal F3 from the flip-flop circuit 69 is generated in response to the pressing period of one key on the keyboard 18. be done.

Therefore, even if the signals A△1 and A△2 are generated synchronously, the signal A△1 corresponding to the release of the key on the keyboard 18
is used, and the AND circuit 72 compares the key depression time on the keyboard 18, that is, the note length. The correct note length signal from the AND circuit 72 is counted by a counter 50c which is initialized by the start signal STRT, and taken out as correct scale information A3.
At step c, the first parameter status information "BOSU'1" is calculated, note length accuracy rate information TEM2 is obtained, and the display 24c displays the score of note length accuracy* rate.

Further, the note length correct signal from the AND circuit 72 is sent to the AND circuit 72 along with the pitch correct signal in the latch circuit 57.
The note and note length correct signals from the AND circuit 73 are supplied to the counter 5 which is initialized by the start signal STRT.
Count at 0d.

Then, the count value information is processed by the arithmetic circuit 51d as parameter information "
80SU(2}'' and extracts it as note accuracy rate information TEN5, which is displayed on the display 24d. The timing pitch and note length name correct count information AI to A3 from the counters 50a, 50b, and 50c are added together. It is supplied to a circuit 74 for summation, and then supplied to an arithmetic circuit 50e.The arithmetic circuit 51e receives the first parameter information "BOS" from an adder circuit 75.
Parameter information obtained by adding two pieces of the first parameter information "Um" and one piece of the first parameter information "BOSUO" is supplied, and a partial positive scale rate average is calculated. The result of this calculation is taken out as information TENI, and the display 24e displays the average score of each part. In addition, the arithmetic circuits 51e, 51
The accuracy scoring information TENI~5 from a~51d is arbitrarily selected and supplied to the addition circuit 76.

The output information from this adder circuit 76 is read and stored in a delayed flip-flop group 78 each time a switch 77 is operated at the end of one performance, and the stored information is returned to the adder circuit 76 and used as addition information. Make it. That is, each time the switch 77 is operated at the end of the performance, the selected correct answer rate is sequentially added up in the adding circuit 76, and the integrated result is stored and held in the delayed flip-flop group 78. Then, this stored integration information is supplied to a division circuit 79. This division circuit 79 is supplied with the count value of a counter 80 as parameter information, and this counter 8 is incremented each time the switch 77 is operated. In this case, the counter 80 and delayed flip-flop group 78 are reset and initialized by operating the number average display start switch 81.
That is, after resetting the delayed flip-flop group 78 and the counter 80 with the start switch 81,
One of the pieces of information TEN1 to TEN5 is selected and supplied to the addition circuit 76, and the switch 77 is activated every time one piece of music is played.
By operating , the scores of a plurality of practice attempts are added, and the average score is calculated by the division circuit 79.

The average scoring result of the multiple attempts is then displayed on the display 24f. The above explanation is based on the case where the model performance information is stored in the storage device 11 and read out according to the note length. However, it is effective for students to practice playing while intuitively understanding the teacher's performance. There are cases where

In this case, the performance information from the teacher's keyboard 25 is used as the model performance information, and the same means as the means for generating the signals M△1 and M△2 shown in Fig. 4 are used. , based on the performance information from the keyboard 25, the signal A△1
, AΔ2 may be generated. That is, in this case, a score is displayed to show how well the student's performance matches the teacher's performance, which is particularly effective when teaching musical sense. Further, in this embodiment, a parameter counter is provided to score the correct answer rate, and the parameter counter is configured to accumulate the number of pieces of information as performance practice progresses.

However, when it is only necessary to know the scoring result at the final stage of one performance practice, especially when using information from the storage device 11, it is recommended to preset the parameter counter to the number of information that can be known in advance. It is okay to do so.

As described above, according to the present invention, each student's performance practice status can be scored based on exemplary performance information, and the score can be displayed in the form of accuracy rate, etc., so that the student can maintain objectivity. Students will be able to know a wide range of scoring results, receive guidance from teachers more effectively, and effectively improve the effectiveness of their practice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram schematically showing a practice device according to an embodiment of the present invention, Fig. 2 is a block diagram illustrating a storage information reading section of the above embodiment, and Fig. 3 shows the format of the storage information. 4 is a block diagram illustrating the correct answer scoring section of the above embodiment, and FIG. 5 is a signal waveform diagram illustrating the operation of FIG. 4. 11... Storage device, 14... Read circuit, 16... Data latch circuit, 17...
...Correct keystroke judgment circuit, 22...Scoring circuit, 2
3, 23a, 23b.・・・・・・Parameter counter, 24,
24a to 24e... Indicator, 25...
Teacher's keyboard, 51a to 51d...Arithmetic circuit. Figure 3 Ship chart N Rudder diagram Dimensions Ship Figure 5

Claims (1)

[Scope of Claims] 1. A model performance information source that sequentially generates performance information corresponding to a musical score in correspondence with note length, a keyboard for performance practice, performance information corresponding to performance operations on this keyboard, and the above model performance information. A judgment circuit that compares the performance information from the source and determines whether it is correct or incorrect, a parameter counter that counts the number of information from the model performance information source, and a correct answer based on the counted value of this counter and the judgment result from the judgment circuit. 1. A practice device for a keyboard instrument, comprising: an arithmetic circuit that calculates a ratio; and a display that displays the arithmetic results of the arithmetic circuit as a correct answer score. 2. The apparatus according to claim 1, wherein the judgment circuit compares timings of generation of performance information generated from a model performance information source and performance information from a keyboard to determine whether the performance information is correct or incorrect. 3. The apparatus according to claim 1, wherein the discrimination circuit compares each pitch information of the performance information issued from the model performance information source and the performance information from the keyboard to determine whether it is correct or incorrect. 4. The above-mentioned discrimination circuit compares the generation interval of performance information generated from a model performance information source with the key press time detected from the performance information from the keyboard to determine whether the note length is correct or incorrect. The device according to scope 1. 5. The device according to claim 1, wherein the population counter counts performance information every time performance information is generated from a model performance information source. 6. The device according to claim 1, wherein the parameter counter is set in advance to performance information of a model performance information source. 7. The apparatus according to claim 1, wherein the model performance information source is a master keyboard for a teacher, and the performance information of the model performance is generated in response to the teacher's performance. 8 The model performance information source is a storage device that stores performance information corresponding to each musical score so as to be read out sequentially in correspondence with note length information, and stores each performance information at note length intervals corresponding to a specified performance tempo. An apparatus according to claim 1, configured to read out. 9. The device according to claim 1, wherein the display unit adds and averages the calculation results from the calculation circuit for a plurality of exercises, and displays the average score for the exercises.